mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-07 11:26:02 +09:00
Merge commit 'ce2a8c86e69728b10c3464ca78f5cee2f0f4d5a8'
* commit 'ce2a8c86e69728b10c3464ca78f5cee2f0f4d5a8': arm64: dts: rockchip: rk3588: Add hdmitx hdcp14 ext memory arm64: configs: rockchip_linux_defconfig: enable CONFIG_DTC_SYMBOLS arm64: dts: rockchip: rk3568: add rk3568-evb8-lp4-v10 support ARM: dts: rockchip: rv1106-evb-cam: add sc3338 ARM: configs: rv1106-smart-door: enable SC230AI and SC301IOT arm64: dts: rockchip: fix timing configs of panel k350c4516t for rk3308/rk3562 evb media: rockchip: vicap fixes error of buffer state while start stream failed media: i2c: nvp6158: add g_frame_interval ops clk: rockchip: rk3328: set ddr clk with sip call Change-Id: I231375375df56506d8014984e64b8460fc5bc0a0
This commit is contained in:
Tao Huang
@@ -1,6 +1,6 @@
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||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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||||
/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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||||
*/
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||||
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||||
@@ -45,6 +45,11 @@
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||||
remote-endpoint = <&jx_k17_out>;
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data-lanes = <1 2>;
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};
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csi_dphy_input5: endpoint@5 {
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reg = <5>;
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remote-endpoint = <&sc3338_out>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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@@ -110,6 +115,28 @@
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};
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};
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sc3338: sc3338@30 {
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compatible = "smartsens,sc3338";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru MCLK_REF_MIPI0>;
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clock-names = "xvclk";
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reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipi_refclk_out0>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "FKO1";
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rockchip,camera-module-lens-name = "30IRC-F16";
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port {
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sc3338_out: endpoint {
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remote-endpoint = <&csi_dphy_input5>;
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data-lanes = <1 2>;
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};
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||||
};
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};
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sc4336: sc4336@30 {
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compatible = "smartsens,sc4336";
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status = "okay";
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@@ -29,6 +29,8 @@ CONFIG_SPI=y
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CONFIG_USB_SUPPORT=y
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CONFIG_VIDEO_GC2093=y
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CONFIG_VIDEO_SC035GS=y
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CONFIG_VIDEO_SC230AI=y
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CONFIG_VIDEO_SC301IOT=y
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CONFIG_VIDEO_SC3338=y
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CONFIG_WIRELESS=y
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CONFIG_WLAN=y
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@@ -233,6 +235,7 @@ CONFIG_MPILIB=y
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# CONFIG_MTD_MCHP23K256 is not set
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# CONFIG_MTD_SPI_NAND is not set
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CONFIG_MTD_SPI_NOR=m
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# CONFIG_MTD_SPI_NOR_MISC is not set
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# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
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# CONFIG_MTD_SST25L is not set
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# CONFIG_NL80211_TESTMODE is not set
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@@ -257,8 +260,10 @@ CONFIG_RFKILL_RK=y
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CONFIG_ROCKCHIP_MBOX=y
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# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
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CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m
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# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set
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CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE=y
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# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
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# CONFIG_RPMSG_ROCKCHIP is not set
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# CONFIG_RTC_DRV_DS1302 is not set
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# CONFIG_RTC_DRV_DS1305 is not set
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# CONFIG_RTC_DRV_DS1343 is not set
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@@ -161,6 +161,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10.dtb
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||||
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||||
@@ -45,147 +45,171 @@
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||||
default-brightness-level = <200>;
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};
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panel: panel {
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compatible = "simple-panel";
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bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
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backlight = <&backlight>;
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enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
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enable-delay-ms = <20>;
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reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
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reset-delay-ms = <10>;
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prepare-delay-ms = <20>;
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||||
unprepare-delay-ms = <20>;
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disable-delay-ms = <20>;
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/* spi-sdo-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; */
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spi-sdi-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
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spi-scl-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
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spi-cs-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
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width-mm = <217>;
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height-mm = <136>;
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status = "okay";
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spi_gpio: spi-gpio {
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compatible = "spi-gpio";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_init_cmd>;
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rockchip,cmd-type = "spi";
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pinctrl-0 = <&spi_pins>;
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spi-delay-us = <10>;
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status = "okay";
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/* type:0 is cmd, 1 is data */
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panel-init-sequence = [
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||||
/* type delay num val1 val2 val3 */
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00 00 01 e0
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01 00 01 00
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01 00 01 07
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01 00 01 0f
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||||
01 00 01 0d
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||||
01 00 01 1b
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01 00 01 0a
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01 00 01 3c
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||||
01 00 01 78
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||||
01 00 01 4a
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01 00 01 07
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||||
01 00 01 0e
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01 00 01 09
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01 00 01 1b
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01 00 01 1e
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01 00 01 0f
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||||
00 00 01 e1
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01 00 01 00
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01 00 01 22
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01 00 01 24
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01 00 01 06
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||||
01 00 01 12
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||||
01 00 01 07
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||||
01 00 01 36
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||||
01 00 01 47
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||||
01 00 01 47
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||||
01 00 01 06
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01 00 01 0a
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||||
01 00 01 07
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||||
01 00 01 30
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01 00 01 37
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01 00 01 0f
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sck-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
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miso-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
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mosi-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
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num-chipselects = <1>;
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00 00 01 c0
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01 00 01 10
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01 00 01 10
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/*
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* 320x480 RGB/MCU screen K350C4516T
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*/
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panel: panel {
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compatible = "simple-panel-spi";
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reg = <0>;
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bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
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backlight = <&backlight>;
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enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
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enable-delay-ms = <20>;
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reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
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reset-delay-ms = <10>;
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prepare-delay-ms = <20>;
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unprepare-delay-ms = <20>;
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disable-delay-ms = <20>;
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init-delay-ms = <10>;
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width-mm = <217>;
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height-mm = <136>;
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rockchip,cmd-type = "spi";
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status = "okay";
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00 00 01 c1
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01 00 01 41
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// type:0 is cmd, 1 is data
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panel-init-sequence = [
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/* type delay num val1 val2 val3 */
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00 00 01 e0
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01 00 01 00
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01 00 01 07
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01 00 01 0f
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01 00 01 0d
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01 00 01 1b
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01 00 01 0a
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01 00 01 3c
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01 00 01 78
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01 00 01 4a
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01 00 01 07
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01 00 01 0e
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01 00 01 09
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01 00 01 1b
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01 00 01 1e
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01 00 01 0f
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00 00 01 e1
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01 00 01 00
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01 00 01 22
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01 00 01 24
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01 00 01 06
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01 00 01 12
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01 00 01 07
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01 00 01 36
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01 00 01 47
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01 00 01 47
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01 00 01 06
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01 00 01 0a
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01 00 01 07
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01 00 01 30
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01 00 01 37
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01 00 01 0f
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00 00 01 c5
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01 00 01 00
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01 00 01 22
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01 00 01 80
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00 00 01 c0
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01 00 01 10
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01 00 01 10
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00 00 01 36
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01 00 01 48
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00 00 01 c1
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01 00 01 41
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00 00 01 3a //interface pixel format
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01 00 01 66 // bpp cfg
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// 3 11
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// 16 55
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// 18 66
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// 24 77
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00 00 01 c5
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01 00 01 00
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01 00 01 22
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01 00 01 80
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||||
00 00 01 b0 /* interface mode control */
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01 00 01 00
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00 00 01 36
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01 00 01 48
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00 00 01 b1 /* frame rate 60hz */
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01 00 01 a0
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01 00 01 11
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00 00 01 b4
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01 00 01 02
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00 00 01 B6
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01 00 01 32
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01 00 01 02
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00 00 01 3a
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01 00 01 66 /*
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||||
* interface pixel format:
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* 66 for RGB666(18bit)
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*/
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||||
|
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00 00 01 b7
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01 00 01 c6
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00 00 01 b0
|
||||
01 00 01 00
|
||||
|
||||
00 00 01 be
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01 00 01 00
|
||||
01 00 01 04
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||||
00 00 01 b1
|
||||
01 00 01 a0 /*
|
||||
* frame rate control:
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* a0 (60hz) for RGB666(18bit)
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||||
*/
|
||||
01 00 01 11
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00 00 01 b4
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01 00 01 02
|
||||
00 00 01 B6
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01 00 01 32 /*
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||||
* display function control:
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* 32 for RGB
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||||
* 02 for MCU
|
||||
*/
|
||||
01 00 01 02
|
||||
|
||||
00 00 01 e9
|
||||
01 00 01 00
|
||||
00 00 01 b7
|
||||
01 00 01 c6
|
||||
|
||||
00 00 01 f7
|
||||
01 00 01 a9
|
||||
01 00 01 51
|
||||
01 00 01 2c
|
||||
01 00 01 82
|
||||
00 00 01 be
|
||||
01 00 01 00
|
||||
01 00 01 04
|
||||
|
||||
00 78 01 11
|
||||
00 00 01 29
|
||||
];
|
||||
00 00 01 e9
|
||||
01 00 01 00
|
||||
|
||||
panel-exit-sequence = [
|
||||
/* type delay num val1 val2 val3 */
|
||||
00 0a 01 28
|
||||
00 78 01 10
|
||||
];
|
||||
00 00 01 f7
|
||||
01 00 01 a9
|
||||
01 00 01 51
|
||||
01 00 01 2c
|
||||
01 00 01 82
|
||||
|
||||
display-timings {
|
||||
native-mode = <&kd050fwfba002_timing>;
|
||||
00 78 01 11
|
||||
00 00 01 29
|
||||
];
|
||||
|
||||
kd050fwfba002_timing: timing0 {
|
||||
clock-frequency = <94081500>;
|
||||
hactive = <320>;
|
||||
vactive = <480>;
|
||||
hback-porch = <10>;
|
||||
hfront-porch = <5>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <5>;
|
||||
hsync-len = <10>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <0>;
|
||||
panel-exit-sequence = [
|
||||
//type delay num val1 val2 val3
|
||||
00 0a 01 28
|
||||
00 78 01 10
|
||||
];
|
||||
|
||||
display-timings {
|
||||
native-mode = <&kd050fwfba002_timing>;
|
||||
|
||||
kd050fwfba002_timing: timing0 {
|
||||
/*
|
||||
* 10453500 for RGB666(18bit)
|
||||
*/
|
||||
clock-frequency = <10453500>;
|
||||
hactive = <320>;
|
||||
vactive = <480>;
|
||||
hback-porch = <10>;
|
||||
hfront-porch = <5>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <5>;
|
||||
hsync-len = <10>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <&rgb_out_panel>;
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <&rgb_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -196,9 +220,11 @@
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
spi_panel {
|
||||
spi_init_cmd: spi-init-cmd {
|
||||
soft_spi {
|
||||
spi_pins: spi-pins {
|
||||
rockchip,pins =
|
||||
/* spi sdo */
|
||||
<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
/* spi sdi */
|
||||
<1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
/* spi scl */
|
||||
@@ -236,14 +262,4 @@
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
|
||||
mcu-timing {
|
||||
mcu-pix-total = <9>;
|
||||
mcu-cs-pst = <1>;
|
||||
mcu-cs-pend = <8>;
|
||||
mcu-rw-pst = <2>;
|
||||
mcu-rw-pend = <5>;
|
||||
|
||||
mcu-hold-mode = <0>; // default set to 0
|
||||
};
|
||||
};
|
||||
|
||||
@@ -45,8 +45,40 @@
|
||||
default-brightness-level = <200>;
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "simple-panel";
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x800000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rgb {
|
||||
status = "okay";
|
||||
rockchip,data-sync-bypass;
|
||||
|
||||
/*
|
||||
* 320x480 RGB/MCU screen K350C4516T
|
||||
*/
|
||||
mcu_panel: mcu-panel {
|
||||
/*
|
||||
* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
|
||||
* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
|
||||
*/
|
||||
bus-format = <MEDIA_BUS_FMT_RGB565_1X16>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
@@ -59,8 +91,6 @@
|
||||
disable-delay-ms = <20>;
|
||||
width-mm = <217>;
|
||||
height-mm = <136>;
|
||||
status = "okay";
|
||||
rockchip,cmd-type = "mcu";
|
||||
|
||||
// type:0 is cmd, 1 is data
|
||||
panel-init-sequence = [
|
||||
@@ -113,23 +143,31 @@
|
||||
00 00 01 36
|
||||
01 00 01 48
|
||||
|
||||
00 00 01 3a //interface pixel format
|
||||
01 00 01 55 // bpp cfg
|
||||
// 3 11
|
||||
// 16 55
|
||||
// 18 66
|
||||
// 24 77
|
||||
00 00 01 3a
|
||||
01 00 01 55 /*
|
||||
* interface pixel format:
|
||||
* 66 for RGB3x8(8bit)
|
||||
* 55 for RGB565(16bit)
|
||||
*/
|
||||
|
||||
00 00 01 b0 //interface mode control
|
||||
00 00 01 b0
|
||||
01 00 01 00
|
||||
|
||||
00 00 01 b1 //frame rate 60hz
|
||||
01 00 01 a0
|
||||
00 00 01 b1
|
||||
01 00 01 a0 /*
|
||||
* frame rate control:
|
||||
* 70 (45hz) for RGB3x8(8bit)
|
||||
* a0 (60hz) for RGB565(16bit)
|
||||
*/
|
||||
01 00 01 11
|
||||
00 00 01 b4
|
||||
01 00 01 02
|
||||
00 00 01 B6
|
||||
01 00 01 02
|
||||
01 00 01 02 /*
|
||||
* display function control:
|
||||
* 32 for RGB
|
||||
* 02 for MCU
|
||||
*/
|
||||
01 00 01 02
|
||||
|
||||
00 00 01 b7
|
||||
@@ -163,7 +201,11 @@
|
||||
native-mode = <&kd050fwfba002_timing>;
|
||||
|
||||
kd050fwfba002_timing: timing0 {
|
||||
clock-frequency = <94081500>;
|
||||
/*
|
||||
* 7840125 for frame rate 45Hz
|
||||
* 10453500 for frame rate 60Hz
|
||||
*/
|
||||
clock-frequency = <10453500>;
|
||||
hactive = <320>;
|
||||
vactive = <480>;
|
||||
hback-porch = <10>;
|
||||
@@ -186,35 +228,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x800000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_rgb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rgb {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
rgb_out: port@1 {
|
||||
reg = <1>;
|
||||
@@ -229,15 +242,32 @@
|
||||
};
|
||||
};
|
||||
|
||||
&route_rgb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Default config is as follows:
|
||||
*
|
||||
* mcu-pix-total = <9>;
|
||||
* mcu-cs-pst = <1>;
|
||||
* mcu-cs-pend = <8>;
|
||||
* mcu-rw-pst = <2>;
|
||||
* mcu-rw-pend = <5>;
|
||||
* mcu-hold-mode = <0>; // default set to 0
|
||||
*
|
||||
* To increase the frame rate, reduce all parameters because
|
||||
* the max dclk rate of mcu is 150M in rk3308.
|
||||
*/
|
||||
mcu-timing {
|
||||
mcu-pix-total = <9>;
|
||||
mcu-pix-total = <5>;
|
||||
mcu-cs-pst = <1>;
|
||||
mcu-cs-pend = <8>;
|
||||
mcu-cs-pend = <4>;
|
||||
mcu-rw-pst = <2>;
|
||||
mcu-rw-pend = <5>;
|
||||
mcu-rw-pend = <3>;
|
||||
|
||||
mcu-hold-mode = <0>; // default set to 0
|
||||
};
|
||||
|
||||
@@ -47,8 +47,8 @@
|
||||
rockchip,data-sync-bypass;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* rgb3x8_pins_m0/rgb3x8_pins_m1 for serial mcu
|
||||
* rgb565_pins for parallel mcu
|
||||
* rgb3x8_pins_m0/rgb3x8_pins_m1 for RGB3x8(8bit)
|
||||
* rgb565_pins for RGB565(16bit)
|
||||
*/
|
||||
pinctrl-0 = <&rgb565_pins>;
|
||||
|
||||
@@ -57,19 +57,19 @@
|
||||
*/
|
||||
mcu_panel: mcu-panel {
|
||||
/*
|
||||
* MEDIA_BUS_FMT_RGB888_3X8 for serial mcu
|
||||
* MEDIA_BUS_FMT_RGB565_1X16 for parallel mcu
|
||||
* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
|
||||
* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
|
||||
*/
|
||||
bus-format = <MEDIA_BUS_FMT_RGB565_1X16>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
enable-delay-ms = <20>;
|
||||
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
reset-value = <0>;
|
||||
reset-delay-ms = <10>;
|
||||
prepare-delay-ms = <20>;
|
||||
unprepare-delay-ms = <20>;
|
||||
disable-delay-ms = <20>;
|
||||
init-delay-ms = <10>;
|
||||
width-mm = <217>;
|
||||
height-mm = <136>;
|
||||
|
||||
@@ -124,23 +124,31 @@
|
||||
00 00 01 36
|
||||
01 00 01 48
|
||||
|
||||
00 00 01 3a //interface pixel format
|
||||
01 00 01 55 // bpp cfg
|
||||
// 3 11
|
||||
// 16 55
|
||||
// 18 66
|
||||
// 24 77
|
||||
00 00 01 3a
|
||||
01 00 01 55 /*
|
||||
* interface pixel format:
|
||||
* 66 for RGB3x8(8bit)
|
||||
* 55 for RGB565(16bit)
|
||||
*/
|
||||
|
||||
00 00 01 b0 //interface mode control
|
||||
00 00 01 b0
|
||||
01 00 01 00
|
||||
|
||||
00 00 01 b1 //frame rate 60hz
|
||||
01 00 01 a0
|
||||
00 00 01 b1
|
||||
01 00 01 a0 /*
|
||||
* frame rate control:
|
||||
* 70 (45hz) for RGB3x8(8bit)
|
||||
* a0 (60hz) for RGB565(16bit)
|
||||
*/
|
||||
01 00 01 11
|
||||
00 00 01 b4
|
||||
01 00 01 02
|
||||
00 00 01 B6
|
||||
01 00 01 02
|
||||
01 00 01 02 /*
|
||||
* display function control:
|
||||
* 32 for RGB
|
||||
* 02 for MCU
|
||||
*/
|
||||
01 00 01 02
|
||||
|
||||
00 00 01 b7
|
||||
@@ -174,7 +182,11 @@
|
||||
native-mode = <&kd050fwfba002_timing>;
|
||||
|
||||
kd050fwfba002_timing: timing0 {
|
||||
clock-frequency = <94081500>;
|
||||
/*
|
||||
* 7840125 for frame rate 45Hz
|
||||
* 10453500 for frame rate 60Hz
|
||||
*/
|
||||
clock-frequency = <10453500>;
|
||||
hactive = <320>;
|
||||
vactive = <480>;
|
||||
hback-porch = <10>;
|
||||
@@ -240,12 +252,27 @@
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Default config is as follows:
|
||||
*
|
||||
* mcu-pix-total = <9>;
|
||||
* mcu-cs-pst = <1>;
|
||||
* mcu-cs-pend = <8>;
|
||||
* mcu-rw-pst = <2>;
|
||||
* mcu-rw-pend = <5>;
|
||||
* mcu-hold-mode = <0>; // default set to 0
|
||||
*
|
||||
* To increase the frame rate, reduce all parameters because
|
||||
* the max dclk rate of mcu is 150M in rk3562.
|
||||
*/
|
||||
mcu-timing {
|
||||
mcu-pix-total = <9>;
|
||||
mcu-pix-total = <5>;
|
||||
mcu-cs-pst = <1>;
|
||||
mcu-cs-pend = <8>;
|
||||
mcu-cs-pend = <4>;
|
||||
mcu-rw-pst = <2>;
|
||||
mcu-rw-pend = <5>;
|
||||
mcu-rw-pend = <3>;
|
||||
|
||||
mcu-hold-mode = <0>; // default set to 0
|
||||
};
|
||||
|
||||
@@ -43,6 +43,7 @@
|
||||
prepare-delay-ms = <20>;
|
||||
unprepare-delay-ms = <20>;
|
||||
disable-delay-ms = <20>;
|
||||
init-delay-ms = <10>;
|
||||
width-mm = <217>;
|
||||
height-mm = <136>;
|
||||
rockchip,cmd-type = "spi";
|
||||
@@ -99,23 +100,29 @@
|
||||
00 00 01 36
|
||||
01 00 01 48
|
||||
|
||||
00 00 01 3a //interface pixel format
|
||||
01 00 01 66 // bpp cfg
|
||||
// 3 11
|
||||
// 16 55
|
||||
// 18 66
|
||||
// 24 77
|
||||
00 00 01 3a
|
||||
01 00 01 66 /*
|
||||
* interface pixel format:
|
||||
* 66 for RGB666(18bit)
|
||||
*/
|
||||
|
||||
00 00 01 b0 /* interface mode control */
|
||||
00 00 01 b0
|
||||
01 00 01 00
|
||||
|
||||
00 00 01 b1 /* frame rate 60hz */
|
||||
01 00 01 a0
|
||||
00 00 01 b1
|
||||
01 00 01 a0 /*
|
||||
* frame rate control:
|
||||
* a0 (60hz) for RGB666(18bit)
|
||||
*/
|
||||
01 00 01 11
|
||||
00 00 01 b4
|
||||
01 00 01 02
|
||||
00 00 01 B6
|
||||
01 00 01 32
|
||||
01 00 01 32 /*
|
||||
* display function control:
|
||||
* 32 for RGB
|
||||
* 02 for MCU
|
||||
*/
|
||||
01 00 01 02
|
||||
|
||||
00 00 01 b7
|
||||
@@ -148,6 +155,9 @@
|
||||
native-mode = <&kd050fwfba002_timing>;
|
||||
|
||||
kd050fwfba002_timing: timing0 {
|
||||
/*
|
||||
* 10453500 for RGB666(18bit)
|
||||
*/
|
||||
clock-frequency = <10453500>;
|
||||
hactive = <320>;
|
||||
vactive = <480>;
|
||||
|
||||
17
arch/arm64/boot/dts/rockchip/rk3568-evb8-lp4-v10-linux.dts
Normal file
17
arch/arm64/boot/dts/rockchip/rk3568-evb8-lp4-v10-linux.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3568-evb8-lp4-v10.dtsi"
|
||||
#include "rk3568-linux.dtsi"
|
||||
#include <dt-bindings/display/rockchip_vop.h>
|
||||
|
||||
&vp0 {
|
||||
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>;
|
||||
};
|
||||
|
||||
&vp1 {
|
||||
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER1>;
|
||||
};
|
||||
20
arch/arm64/boot/dts/rockchip/rk3568-evb8-lp4-v10.dts
Normal file
20
arch/arm64/boot/dts/rockchip/rk3568-evb8-lp4-v10.dts
Normal file
@@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3568-evb8-lp4-v10.dtsi"
|
||||
#include "rk3568-android.dtsi"
|
||||
|
||||
&bt_sco {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bt_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s3_2ch {
|
||||
status = "okay";
|
||||
};
|
||||
37
arch/arm64/boot/dts/rockchip/rk3568-evb8-lp4-v10.dtsi
Normal file
37
arch/arm64/boot/dts/rockchip/rk3568-evb8-lp4-v10.dtsi
Normal file
@@ -0,0 +1,37 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-evb1-ddr4-v10.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3568 EVB8 LP4 V10 Board";
|
||||
compatible = "rockchip,rk3568-evb8-lp4-v10", "rockchip,rk3568";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
/delete-node/ tcs4525@1c;
|
||||
|
||||
vdd_cpu: rk8600@40 {
|
||||
compatible = "rockchip,rk8600";
|
||||
reg = <0x40>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "rk860x-reg";
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
rockchip,suspend-voltage-selector = <1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -361,7 +361,7 @@
|
||||
|
||||
hdmi1: hdmi@fdea0000 {
|
||||
compatible = "rockchip,rk3588-dw-hdmi";
|
||||
reg = <0x0 0xfdea0000 0x0 0x20000>;
|
||||
reg = <0x0 0xfdea0000 0x0 0x10000>, <0x0 0xfdeb0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@@ -5037,7 +5037,7 @@
|
||||
|
||||
hdmi0: hdmi@fde80000 {
|
||||
compatible = "rockchip,rk3588-dw-hdmi";
|
||||
reg = <0x0 0xfde80000 0x0 0x20000>;
|
||||
reg = <0x0 0xfde80000 0x0 0x10000>, <0x0 0xfde90000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@@ -140,6 +140,7 @@ CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_DTC_SYMBOLS=y
|
||||
CONFIG_ZRAM=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
||||
@@ -317,14 +317,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
|
||||
RK3328_CLKGATE_CON(14), 1, GFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IS_CRITICAL,
|
||||
RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
RK3328_CLKGATE_CON(0), 4, GFLAGS),
|
||||
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IS_CRITICAL,
|
||||
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
|
||||
RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
|
||||
ROCKCHIP_DDRCLK_SIP_V2),
|
||||
|
||||
GATE(0, "clk_ddrmsch", "sclk_ddrc", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 6, GFLAGS),
|
||||
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IS_CRITICAL,
|
||||
GATE(0, "clk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 5, GFLAGS),
|
||||
GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
GATE(0, "aclk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 4, GFLAGS),
|
||||
GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(0), 6, GFLAGS),
|
||||
|
||||
@@ -924,6 +924,17 @@ static int nvp6158_set_fmt(struct v4l2_subdev *sd,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nvp6158_g_frame_interval(struct v4l2_subdev *sd,
|
||||
struct v4l2_subdev_frame_interval *fi)
|
||||
{
|
||||
struct nvp6158 *nvp6158 = to_nvp6158(sd);
|
||||
const struct nvp6158_framesize *size = nvp6158->frame_size;
|
||||
|
||||
fi->interval = size->max_fps;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void nvp6158_get_module_inf(struct nvp6158 *nvp6158,
|
||||
struct rkmodule_inf *inf)
|
||||
{
|
||||
@@ -1174,6 +1185,7 @@ static const struct dev_pm_ops nvp6158_pm_ops = {
|
||||
static const struct v4l2_subdev_video_ops nvp6158_video_ops = {
|
||||
.s_stream = nvp6158_stream,
|
||||
.querystd = nvp6158_querystd,
|
||||
.g_frame_interval = nvp6158_g_frame_interval,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_pad_ops nvp6158_subdev_pad_ops = {
|
||||
|
||||
@@ -5025,10 +5025,12 @@ void rkcif_do_stop_stream(struct rkcif_stream *stream,
|
||||
dev->wait_line = 0;
|
||||
stream->is_line_wake_up = false;
|
||||
}
|
||||
tasklet_disable(&stream->vb_done_tasklet);
|
||||
if (can_reset && hw_dev->dummy_buf.vaddr)
|
||||
rkcif_destroy_dummy_buf(stream);
|
||||
}
|
||||
if (can_reset && hw_dev->dummy_buf.vaddr)
|
||||
rkcif_destroy_dummy_buf(stream);
|
||||
if (mode == RKCIF_STREAM_MODE_CAPTURE)
|
||||
tasklet_disable(&stream->vb_done_tasklet);
|
||||
|
||||
stream->cur_stream_mode &= ~mode;
|
||||
INIT_LIST_HEAD(&stream->vb_done_list);
|
||||
v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished, dma_en 0x%x\n", stream->id, stream->dma_en);
|
||||
@@ -6140,8 +6142,10 @@ int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode)
|
||||
}
|
||||
mutex_unlock(&hw_dev->dev_lock);
|
||||
|
||||
if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
|
||||
if (mode == RKCIF_STREAM_MODE_CAPTURE)
|
||||
tasklet_enable(&stream->vb_done_tasklet);
|
||||
|
||||
if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
|
||||
ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
|
||||
if (ret < 0) {
|
||||
v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
|
||||
@@ -6159,7 +6163,7 @@ int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode)
|
||||
rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
|
||||
ret = dev->pipe.set_stream(&dev->pipe, true);
|
||||
if (ret < 0)
|
||||
goto runtime_put;
|
||||
goto destroy_buf;
|
||||
}
|
||||
}
|
||||
if (dev->chip_id >= CHIP_RK1808_CIF) {
|
||||
@@ -6175,7 +6179,7 @@ int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode)
|
||||
}
|
||||
|
||||
if (ret < 0)
|
||||
goto runtime_put;
|
||||
goto destroy_buf;
|
||||
|
||||
if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
|
||||
ret = video_device_pipeline_start(&node->vdev, &dev->pipe.pipe);
|
||||
@@ -6221,15 +6225,19 @@ stop_stream:
|
||||
rkcif_stream_stop(stream);
|
||||
pipe_stream_off:
|
||||
dev->pipe.set_stream(&dev->pipe, false);
|
||||
runtime_put:
|
||||
pm_runtime_put_sync(dev->dev);
|
||||
|
||||
destroy_buf:
|
||||
if (stream->next_buf)
|
||||
vb2_buffer_done(&stream->next_buf->vb.vb2_buf,
|
||||
VB2_BUF_STATE_QUEUED);
|
||||
if (mode == RKCIF_STREAM_MODE_CAPTURE)
|
||||
tasklet_disable(&stream->vb_done_tasklet);
|
||||
if (stream->curr_buf)
|
||||
vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
|
||||
VB2_BUF_STATE_QUEUED);
|
||||
list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
|
||||
if (stream->next_buf &&
|
||||
stream->next_buf != stream->curr_buf)
|
||||
list_add_tail(&stream->next_buf->queue, &stream->buf_head);
|
||||
|
||||
stream->curr_buf = NULL;
|
||||
stream->next_buf = NULL;
|
||||
atomic_set(&stream->buf_cnt, 0);
|
||||
while (!list_empty(&stream->buf_head)) {
|
||||
struct rkcif_buffer *buf;
|
||||
|
||||
|
||||
@@ -622,36 +622,39 @@ static int sditf_start_stream(struct sditf_priv *priv)
|
||||
struct rkcif_device *cif_dev = priv->cif_dev;
|
||||
struct v4l2_subdev_format fmt;
|
||||
unsigned int mode = RKCIF_STREAM_MODE_TOISP;
|
||||
int ret = 0;
|
||||
|
||||
sditf_check_capture_mode(cif_dev);
|
||||
sditf_get_set_fmt(&priv->sd, NULL, &fmt);
|
||||
if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
|
||||
if (priv->toisp_inf.link_mode == TOISP0) {
|
||||
sditf_channel_enable(priv, 0);
|
||||
ret = sditf_channel_enable(priv, 0);
|
||||
} else if (priv->toisp_inf.link_mode == TOISP1) {
|
||||
sditf_channel_enable(priv, 1);
|
||||
ret = sditf_channel_enable(priv, 1);
|
||||
} else if (priv->toisp_inf.link_mode == TOISP_UNITE) {
|
||||
sditf_channel_enable(priv, 0);
|
||||
sditf_channel_enable(priv, 1);
|
||||
ret = sditf_channel_enable(priv, 0);
|
||||
ret |= sditf_channel_enable(priv, 1);
|
||||
}
|
||||
mode = RKCIF_STREAM_MODE_TOISP;
|
||||
} else if (priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
|
||||
mode = RKCIF_STREAM_MODE_TOISP_RDBK;
|
||||
}
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (priv->hdr_cfg.hdr_mode == NO_HDR ||
|
||||
priv->hdr_cfg.hdr_mode == HDR_COMPR) {
|
||||
rkcif_do_start_stream(&cif_dev->stream[0], mode);
|
||||
ret = rkcif_do_start_stream(&cif_dev->stream[0], mode);
|
||||
} else if (priv->hdr_cfg.hdr_mode == HDR_X2) {
|
||||
rkcif_do_start_stream(&cif_dev->stream[0], mode);
|
||||
rkcif_do_start_stream(&cif_dev->stream[1], mode);
|
||||
ret = rkcif_do_start_stream(&cif_dev->stream[0], mode);
|
||||
ret |= rkcif_do_start_stream(&cif_dev->stream[1], mode);
|
||||
} else if (priv->hdr_cfg.hdr_mode == HDR_X3) {
|
||||
rkcif_do_start_stream(&cif_dev->stream[0], mode);
|
||||
rkcif_do_start_stream(&cif_dev->stream[1], mode);
|
||||
rkcif_do_start_stream(&cif_dev->stream[2], mode);
|
||||
ret = rkcif_do_start_stream(&cif_dev->stream[0], mode);
|
||||
ret |= rkcif_do_start_stream(&cif_dev->stream[1], mode);
|
||||
ret |= rkcif_do_start_stream(&cif_dev->stream[2], mode);
|
||||
}
|
||||
INIT_LIST_HEAD(&priv->buf_free_list);
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sditf_stop_stream(struct sditf_priv *priv)
|
||||
@@ -713,6 +716,8 @@ static int sditf_s_stream(struct v4l2_subdev *sd, int on)
|
||||
}
|
||||
|
||||
}
|
||||
if (on && ret)
|
||||
atomic_dec(&priv->stream_cnt);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -740,6 +745,7 @@ static int sditf_s_power(struct v4l2_subdev *sd, int on)
|
||||
} else {
|
||||
v4l2_pipeline_pm_put(&node->vdev.entity);
|
||||
pm_runtime_put_sync(cif_dev->dev);
|
||||
priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
|
||||
}
|
||||
v4l2_info(&node->vdev, "s_power %d, entity use_count %d\n",
|
||||
on, node->vdev.entity.use_count);
|
||||
|
||||
Reference in New Issue
Block a user