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UPSTREAM: clk: rockchip: add 533.25MHz to rk3399 clock rates table

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We need to get the accurate 533.25MHz for the DP display.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 5c1c63f634)

Change-Id: Ib945c80451d52081683488fe410c5200622fb1c3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Xing Zheng
2016-10-21 12:03:40 +08:00
committed by Tao Huang
parent 25c7cb783d
commit 49d2f9f2a7
1 changed files with 1 additions and 0 deletions
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drivers/clk/rockchip/clk-rk3399.c
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@@ -94,6 +94,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),