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[ARM] tegra: clocks: Set all SDMMC clocks to 48MHz at boot

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48MHz is the max speed reported by present-day Tegra2 SDHCI controllers
and is the max speed we can run without adjusting for DVFS changes.

Change-Id: I3f2c23ffdfc40aebe8211688077003f09f599f1a
Signed-off-by: Todd Poynor <toddpoynor@google.com>
This commit is contained in:
Todd Poynor
2010-09-02 15:10:29 -07:00
committed by Colin Cross
parent 7e9bd8ff3f
commit 4a4af7562a
1 changed files with 5 additions and 1 deletions
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6
arch/arm/mach-tegra/common.c
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@@ -1,5 +1,5 @@
/*
* arch/arm/mach-tegra/board-harmony.c
* arch/arm/mach-tegra/common.c
*
* Copyright (C) 2010 Google, Inc.
*
@@ -46,6 +46,10 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "hclk", "sclk", 108000000, true },
{ "pclk", "hclk", 54000000, true },
{ "pll_u", "clk_m", 480000000, false },
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc2", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
{ NULL, NULL, 0, 0},
};