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media: rockchip: isp: compiled with differe hardware version

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Change-Id: Ic18a8ba5005e14f9676716fc9b089ed81bdd38b0
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2021-08-16 11:35:42 +08:00
committed by Tao Huang
parent acfebbb68f
commit 4a7a52e98c
16 changed files with 616 additions and 371 deletions
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16
drivers/media/platform/rockchip/isp/Kconfig
View File

@@ -12,8 +12,24 @@ config VIDEO_ROCKCHIP_ISP
help
Support for ISP on the rockchip SoC.
if VIDEO_ROCKCHIP_ISP
config VIDEO_ROCKCHIP_ISP_VERSION_V1X
bool "isp1 for rk1808 rk3288 rk3326 rk3368 rk3399"
default y if CPU_RK1808 || CPU_RK3288 || CPU_PX30 || CPU_RK3368 || CPU_RK3399
config VIDEO_ROCKCHIP_ISP_VERSION_V20
bool "isp20 for rv1126 and rv1109"
default y if CPU_RV1126
config VIDEO_ROCKCHIP_ISP_VERSION_V21
bool "isp21 for rk3566 and rk3568"
default y if CPU_RK3568
config VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
bool "Rockchip Image Signal Processing Thunderboot helper"
depends on ROCKCHIP_THUNDER_BOOT
help
Say y if enable thunderboot helper for isp.
endif

32
drivers/media/platform/rockchip/isp/Makefile
View File

@@ -7,24 +7,28 @@ video_rkisp-objs += hw.o \
regs.o \
common.o \
isp_stats.o \
isp_stats_v1x.o \
isp_stats_v2x.o \
isp_stats_v21.o \
isp_params.o \
isp_params_v1x.o \
isp_params_v2x.o \
isp_params_v21.o \
capture.o \
capture_v1x.o \
capture_v20.o \
capture_v21.o \
dmarx.o \
csi.o \
bridge.o \
isp_mipi_luma.o \
procfs.o \
videobuf2-rdma-sg.o
ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
video_rkisp-objs += rkisp_tb_helper.o
endif
video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X) += \
isp_stats_v1x.o \
isp_params_v1x.o \
capture_v1x.o
video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20) += \
isp_stats_v2x.o \
isp_params_v2x.o \
capture_v20.o \
bridge.o \
isp_mipi_luma.o
video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21) += \
isp_stats_v21.o \
isp_params_v21.o \
capture_v21.o
video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) += rkisp_tb_helper.o

11
drivers/media/platform/rockchip/isp/bridge.h
View File

@@ -67,6 +67,7 @@ struct rkisp_bridge_device {
bool en;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20)
int rkisp_register_bridge_subdev(struct rkisp_device *dev,
struct v4l2_device *v4l2_dev);
void rkisp_unregister_bridge_subdev(struct rkisp_device *dev);
@@ -76,6 +77,12 @@ void rkisp_bridge_sendtopp_buffer(struct rkisp_device *dev, u32 dev_id, u32 buf_
void rkisp_bridge_save_spbuf(struct rkisp_device *dev, struct rkisp_buffer *sp_buf);
void rkisp_bridge_stop_spstream(struct rkisp_device *dev);
void rkisp_bridge_update_mi(struct rkisp_device *dev);
void rkisp_get_bridge_sd(struct platform_device *dev,
struct v4l2_subdev **sd);
void rkisp_get_bridge_sd(struct platform_device *dev, struct v4l2_subdev **sd);
#else
static inline int rkisp_register_bridge_subdev(struct rkisp_device *dev, struct v4l2_device *v4l2_dev) { return 0; }
static inline void rkisp_unregister_bridge_subdev(struct rkisp_device *dev) {}
static inline int rkisp_bridge_get_fbcbuf_fd(struct rkisp_device *dev, struct isp2x_buf_idxfd *idxfd) { return 0; }
static inline void rkisp_bridge_update_mi(struct rkisp_device *dev) {}
#endif
#endif

336
drivers/media/platform/rockchip/isp/capture.c
View File

@@ -23,6 +23,342 @@
#define STREAM_MIN_MP_SP_INPUT_WIDTH 32
#define STREAM_MIN_MP_SP_INPUT_HEIGHT 32
static int hdr_dma_frame(struct rkisp_device *dev)
{
int max_dma;
switch (dev->hdr.op_mode) {
case HDR_FRAMEX2_DDR:
case HDR_LINEX2_DDR:
case HDR_RDBK_FRAME1:
max_dma = 1;
break;
case HDR_FRAMEX3_DDR:
case HDR_LINEX3_DDR:
case HDR_RDBK_FRAME2:
max_dma = 2;
break;
case HDR_RDBK_FRAME3:
max_dma = HDR_DMA_MAX;
break;
case HDR_LINEX2_NO_DDR:
case HDR_NORMAL:
default:
max_dma = 0;
}
return max_dma;
}
static int rkisp_create_hdr_buf(struct rkisp_device *dev)
{
int i, j, max_dma, max_buf = 1;
struct rkisp_dummy_buffer *buf;
struct rkisp_stream *stream;
u32 size;
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
size = stream->out_fmt.plane_fmt[0].sizeimage;
max_dma = hdr_dma_frame(dev);
/* hdr read back mode using base and shd address
* this support multi-buffer
*/
if (IS_HDR_RDBK(dev->hdr.op_mode)) {
if (!dev->dmarx_dev.trigger)
max_buf = HDR_MAX_DUMMY_BUF;
else
max_buf = 0;
}
for (i = 0; i < max_dma; i++) {
for (j = 0; j < max_buf; j++) {
buf = &dev->hdr.dummy_buf[i][j];
buf->size = size;
if (rkisp_alloc_buffer(dev, buf) < 0) {
v4l2_err(&dev->v4l2_dev,
"Failed to allocate the memory for hdr buffer\n");
return -ENOMEM;
}
hdr_qbuf(&dev->hdr.q_tx[i], buf);
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"hdr buf[%d][%d]:0x%x\n",
i, j, (u32)buf->dma_addr);
}
dev->hdr.index[i] = i;
}
/*
* normal: q_tx[0] to dma0
* q_tx[1] to dma1
* rdbk1: using dma2
q_tx[0] to dma2
* rdbk2: using dma0 (as M), dma2 (as S)
* q_tx[0] to dma0
* q_tx[1] to dma2
* rdbk3: using dma0 (as M), dam1 (as L), dma2 (as S)
* q_tx[0] to dma0
* q_tx[1] to dma1
* q_tx[2] to dma2
*/
if (dev->hdr.op_mode == HDR_RDBK_FRAME1) {
dev->hdr.index[HDR_DMA2] = 0;
dev->hdr.index[HDR_DMA0] = 1;
dev->hdr.index[HDR_DMA1] = 2;
} else if (dev->hdr.op_mode == HDR_RDBK_FRAME2) {
dev->hdr.index[HDR_DMA0] = 0;
dev->hdr.index[HDR_DMA2] = 1;
dev->hdr.index[HDR_DMA1] = 2;
}
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"hdr:%d buf index dma0:%d dma1:%d dma2:%d\n",
max_dma,
dev->hdr.index[HDR_DMA0],
dev->hdr.index[HDR_DMA1],
dev->hdr.index[HDR_DMA2]);
return 0;
}
void hdr_destroy_buf(struct rkisp_device *dev)
{
int i, j;
struct rkisp_dummy_buffer *buf;
if (atomic_read(&dev->cap_dev.refcnt) > 1 ||
!dev->active_sensor ||
(dev->active_sensor &&
dev->active_sensor->mbus.type != V4L2_MBUS_CSI2))
return;
atomic_set(&dev->hdr.refcnt, 0);
for (i = 0; i < HDR_DMA_MAX; i++) {
buf = dev->hdr.rx_cur_buf[i];
if (buf) {
rkisp_free_buffer(dev, buf);
dev->hdr.rx_cur_buf[i] = NULL;
}
for (j = 0; j < HDR_MAX_DUMMY_BUF; j++) {
buf = hdr_dqbuf(&dev->hdr.q_tx[i]);
if (buf)
rkisp_free_buffer(dev, buf);
buf = hdr_dqbuf(&dev->hdr.q_rx[i]);
if (buf)
rkisp_free_buffer(dev, buf);
}
}
}
int hdr_update_dmatx_buf(struct rkisp_device *dev)
{
void __iomem *base = dev->base_addr;
struct rkisp_stream *dmatx;
struct rkisp_dummy_buffer *buf;
u8 i, index;
if (!dev->active_sensor ||
(dev->active_sensor &&
dev->active_sensor->mbus.type != V4L2_MBUS_CSI2) ||
(dev->isp_inp & INP_CIF))
return 0;
for (i = RKISP_STREAM_DMATX0; i <= RKISP_STREAM_DMATX2; i++) {
dmatx = &dev->cap_dev.stream[i];
if (dmatx->ops && dmatx->ops->frame_end)
dmatx->ops->frame_end(dmatx);
}
if (dev->dmarx_dev.trigger)
goto end;
/* for rawrd auto trigger mode, config first buf */
index = dev->hdr.index[HDR_DMA0];
buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
if (buf) {
mi_raw0_rd_set_addr(base, buf->dma_addr);
dev->hdr.rx_cur_buf[index] = buf;
} else {
mi_raw0_rd_set_addr(base,
readl(base + MI_RAW0_WR_BASE_SHD));
}
index = dev->hdr.index[HDR_DMA1];
buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
if (buf) {
mi_raw1_rd_set_addr(base, buf->dma_addr);
dev->hdr.rx_cur_buf[index] = buf;
} else {
mi_raw1_rd_set_addr(base,
readl(base + MI_RAW1_WR_BASE_SHD));
}
index = dev->hdr.index[HDR_DMA2];
buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
if (buf) {
mi_raw2_rd_set_addr(base, buf->dma_addr);
dev->hdr.rx_cur_buf[index] = buf;
} else {
mi_raw2_rd_set_addr(base,
readl(base + MI_RAW2_WR_BASE_SHD));
}
end:
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"CSI2RX CTRL0:0x%x CTRL1:0x%x\n"
"WR CTRL RAW0:0x%x RAW1:0x%x RAW2:0x%x\n"
"RD CTRL:0x%x\n",
readl(base + CSI2RX_CTRL0),
readl(base + CSI2RX_CTRL1),
readl(base + CSI2RX_RAW0_WR_CTRL),
readl(base + CSI2RX_RAW1_WR_CTRL),
readl(base + CSI2RX_RAW2_WR_CTRL),
readl(base + CSI2RX_RAW_RD_CTRL));
return 0;
}
int hdr_config_dmatx(struct rkisp_device *dev)
{
struct rkisp_stream *stream;
struct v4l2_pix_format_mplane pixm;
if (atomic_inc_return(&dev->hdr.refcnt) > 1 ||
!dev->active_sensor ||
(dev->active_sensor &&
dev->active_sensor->mbus.type != V4L2_MBUS_CSI2) ||
(dev->isp_inp & INP_CIF))
return 0;
rkisp_create_hdr_buf(dev);
memset(&pixm, 0, sizeof(pixm));
if (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
dev->hdr.op_mode == HDR_LINEX2_DDR ||
dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
dev->hdr.op_mode == HDR_LINEX3_DDR ||
dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
if (stream->ops && stream->ops->config_mi)
stream->ops->config_mi(stream);
if (!dev->dmarx_dev.trigger) {
pixm = stream->out_fmt;
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
rkisp_dmarx_set_fmt(stream, pixm);
mi_raw_length(stream);
}
}
if (dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
dev->hdr.op_mode == HDR_LINEX3_DDR ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX1];
if (stream->ops && stream->ops->config_mi)
stream->ops->config_mi(stream);
if (!dev->dmarx_dev.trigger) {
pixm = stream->out_fmt;
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
rkisp_dmarx_set_fmt(stream, pixm);
mi_raw_length(stream);
}
}
if (dev->hdr.op_mode == HDR_RDBK_FRAME1 ||
dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX2];
if (stream->ops && stream->ops->config_mi)
stream->ops->config_mi(stream);
if (!dev->dmarx_dev.trigger) {
pixm = stream->out_fmt;
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
rkisp_dmarx_set_fmt(stream, pixm);
stream->ops->config_mi(stream);
}
}
if (dev->hdr.op_mode != HDR_NORMAL && !dev->dmarx_dev.trigger) {
raw_rd_ctrl(dev->base_addr, dev->csi_dev.memory << 2);
if (pixm.width && pixm.height)
rkisp_rawrd_set_pic_size(dev, pixm.width, pixm.height);
}
return 0;
}
void hdr_stop_dmatx(struct rkisp_device *dev)
{
struct rkisp_stream *stream;
if (atomic_dec_return(&dev->hdr.refcnt) ||
!dev->active_sensor ||
(dev->active_sensor &&
dev->active_sensor->mbus.type != V4L2_MBUS_CSI2) ||
(dev->isp_inp & INP_CIF))
return;
if (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
dev->hdr.op_mode == HDR_LINEX2_DDR ||
dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
dev->hdr.op_mode == HDR_LINEX3_DDR ||
dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
stream->ops->stop_mi(stream);
}
if (dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
dev->hdr.op_mode == HDR_LINEX3_DDR ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX1];
stream->ops->stop_mi(stream);
}
if (dev->hdr.op_mode == HDR_RDBK_FRAME1 ||
dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX2];
stream->ops->stop_mi(stream);
}
}
struct rkisp_dummy_buffer *hdr_dqbuf(struct list_head *q)
{
struct rkisp_dummy_buffer *buf = NULL;
if (!list_empty(q)) {
buf = list_first_entry(q,
struct rkisp_dummy_buffer, queue);
list_del(&buf->queue);
}
return buf;
}
void hdr_qbuf(struct list_head *q,
struct rkisp_dummy_buffer *buf)
{
if (buf)
list_add_tail(&buf->queue, q);
}
void rkisp_config_dmatx_valid_buf(struct rkisp_device *dev)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_stream *stream;
struct rkisp_device *isp;
u32 i, j;
if (!hw->dummy_buf.mem_priv)
return;
/* dmatx buf update by mi force or oneself frame end,
* for async dmatx enable need to update to valid buf first.
*/
for (i = 0; i < hw->dev_num; i++) {
isp = hw->isp[i];
if (!(isp->isp_inp & INP_CSI))
continue;
for (j = RKISP_STREAM_DMATX0; j < RKISP_MAX_STREAM; j++) {
stream = &isp->cap_dev.stream[j];
if (!stream->linked || stream->u.dmatx.is_config)
continue;
mi_set_y_addr(stream, hw->dummy_buf.dma_addr);
}
}
}
/* Get xsubs and ysubs for fourcc formats
*
* @xsubs: horizontal color samples in a 4*4 matrix, for yuv

7
drivers/media/platform/rockchip/isp/capture_v1x.h
View File

@@ -4,7 +4,14 @@
#ifndef _RKISP_CAPTURE_V1X_H
#define _RKISP_CAPTURE_V1X_H
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X)
int rkisp_register_stream_v1x(struct rkisp_device *dev);
void rkisp_unregister_stream_v1x(struct rkisp_device *dev);
void rkisp_mi_v1x_isr(u32 mis_val, struct rkisp_device *dev);
#else
static inline int rkisp_register_stream_v1x(struct rkisp_device *dev) { return 0; }
static inline void rkisp_unregister_stream_v1x(struct rkisp_device *dev) {}
static inline void rkisp_mi_v1x_isr(u32 mis_val, struct rkisp_device *dev) {}
#endif
#endif

351
drivers/media/platform/rockchip/isp/capture_v20.c
View File

@@ -129,7 +129,7 @@ static const struct capture_fmt dmatx_fmts[] = {
}
};
struct stream_config rkisp2_dmatx0_stream_config = {
static struct stream_config rkisp2_dmatx0_stream_config = {
.fmts = dmatx_fmts,
.fmt_size = ARRAY_SIZE(dmatx_fmts),
.frame_end_id = MI_RAW0_WR_FRAME,
@@ -146,7 +146,7 @@ struct stream_config rkisp2_dmatx0_stream_config = {
},
};
struct stream_config rkisp2_dmatx1_stream_config = {
static struct stream_config rkisp2_dmatx1_stream_config = {
.fmts = dmatx_fmts,
.fmt_size = ARRAY_SIZE(dmatx_fmts),
.frame_end_id = MI_RAW1_WR_FRAME,
@@ -163,7 +163,7 @@ struct stream_config rkisp2_dmatx1_stream_config = {
},
};
struct stream_config rkisp2_dmatx2_stream_config = {
static struct stream_config rkisp2_dmatx2_stream_config = {
.fmts = dmatx_fmts,
.fmt_size = ARRAY_SIZE(dmatx_fmts),
.frame_end_id = MI_RAW2_WR_FRAME,
@@ -180,7 +180,7 @@ struct stream_config rkisp2_dmatx2_stream_config = {
},
};
struct stream_config rkisp2_dmatx3_stream_config = {
static struct stream_config rkisp2_dmatx3_stream_config = {
.fmts = dmatx_fmts,
.fmt_size = ARRAY_SIZE(dmatx_fmts),
.frame_end_id = MI_RAW3_WR_FRAME,
@@ -215,342 +215,6 @@ static bool is_rdbk_stream(struct rkisp_stream *stream)
return en;
}
static int hdr_dma_frame(struct rkisp_device *dev)
{
int max_dma;
switch (dev->hdr.op_mode) {
case HDR_FRAMEX2_DDR:
case HDR_LINEX2_DDR:
case HDR_RDBK_FRAME1:
max_dma = 1;
break;
case HDR_FRAMEX3_DDR:
case HDR_LINEX3_DDR:
case HDR_RDBK_FRAME2:
max_dma = 2;
break;
case HDR_RDBK_FRAME3:
max_dma = HDR_DMA_MAX;
break;
case HDR_LINEX2_NO_DDR:
case HDR_NORMAL:
default:
max_dma = 0;
}
return max_dma;
}
static int rkisp_create_hdr_buf(struct rkisp_device *dev)
{
int i, j, max_dma, max_buf = 1;
struct rkisp_dummy_buffer *buf;
struct rkisp_stream *stream;
u32 size;
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
size = stream->out_fmt.plane_fmt[0].sizeimage;
max_dma = hdr_dma_frame(dev);
/* hdr read back mode using base and shd address
* this support multi-buffer
*/
if (IS_HDR_RDBK(dev->hdr.op_mode)) {
if (!dev->dmarx_dev.trigger)
max_buf = HDR_MAX_DUMMY_BUF;
else
max_buf = 0;
}
for (i = 0; i < max_dma; i++) {
for (j = 0; j < max_buf; j++) {
buf = &dev->hdr.dummy_buf[i][j];
buf->size = size;
if (rkisp_alloc_buffer(dev, buf) < 0) {
v4l2_err(&dev->v4l2_dev,
"Failed to allocate the memory for hdr buffer\n");
return -ENOMEM;
}
hdr_qbuf(&dev->hdr.q_tx[i], buf);
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"hdr buf[%d][%d]:0x%x\n",
i, j, (u32)buf->dma_addr);
}
dev->hdr.index[i] = i;
}
/*
* normal: q_tx[0] to dma0
* q_tx[1] to dma1
* rdbk1: using dma2
q_tx[0] to dma2
* rdbk2: using dma0 (as M), dma2 (as S)
* q_tx[0] to dma0
* q_tx[1] to dma2
* rdbk3: using dma0 (as M), dam1 (as L), dma2 (as S)
* q_tx[0] to dma0
* q_tx[1] to dma1
* q_tx[2] to dma2
*/
if (dev->hdr.op_mode == HDR_RDBK_FRAME1) {
dev->hdr.index[HDR_DMA2] = 0;
dev->hdr.index[HDR_DMA0] = 1;
dev->hdr.index[HDR_DMA1] = 2;
} else if (dev->hdr.op_mode == HDR_RDBK_FRAME2) {
dev->hdr.index[HDR_DMA0] = 0;
dev->hdr.index[HDR_DMA2] = 1;
dev->hdr.index[HDR_DMA1] = 2;
}
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"hdr:%d buf index dma0:%d dma1:%d dma2:%d\n",
max_dma,
dev->hdr.index[HDR_DMA0],
dev->hdr.index[HDR_DMA1],
dev->hdr.index[HDR_DMA2]);
return 0;
}
void hdr_destroy_buf(struct rkisp_device *dev)
{
int i, j;
struct rkisp_dummy_buffer *buf;
if (atomic_read(&dev->cap_dev.refcnt) > 1 ||
!dev->active_sensor ||
(dev->active_sensor &&
dev->active_sensor->mbus.type != V4L2_MBUS_CSI2))
return;
atomic_set(&dev->hdr.refcnt, 0);
for (i = 0; i < HDR_DMA_MAX; i++) {
buf = dev->hdr.rx_cur_buf[i];
if (buf) {
rkisp_free_buffer(dev, buf);
dev->hdr.rx_cur_buf[i] = NULL;
}
for (j = 0; j < HDR_MAX_DUMMY_BUF; j++) {
buf = hdr_dqbuf(&dev->hdr.q_tx[i]);
if (buf)
rkisp_free_buffer(dev, buf);
buf = hdr_dqbuf(&dev->hdr.q_rx[i]);
if (buf)
rkisp_free_buffer(dev, buf);
}
}
}
int hdr_update_dmatx_buf(struct rkisp_device *dev)
{
void __iomem *base = dev->base_addr;
struct rkisp_stream *dmatx;
struct rkisp_dummy_buffer *buf;
u8 i, index;
if (!dev->active_sensor ||
(dev->active_sensor &&
dev->active_sensor->mbus.type != V4L2_MBUS_CSI2) ||
(dev->isp_inp & INP_CIF))
return 0;
for (i = RKISP_STREAM_DMATX0; i <= RKISP_STREAM_DMATX2; i++) {
dmatx = &dev->cap_dev.stream[i];
if (dmatx->ops && dmatx->ops->frame_end)
dmatx->ops->frame_end(dmatx);
}
if (dev->dmarx_dev.trigger)
goto end;
/* for rawrd auto trigger mode, config first buf */
index = dev->hdr.index[HDR_DMA0];
buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
if (buf) {
mi_raw0_rd_set_addr(base, buf->dma_addr);
dev->hdr.rx_cur_buf[index] = buf;
} else {
mi_raw0_rd_set_addr(base,
readl(base + MI_RAW0_WR_BASE_SHD));
}
index = dev->hdr.index[HDR_DMA1];
buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
if (buf) {
mi_raw1_rd_set_addr(base, buf->dma_addr);
dev->hdr.rx_cur_buf[index] = buf;
} else {
mi_raw1_rd_set_addr(base,
readl(base + MI_RAW1_WR_BASE_SHD));
}
index = dev->hdr.index[HDR_DMA2];
buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
if (buf) {
mi_raw2_rd_set_addr(base, buf->dma_addr);
dev->hdr.rx_cur_buf[index] = buf;
} else {
mi_raw2_rd_set_addr(base,
readl(base + MI_RAW2_WR_BASE_SHD));
}
end:
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"CSI2RX CTRL0:0x%x CTRL1:0x%x\n"
"WR CTRL RAW0:0x%x RAW1:0x%x RAW2:0x%x\n"
"RD CTRL:0x%x\n",
readl(base + CSI2RX_CTRL0),
readl(base + CSI2RX_CTRL1),
readl(base + CSI2RX_RAW0_WR_CTRL),
readl(base + CSI2RX_RAW1_WR_CTRL),
readl(base + CSI2RX_RAW2_WR_CTRL),
readl(base + CSI2RX_RAW_RD_CTRL));
return 0;
}
int hdr_config_dmatx(struct rkisp_device *dev)
{
struct rkisp_stream *stream;
struct v4l2_pix_format_mplane pixm;
if (atomic_inc_return(&dev->hdr.refcnt) > 1 ||
!dev->active_sensor ||
(dev->active_sensor &&
dev->active_sensor->mbus.type != V4L2_MBUS_CSI2) ||
(dev->isp_inp & INP_CIF))
return 0;
rkisp_create_hdr_buf(dev);
memset(&pixm, 0, sizeof(pixm));
if (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
dev->hdr.op_mode == HDR_LINEX2_DDR ||
dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
dev->hdr.op_mode == HDR_LINEX3_DDR ||
dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
if (stream->ops && stream->ops->config_mi)
stream->ops->config_mi(stream);
if (!dev->dmarx_dev.trigger) {
pixm = stream->out_fmt;
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
rkisp_dmarx_set_fmt(stream, pixm);
mi_raw_length(stream);
}
}
if (dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
dev->hdr.op_mode == HDR_LINEX3_DDR ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX1];
if (stream->ops && stream->ops->config_mi)
stream->ops->config_mi(stream);
if (!dev->dmarx_dev.trigger) {
pixm = stream->out_fmt;
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
rkisp_dmarx_set_fmt(stream, pixm);
mi_raw_length(stream);
}
}
if (dev->hdr.op_mode == HDR_RDBK_FRAME1 ||
dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX2];
if (stream->ops && stream->ops->config_mi)
stream->ops->config_mi(stream);
if (!dev->dmarx_dev.trigger) {
pixm = stream->out_fmt;
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
rkisp_dmarx_set_fmt(stream, pixm);
stream->ops->config_mi(stream);
}
}
if (dev->hdr.op_mode != HDR_NORMAL && !dev->dmarx_dev.trigger) {
raw_rd_ctrl(dev->base_addr, dev->csi_dev.memory << 2);
if (pixm.width && pixm.height)
rkisp_rawrd_set_pic_size(dev, pixm.width, pixm.height);
}
return 0;
}
void hdr_stop_dmatx(struct rkisp_device *dev)
{
struct rkisp_stream *stream;
if (atomic_dec_return(&dev->hdr.refcnt) ||
!dev->active_sensor ||
(dev->active_sensor &&
dev->active_sensor->mbus.type != V4L2_MBUS_CSI2) ||
(dev->isp_inp & INP_CIF))
return;
if (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
dev->hdr.op_mode == HDR_LINEX2_DDR ||
dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
dev->hdr.op_mode == HDR_LINEX3_DDR ||
dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
stream->ops->stop_mi(stream);
}
if (dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
dev->hdr.op_mode == HDR_LINEX3_DDR ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX1];
stream->ops->stop_mi(stream);
}
if (dev->hdr.op_mode == HDR_RDBK_FRAME1 ||
dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME3) {
stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX2];
stream->ops->stop_mi(stream);
}
}
struct rkisp_dummy_buffer *hdr_dqbuf(struct list_head *q)
{
struct rkisp_dummy_buffer *buf = NULL;
if (!list_empty(q)) {
buf = list_first_entry(q,
struct rkisp_dummy_buffer, queue);
list_del(&buf->queue);
}
return buf;
}
void hdr_qbuf(struct list_head *q,
struct rkisp_dummy_buffer *buf)
{
if (buf)
list_add_tail(&buf->queue, q);
}
void rkisp_config_dmatx_valid_buf(struct rkisp_device *dev)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_stream *stream;
struct rkisp_device *isp;
u32 i, j;
if (!hw->dummy_buf.mem_priv)
return;
/* dmatx buf update by mi force or oneself frame end,
* for async dmatx enable need to update to valid buf first.
*/
for (i = 0; i < hw->dev_num; i++) {
isp = hw->isp[i];
if (!(isp->isp_inp & INP_CSI))
continue;
for (j = RKISP_STREAM_DMATX0; j < RKISP_MAX_STREAM; j++) {
stream = &isp->cap_dev.stream[j];
if (!stream->linked || stream->u.dmatx.is_config)
continue;
mi_set_y_addr(stream, hw->dummy_buf.dma_addr);
}
}
}
/* configure dual-crop unit */
static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)
{
@@ -1235,7 +899,7 @@ static void rdbk_frame_end(struct rkisp_stream *stream)
u32 denominator = sensor->fi.interval.denominator;
u32 numerator = sensor->fi.interval.numerator;
u64 l_ts, m_ts, s_ts;
int ret, max_dma, fps = -1, time = 30000000;
int ret, fps = -1, time = 30000000;
if (stream->id != RKISP_STREAM_DMATX2)
return;
@@ -1243,8 +907,7 @@ static void rdbk_frame_end(struct rkisp_stream *stream)
if (denominator && numerator)
time = numerator * 1000 / denominator * 1000 * 1000;
max_dma = hdr_dma_frame(isp_dev);
if (max_dma == 3) {
if (isp_dev->hdr.op_mode == HDR_RDBK_FRAME3) {
if (cap->rdbk_buf[RDBK_L] && cap->rdbk_buf[RDBK_M] &&
cap->rdbk_buf[RDBK_S]) {
l_ts = cap->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
@@ -1290,7 +953,7 @@ static void rdbk_frame_end(struct rkisp_stream *stream)
v4l2_err(&isp_dev->v4l2_dev, "lost long or middle frames\n");
goto RDBK_FRM_UNMATCH;
}
} else if (max_dma == 2) {
} else if (isp_dev->hdr.op_mode == HDR_RDBK_FRAME2) {
if (cap->rdbk_buf[RDBK_L] && cap->rdbk_buf[RDBK_S]) {
l_ts = cap->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
s_ts = cap->rdbk_buf[RDBK_S]->vb.vb2_buf.timestamp;

161
drivers/media/platform/rockchip/isp/capture_v21.c
View File

@@ -19,6 +19,167 @@ static int mi_frame_end(struct rkisp_stream *stream);
static void rkisp_buf_queue(struct vb2_buffer *vb);
static int rkisp_create_dummy_buf(struct rkisp_stream *stream);
static const struct capture_fmt dmatx_fmts[] = {
/* raw */
{
.fourcc = V4L2_PIX_FMT_SRGGB8,
.fmt_type = FMT_BAYER,
.bpp = { 8 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG8,
.fmt_type = FMT_BAYER,
.bpp = { 8 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG8,
.fmt_type = FMT_BAYER,
.bpp = { 8 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR8,
.fmt_type = FMT_BAYER,
.bpp = { 8 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_GREY,
.fmt_type = FMT_BAYER,
.bpp = { 8 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB10,
.fmt_type = FMT_BAYER,
.bpp = { 10 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG10,
.fmt_type = FMT_BAYER,
.bpp = { 10 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG10,
.fmt_type = FMT_BAYER,
.bpp = { 10 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.fmt_type = FMT_BAYER,
.bpp = { 10 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_Y10,
.fmt_type = FMT_BAYER,
.bpp = { 10 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB12,
.fmt_type = FMT_BAYER,
.bpp = { 12 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG12,
.fmt_type = FMT_BAYER,
.bpp = { 12 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG12,
.fmt_type = FMT_BAYER,
.bpp = { 12 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR12,
.fmt_type = FMT_BAYER,
.bpp = { 12 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_Y12,
.fmt_type = FMT_BAYER,
.bpp = { 12 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_YUYV,
.fmt_type = FMT_YUV,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_YVYU,
.fmt_type = FMT_YUV,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_UYVY,
.fmt_type = FMT_YUV,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_VYUY,
.fmt_type = FMT_YUV,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4l2_PIX_FMT_EBD8,
.fmt_type = FMT_EBD,
.bpp = { 8 },
.mplanes = 1,
}, {
.fourcc = V4l2_PIX_FMT_SPD16,
.fmt_type = FMT_SPD,
.bpp = { 16 },
.mplanes = 1,
}
};
static struct stream_config rkisp2_dmatx0_stream_config = {
.fmts = dmatx_fmts,
.fmt_size = ARRAY_SIZE(dmatx_fmts),
.frame_end_id = MI_RAW0_WR_FRAME,
.mi = {
.y_size_init = MI_RAW0_WR_SIZE,
.y_base_ad_init = MI_RAW0_WR_BASE,
.y_base_ad_shd = MI_RAW0_WR_BASE_SHD,
.length = MI_RAW0_WR_LENGTH,
},
.dma = {
.ctrl = CSI2RX_RAW0_WR_CTRL,
.pic_size = CSI2RX_RAW0_WR_PIC_SIZE,
.pic_offs = CSI2RX_RAW0_WR_PIC_OFF,
},
};
static struct stream_config rkisp2_dmatx1_stream_config = {
.fmts = dmatx_fmts,
.fmt_size = ARRAY_SIZE(dmatx_fmts),
.frame_end_id = MI_RAW1_WR_FRAME,
.mi = {
.y_size_init = MI_RAW1_WR_SIZE,
.y_base_ad_init = MI_RAW1_WR_BASE,
.y_base_ad_shd = MI_RAW1_WR_BASE_SHD,
.length = MI_RAW1_WR_LENGTH,
},
.dma = {
.ctrl = CSI2RX_RAW1_WR_CTRL,
.pic_size = CSI2RX_RAW1_WR_PIC_SIZE,
.pic_offs = CSI2RX_RAW1_WR_PIC_OFF,
},
};
static struct stream_config rkisp2_dmatx3_stream_config = {
.fmts = dmatx_fmts,
.fmt_size = ARRAY_SIZE(dmatx_fmts),
.frame_end_id = MI_RAW3_WR_FRAME,
.mi = {
.y_size_init = MI_RAW3_WR_SIZE,
.y_base_ad_init = MI_RAW3_WR_BASE,
.y_base_ad_shd = MI_RAW3_WR_BASE_SHD,
.length = MI_RAW3_WR_LENGTH,
},
.dma = {
.ctrl = CSI2RX_RAW3_WR_CTRL,
.pic_size = CSI2RX_RAW3_WR_PIC_SIZE,
.pic_offs = CSI2RX_RAW3_WR_PIC_OFF,
},
};
static bool is_rdbk_stream(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;

29
drivers/media/platform/rockchip/isp/capture_v2x.h
View File

@@ -4,11 +4,6 @@
#ifndef _RKISP_CAPTURE_V2X_H
#define _RKISP_CAPTURE_V2X_H
extern struct stream_config rkisp2_dmatx0_stream_config;
extern struct stream_config rkisp2_dmatx1_stream_config;
extern struct stream_config rkisp2_dmatx2_stream_config;
extern struct stream_config rkisp2_dmatx3_stream_config;
struct rkisp_stream;
struct rkisp_dummy_buffer *hdr_dqbuf(struct list_head *q);
@@ -19,19 +14,33 @@ void hdr_stop_dmatx(struct rkisp_device *dev);
void hdr_destroy_buf(struct rkisp_device *dev);
void rkisp_config_dmatx_valid_buf(struct rkisp_device *dev);
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20)
int rkisp_register_stream_v20(struct rkisp_device *dev);
void rkisp_unregister_stream_v20(struct rkisp_device *dev);
void rkisp_mi_v20_isr(u32 mis_val, struct rkisp_device *dev);
void rkisp_mipi_v20_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev);
int rkisp_register_stream_v21(struct rkisp_device *dev);
void rkisp_unregister_stream_v21(struct rkisp_device *dev);
void rkisp_mi_v21_isr(u32 mis_val, struct rkisp_device *dev);
void rkisp_mipi_v21_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev);
void rkisp_spbuf_queue(struct rkisp_stream *stream, struct rkisp_buffer *sp_buf);
int rkisp_start_spstream(struct rkisp_stream *stream);
void rkisp_stop_spstream(struct rkisp_stream *stream);
void rkisp_update_spstream_buf(struct rkisp_stream *stream);
#else
static inline int rkisp_register_stream_v20(struct rkisp_device *dev) { return 0; }
static inline void rkisp_unregister_stream_v20(struct rkisp_device *dev) {}
static inline void rkisp_mi_v20_isr(u32 mis_val, struct rkisp_device *dev) {}
static inline void rkisp_mipi_v20_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev) {}
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21)
int rkisp_register_stream_v21(struct rkisp_device *dev);
void rkisp_unregister_stream_v21(struct rkisp_device *dev);
void rkisp_mi_v21_isr(u32 mis_val, struct rkisp_device *dev);
void rkisp_mipi_v21_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev);
#else
static inline int rkisp_register_stream_v21(struct rkisp_device *dev) { return 0; }
static inline void rkisp_unregister_stream_v21(struct rkisp_device *dev) {}
static inline void rkisp_mi_v21_isr(u32 mis_val, struct rkisp_device *dev) {}
static inline void rkisp_mipi_v21_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev) {}
#endif
#endif

2
drivers/media/platform/rockchip/isp/isp_ispp.h
View File

@@ -121,7 +121,7 @@ struct rkisp_ispp_buf {
int __init rkispp_hw_drv_init(void);
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP)
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20)
void rkisp_get_bridge_sd(struct platform_device *dev,
struct v4l2_subdev **sd);
#else

10
drivers/media/platform/rockchip/isp/isp_mipi_luma.h
View File

@@ -58,6 +58,7 @@ struct rkisp_luma_vdev {
struct rkisp_luma_readout_work work;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20)
void rkisp_luma_isr(struct rkisp_luma_vdev *luma_vdev, u32 isp_stat);
int rkisp_register_luma_vdev(struct rkisp_luma_vdev *luma_vdev,
@@ -65,5 +66,14 @@ int rkisp_register_luma_vdev(struct rkisp_luma_vdev *luma_vdev,
struct rkisp_device *dev);
void rkisp_unregister_luma_vdev(struct rkisp_luma_vdev *luma_vdev);
#else
static inline void rkisp_unregister_luma_vdev(struct rkisp_luma_vdev *luma_vdev) {}
static inline int rkisp_register_luma_vdev(struct rkisp_luma_vdev *luma_vdev,
struct v4l2_device *v4l2_dev,
struct rkisp_device *dev)
{
return 0;
}
#endif
#endif /* _RKISP_ISP_LUMA_H */

5
drivers/media/platform/rockchip/isp/isp_params_v1x.h
View File

@@ -76,7 +76,12 @@ struct rkisp_isp_params_v1x_config {
const int hst_weight_grids_size;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X)
int rkisp_init_params_vdev_v1x(struct rkisp_isp_params_vdev *params_vdev);
void rkisp_uninit_params_vdev_v1x(struct rkisp_isp_params_vdev *params_vdev);
#else
static inline int rkisp_init_params_vdev_v1x(struct rkisp_isp_params_vdev *params_vdev) { return 0; }
static inline void rkisp_uninit_params_vdev_v1x(struct rkisp_isp_params_vdev *params_vdev) {}
#endif
#endif /* _RKISP_ISP_PARAM_V1X_H */

5
drivers/media/platform/rockchip/isp/isp_params_v21.h
View File

@@ -326,7 +326,12 @@ struct rkisp_isp_params_val_v21 {
u8 mge_en;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21)
int rkisp_init_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev);
void rkisp_uninit_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev);
#else
static inline int rkisp_init_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev) { return 0; }
static inline void rkisp_uninit_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev) {}
#endif
#endif /* _RKISP_ISP_PARAM_V21_H */

5
drivers/media/platform/rockchip/isp/isp_params_v2x.h
View File

@@ -343,7 +343,12 @@ struct rkisp_isp_params_val_v2x {
bool delay_en_ldch;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20)
int rkisp_init_params_vdev_v2x(struct rkisp_isp_params_vdev *params_vdev);
void rkisp_uninit_params_vdev_v2x(struct rkisp_isp_params_vdev *params_vdev);
#else
static inline int rkisp_init_params_vdev_v2x(struct rkisp_isp_params_vdev *params_vdev) { return 0; }
static inline void rkisp_uninit_params_vdev_v2x(struct rkisp_isp_params_vdev *params_vdev) {}
#endif
#endif /* _RKISP_ISP_PARAM_V2X_H */

5
drivers/media/platform/rockchip/isp/isp_stats_v1x.h
View File

@@ -31,7 +31,12 @@ struct rkisp_stats_v1x_config {
const int hist_bin_n_max;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X)
void rkisp_init_stats_vdev_v1x(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v1x(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_init_stats_vdev_v1x(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v1x(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif
#endif /* _RKISP_ISP_STATS_V1X_H */

6
drivers/media/platform/rockchip/isp/isp_stats_v21.h
View File

@@ -39,8 +39,14 @@ struct rkisp_stats_v21_ops {
struct rkisp_isp21_stat_buffer *pbuf);
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21)
void rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif
#endif /* _RKISP_ISP_STATS_V21_H */

6
drivers/media/platform/rockchip/isp/isp_stats_v2x.h
View File

@@ -57,8 +57,14 @@ struct rkisp_stats_v2x_ops {
struct rkisp_isp2x_stat_buffer *pbuf);
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20)
void rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif
#endif /* _RKISP_ISP_STATS_V2X_H */