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clk: rockchip: rk3588: support more pll frequency for display

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Change-Id: I24a246f798a4e8bfe9f346e553cfeb2b168edcf3
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
This commit is contained in:
Zhang Yubing
2023-11-17 15:27:07 +08:00
committed by Tao Huang
parent 4389dbd8ec
commit 4ad8ea9a7a
1 changed files with 8 additions and 0 deletions
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8
drivers/clk/rockchip/clk-rk3588.c
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@@ -75,7 +75,11 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
RK3588_PLL_RATE(1186814000, 2, 198, 1, 52581),
RK3588_PLL_RATE(1186812000, 2, 198, 1, 52559),
RK3588_PLL_RATE(1109000000, 3, 554, 2, 32767),
RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
RK3588_PLL_RATE(1051000000, 3, 525, 2, 32767),
RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
@@ -86,11 +90,15 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
RK3588_PLL_RATE(785560000, 3, 393, 2, 51119),
RK3588_PLL_RATE(773000000, 2, 258, 2, 43690),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
RK3588_PLL_RATE(697000000, 2, 232, 2, 21845),
RK3588_PLL_RATE(604800000, 1, 101, 2, 52428),
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
RK3588_PLL_RATE(594000000, 1, 99, 2, 0),
RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
RK3588_PLL_RATE(266580000, 1, 178, 4, 47185),
RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
RK3588_PLL_RATE(96000000, 2, 256, 5, 0),
{ /* sentinel */ },