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ARM: rockchip: support CPU config

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CACHE_L2X0/TWD/ARM_GLOBAL_TIMER are only available on Cortex-A9.
DW_APB_TIMER_OF only use on rk3066a.

Change-Id: Ied2f49b5d308e961ce5af72eb577aac23e3eb890
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang
2018-05-24 14:50:45 +08:00
parent 3eef0d794e
commit 4b1fe5cca9
1 changed files with 5 additions and 5 deletions
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10
arch/arm/mach-rockchip/Kconfig
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@@ -6,16 +6,16 @@ config ARCH_ROCKCHIP
select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GIC
select CACHE_L2X0
select CACHE_L2X0 if (CPU_RK30XX || CPU_RK3188)
select GPIOLIB
select HAVE_ARM_ARCH_TIMER
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select DW_APB_TIMER_OF
select HAVE_ARM_TWD if SMP && (CPU_RK30XX || CPU_RK3188)
select DW_APB_TIMER_OF if CPU_RK30XX
select REGULATOR if PM
select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
select ARM_GLOBAL_TIMER if (CPU_RK30XX || CPU_RK3188)
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK if (CPU_RK30XX || CPU_RK3188)
select ZONE_DMA if ARM_LPAE
select PM
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