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media: i2c: rk628csi: detect resolution changes as quickly as possible

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Change-Id: I432c4178961641e541c75b62a21598d87ae142d8
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
This commit is contained in:
Dingxian Wen
2021-07-06 11:44:57 +08:00
committed by Tao Huang
parent 5d98311786
commit 4b32bc65cf
2 changed files with 37 additions and 8 deletions
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28
drivers/media/i2c/rk628_csi.c
View File

@@ -39,7 +39,7 @@ static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "debug level (0-3)");
#define DRIVER_VERSION KERNEL_VERSION(0, 0x0, 0x5)
#define DRIVER_VERSION KERNEL_VERSION(0, 0x0, 0x6)
#define RK628_CSI_NAME "rk628-csi"
#define EDID_NUM_BLOCKS_MAX 2
@@ -360,12 +360,12 @@ static int rk628_csi_get_detected_timings(struct v4l2_subdev *sd,
htotal = (val >> 16) & 0xffff;
regmap_read(csi->hdmirx_regmap, HDMI_RX_MD_VTL, &val);
vtotal = val & 0xffff;
regmap_read(csi->hdmirx_regmap, 0x3014c, &val);
regmap_read(csi->hdmirx_regmap, HDMI_RX_MD_HT1, &val);
hofs_pix = val & 0xffff;
regmap_read(csi->hdmirx_regmap, 0x30164, &val);
regmap_read(csi->hdmirx_regmap, HDMI_RX_MD_VOL, &val);
vbp = (val & 0xffff) + 1;
regmap_read(csi->hdmirx_regmap, 0x3009c, &val);
regmap_read(csi->hdmirx_regmap, HDMI_RX_HDMI_CKM_RESULT, &val);
tmdsclk_cnt = val & 0xffff;
tmp_data = tmdsclk_cnt;
tmp_data = ((tmp_data * MODETCLK_HZ) + MODETCLK_CNT_NUM / 2);
@@ -378,12 +378,12 @@ static int rk628_csi_get_detected_timings(struct v4l2_subdev *sd,
}
fps = (tmds_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
regmap_read(csi->hdmirx_regmap, 0x30148, &val);
regmap_read(csi->hdmirx_regmap, HDMI_RX_MD_HT0, &val);
modetclk_cnt_hs = val & 0xffff;
hs = (tmdsclk_cnt * modetclk_cnt_hs + MODETCLK_CNT_NUM / 2) /
MODETCLK_CNT_NUM;
regmap_read(csi->hdmirx_regmap, 0x3015c, &val);
regmap_read(csi->hdmirx_regmap, HDMI_RX_MD_VSC, &val);
modetclk_cnt_vs = val & 0xffff;
vs = (tmdsclk_cnt * modetclk_cnt_vs + MODETCLK_CNT_NUM / 2) /
MODETCLK_CNT_NUM;
@@ -1454,7 +1454,12 @@ static void rk628_csi_enable_interrupts(struct v4l2_subdev *sd, bool en)
if (en) {
regmap_write(csi->hdmirx_regmap, HDMI_RX_MD_IEN_SET,
VACT_LIN_ENSET | HACT_PIX_ENSET);
VACT_LIN_ENSET |
HACT_PIX_ENSET |
HS_CLK_ENSET |
DE_ACTIVITY_ENSET |
VS_ACT_ENSET |
HS_ACT_ENSET);
regmap_write(csi->hdmirx_regmap, HDMI_RX_PDEC_IEN_SET,
AVI_RCV_ENSET);
} else {
@@ -1488,7 +1493,11 @@ static int rk628_csi_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
v4l2_dbg(1, debug, sd, "%s: md_ints: %#x, pdec_ints:%#x, plugin: %d\n",
__func__, md_ints, pdec_ints, plugin);
if ((md_ints & (VACT_LIN_ISTS | HACT_PIX_ISTS)) && plugin) {
if ((md_ints & (VACT_LIN_ISTS | HACT_PIX_ISTS |
HS_CLK_ISTS | DE_ACTIVITY_ISTS |
VS_ACT_ISTS | HS_ACT_ISTS))
&& plugin) {
regmap_read(csi->hdmirx_regmap, HDMI_RX_MD_HACT_PX, &hact);
regmap_read(csi->hdmirx_regmap, HDMI_RX_MD_VAL, &vact);
v4l2_dbg(1, debug, sd, "%s: HACT:%#x, VACT:%#x\n",
@@ -2611,6 +2620,7 @@ static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERROR_PROTECT),
regmap_reg_range(HDMI_RX_HDMI_SYNC_CTRL, HDMI_RX_HDMI_CKM_RESULT),
regmap_reg_range(HDMI_RX_HDMI_RESMPL_CTRL, HDMI_RX_HDMI_RESMPL_CTRL),
regmap_reg_range(HDMI_VM_CFG_CH2, HDMI_VM_CFG_CH2),
regmap_reg_range(HDMI_RX_HDCP_CTRL, HDMI_RX_HDCP_SETTINGS),
regmap_reg_range(HDMI_RX_HDCP_KIDX, HDMI_RX_HDCP_KIDX),
regmap_reg_range(HDMI_RX_HDCP_DBG, HDMI_RX_HDCP_AN0),
@@ -2626,8 +2636,10 @@ static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
regmap_reg_range(HDMI_RX_AUD_CHEXTR_CTRL, HDMI_RX_AUD_PAO_CTRL),
regmap_reg_range(HDMI_RX_AUD_FIFO_STS, HDMI_RX_AUD_FIFO_STS),
regmap_reg_range(HDMI_RX_AUDPLL_GEN_CTS, HDMI_RX_AUDPLL_GEN_N),
regmap_reg_range(HDMI_RX_PDEC_CTRL, HDMI_RX_PDEC_CTRL),
regmap_reg_range(HDMI_RX_PDEC_AUDIODET_CTRL, HDMI_RX_PDEC_AUDIODET_CTRL),
regmap_reg_range(HDMI_RX_PDEC_ERR_FILTER, HDMI_RX_PDEC_ASP_CTRL),
regmap_reg_range(HDMI_RX_PDEC_GCP_AVMUTE, HDMI_RX_PDEC_GCP_AVMUTE),
regmap_reg_range(HDMI_RX_PDEC_ACR_CTS, HDMI_RX_PDEC_ACR_N),
regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_AIF_PB0),
regmap_reg_range(HDMI_RX_PDEC_AVI_PB, HDMI_RX_PDEC_AVI_PB),

17
drivers/media/i2c/rk628_csi.h
View File

@@ -76,6 +76,7 @@
#define DCM_COLOUR_DEPTH_SEL(x) UPDATE(x, 12, 12)
#define DCM_COLOUR_DEPTH(x) UPDATE(x, 11, 8)
#define DCM_GCP_ZERO_FIELDS(x) UPDATE(x, 5, 2)
#define HDMI_VM_CFG_CH2 (HDMI_RX_BASE + 0x00b4)
#define HDMI_RX_HDCP_CTRL (HDMI_RX_BASE + 0x00c0)
#define HDCP_ENABLE_MASK BIT(24)
#define HDCP_ENABLE(x) UPDATE(x, 24, 24)
@@ -117,6 +118,7 @@
#define VS_ACT_TIME(x) UPDATE(x, 5, 5)
#define HS_ACT_TIME(x) UPDATE(x, 4, 3)
#define H_START_POS(x) UPDATE(x, 1, 0)
#define HDMI_RX_MD_HT0 (HDMI_RX_BASE + 0x0148)
#define HDMI_RX_MD_HT1 (HDMI_RX_BASE + 0x014c)
#define HDMI_RX_MD_HACT_PX (HDMI_RX_BASE + 0x0150)
#define HDMI_RX_MD_VCTRL (HDMI_RX_BASE + 0x0158)
@@ -211,6 +213,8 @@
#define PFIFO_STORE_GCP(x) UPDATE(x, 17, 17)
#define PFIFO_STORE_ACR_MASK BIT(16)
#define PFIFO_STORE_ACR(x) UPDATE(x, 16, 16)
#define GCPFORCE_SETAVMUTE_MASK BIT(13)
#define GCPFORCE_SETAVMUTE(x) UPDATE(x, 13, 13)
#define PDEC_BCH_EN_MASK BIT(0)
#define PDEC_BCH_EN(x) UPDATE(x, 0, 0)
#define HDMI_RX_PDEC_FIFO_CFG (HDMI_RX_BASE + 0x0304)
@@ -256,11 +260,17 @@
#define HDMI_RX_HDMI2_IEN_CLR (HDMI_RX_BASE + 0x0f60)
#define HDMI_RX_HDMI2_ISTS (HDMI_RX_BASE + 0x0f68)
#define HDMI_RX_PDEC_IEN_CLR (HDMI_RX_BASE + 0x0f78)
#define GCP_AV_MUTE_CHG_ENCLR BIT(21)
#define AVI_RCV_ENCLR BIT(18)
#define GCP_RCV_ENCLR BIT(16)
#define HDMI_RX_PDEC_IEN_SET (HDMI_RX_BASE + 0x0f7c)
#define GCP_AV_MUTE_CHG_ENSET BIT(21)
#define AVI_RCV_ENSET BIT(18)
#define GCP_RCV_ENSET BIT(16)
#define HDMI_RX_PDEC_ISTS (HDMI_RX_BASE + 0x0f80)
#define GCP_AV_MUTE_CHG_ISTS BIT(21)
#define AVI_RCV_ISTS BIT(18)
#define GCP_RCV_ISTS BIT(16)
#define HDMI_RX_PDEC_IEN (HDMI_RX_BASE + 0x0f84)
#define HDMI_RX_PDEC_ICLR (HDMI_RX_BASE + 0x0f88)
#define HDMI_RX_PDEC_ISET (HDMI_RX_BASE + 0x0f8c)
@@ -275,9 +285,14 @@
#define HDMI_RX_MD_IEN_SET (HDMI_RX_BASE + 0x0fc4)
#define VACT_LIN_ENSET BIT(9)
#define HACT_PIX_ENSET BIT(6)
#define HS_CLK_ENSET BIT(5)
#define DE_ACTIVITY_ENSET BIT(2)
#define VS_ACT_ENSET BIT(1)
#define HS_ACT_ENSET BIT(0)
#define HDMI_RX_MD_ISTS (HDMI_RX_BASE + 0x0fc8)
#define VACT_LIN_ISTS BIT(9)
#define HACT_PIX_ISTS BIT(6)
#define HS_CLK_ISTS BIT(5)
#define DE_ACTIVITY_ISTS BIT(2)
#define VS_ACT_ISTS BIT(1)
#define HS_ACT_ISTS BIT(0)
@@ -286,7 +301,9 @@
#define HDMI_RX_MD_ISET (HDMI_RX_BASE + 0x0fd4)
#define HDMI_RX_HDMI_IEN_CLR (HDMI_RX_BASE + 0x0fd8)
#define HDMI_RX_HDMI_IEN_SET (HDMI_RX_BASE + 0x0fdc)
#define CLK_CHANGE_ENSET BIT(6)
#define HDMI_RX_HDMI_ISTS (HDMI_RX_BASE + 0x0fe0)
#define CLK_CHANGE_ISTS BIT(6)
#define HDMI_RX_HDMI_IEN (HDMI_RX_BASE + 0x0fe4)
#define HDMI_RX_HDMI_ICLR (HDMI_RX_BASE + 0x0fe8)
#define HDCP_DKSET_DONE_ISTS_MASK BIT(31)