shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 19:08:57 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: vop2: add max dclk to filter unsupported resolution

Browse Source 
Before this commit, we use max_output.width to filter unsupported resolution,
but just like rk3576 vp0 can support 4k120 but can't support 4k144hz, so
we add max dclk to filer this resolution.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I44e8b7db33ca426226afb2137b2643ae09b97425
This commit is contained in:
Sandy Huang
2024-03-16 16:07:30 +08:00
committed by Tao Huang
parent 077e48341d
commit 4b46ff4a58
2 changed files with 12 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -7250,6 +7250,9 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
request_clock * 1000) / 1000;
}
if (request_clock > vp_data->dclk_max / 1000)
return MODE_CLOCK_HIGH;
/*
* Hdmi or DisplayPort request a Accurate clock.
*/

9
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1125,6 +1125,7 @@ static const struct vop2_video_port_data rk3528_vop_video_ports[] = {
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN | VOP_FEATURE_VIVID_HDR |
VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC | VOP_FEATURE_OUTPUT_10BIT,
.gamma_lut_len = 1024,
.dclk_max = 600000000,
.max_output = { 4096, 4096 },
.hdrvivid_dly = {17, 29, 32, 44, 15, 38, 1, 29, 0, 0},
.sdr2hdr_dly = 21,
@@ -1139,6 +1140,7 @@ static const struct vop2_video_port_data rk3528_vop_video_ports[] = {
.id = 1,
.soc_id = { 0x3528, 0x3528 },
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
.dclk_max = 108000000,
.max_output = { 720, 576 },
.hdrvivid_dly = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
.sdr2hdr_dly = 0,
@@ -1230,6 +1232,7 @@ static const struct vop2_video_port_data rk3562_vop_video_ports[] = {
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
.gamma_lut_len = 1024,
.cubic_lut_len = 729, /* 9x9x9 */
.dclk_max = 200000000,
.max_output = { 2048, 4096 },
.win_dly = 8,
.layer_mix_dly = 8,
@@ -1442,6 +1445,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
VOP_FEATURE_HDR10 | VOP_FEATURE_OVERSCAN,
.gamma_lut_len = 1024,
.cubic_lut_len = 729, /* 9x9x9 */
.dclk_max = 600000000,
.max_output = { 4096, 4096 },
.pre_scan_max_dly = { 69, 53, 53, 42 },
.intr = &rk3568_vp0_intr,
@@ -1453,6 +1457,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
.soc_id = { 0x3568, 0x3566 },
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
.gamma_lut_len = 1024,
.dclk_max = 200000000,
.max_output = { 2048, 2048 },
.pre_scan_max_dly = { 40, 40, 40, 40 },
.intr = &rk3568_vp1_intr,
@@ -1463,6 +1468,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
.soc_id = { 0x3568, 0x3566 },
.gamma_lut_len = 1024,
.dclk_max = 150000000,
.max_output = { 1920, 1920 },
.pre_scan_max_dly = { 40, 40, 40, 40 },
.intr = &rk3568_vp2_intr,
@@ -1739,6 +1745,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
VOP_FEATURE_POST_FRC_V2 | VOP_FEATURE_POST_SHARP,
.gamma_lut_len = 1024,
.cubic_lut_len = 729, /* 9x9x9 */
.dclk_max = 600000000,
.max_output = { 4096, 4096 },
.hdrvivid_dly = {17, 29, 32, 44, 15, 38, 1, 29, 0, 0},
.sdr2hdr_dly = 21,
@@ -1757,6 +1764,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN | VOP_FEATURE_OUTPUT_10BIT |
VOP_FEATURE_POST_FRC_V2,
.gamma_lut_len = 1024,
.dclk_max = 300000000,
.max_output = { 2560, 2560 },
.hdrvivid_dly = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
.sdr2hdr_dly = 0,
@@ -1774,6 +1782,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
.lut_dma_rid = 0x3,/* lut axi id length is 4 bits */
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
.gamma_lut_len = 1024,
.dclk_max = 150000000,
.max_output = { 1920, 1920 },
.hdrvivid_dly = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
.sdr2hdr_dly = 0,