shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 21:07:02 +09:00
Code Issues Packages Projects Releases Wiki Activity

rk2928: add lcdc support and add rga config

Browse Source
This commit is contained in:
kfx
2012-07-17 21:02:16 +08:00
parent e6a9f68960
commit 4b68042201
7 changed files with 1523 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm/configs/rk2928_fpga_defconfig
View File

@@ -76,6 +76,21 @@ CONFIG_SPI_FPGA_GPIO_NUM=0
CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_ION=y
CONFIG_ION_ROCKCHIP=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
CONFIG_DISPLAY_SUPPORT=y
CONFIG_LCD_TD043MGEA1=y
CONFIG_FB_ROCKCHIP=y
CONFIG_LCDC_RK2928=y
# CONFIG_THREE_FB_BUFFER is not set
CONFIG_RGA_RK30=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y

62
arch/arm/mach-rk2928/board-rk2928-fpga.c Normal file → Executable file
View File

@@ -43,6 +43,57 @@
#include <linux/rfkill-rk.h>
#include <linux/sensor-dev.h>
#define RK2928_FB_MEM_SIZE 3*SZ_1M
#ifdef CONFIG_FB_ROCKCHIP
static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
{
return 0;
}
static int rk_fb_io_disable(void)
{
return 0;
}
static int rk_fb_io_enable(void)
{
return 0;
}
#if defined(CONFIG_LCDC_RK2928)
struct rk29fb_info lcdc_screen_info = {
.prop = PRMRY, //primary display device
.io_init = rk_fb_io_init,
.io_disable = rk_fb_io_disable,
.io_enable = rk_fb_io_enable,
.set_screen_info = set_lcd_info,
};
#endif
static struct resource resource_fb[] = {
[0] = {
.name = "fb0 buf",
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "ipp buf", //for rotate
.start = 0,
.end = 0,//RK30_FB0_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device device_fb = {
.name = "rk-fb",
.id = -1,
.num_resources = ARRAY_SIZE(resource_fb),
.resource = resource_fb,
};
#endif
//i2c
#ifdef CONFIG_I2C0_RK30
static struct i2c_board_info __initdata i2c0_info[] = {
@@ -87,6 +138,9 @@ static struct spi_board_info board_spi_devices[] = {
};
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_FB_ROCKCHIP
&device_fb,
#endif
};
static void __init rk2928_board_init(void)
@@ -98,6 +152,10 @@ static void __init rk2928_board_init(void)
static void __init rk2928_reserve(void)
{
#ifdef CONFIG_FB_ROCKCHIP
resource_fb[0].start = board_mem_reserve_add("fb0", RK2928_FB_MEM_SIZE);
resource_fb[0].end = resource_fb[0].start + RK2928_FB_MEM_SIZE - 1;
#endif
board_mem_reserved();
}
@@ -145,6 +203,10 @@ static struct clk_lookup clks[] = {
CLK("rk29_i2s.0", "i2s_frac_div", &xin24m),
CLK("rk29_i2s.0", "i2s", &xin24m),
CLK("rk29_i2s.0", "hclk_i2s", &xin24m),
CLK(NULL, "pd_lcdc0", &xin24m),
CLK(NULL, "hclk_lcdc0", &xin24m),
CLK(NULL, "aclk_lcdc0", &xin24m),
CLK(NULL, "dclk_lcdc0", &xin24m),
};
void __init rk30_clock_init(void)

35
arch/arm/mach-rk2928/devices.c
View File

@@ -181,6 +181,38 @@ static void __init rk2928_init_uart(void)
platform_device_register(&device_uart2);
#endif
}
//LCDC
#ifdef CONFIG_LCDC_RK2928
extern struct rk29fb_info lcdc_screen_info;
static struct resource resource_lcdc[] = {
[0] = {
.name = "lcdc reg",
.start = RK2928_LCDC_PHYS,
.end = RK2928_LCDC_PHYS + RK2928_LCDC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "lcdc irq",
.start = IRQ_LCDC,
.end = IRQ_LCDC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device device_lcdc = {
.name = "rk2928-lcdc",
.id = 0,
.num_resources = ARRAY_SIZE(resource_lcdc),
.resource = resource_lcdc,
.dev = {
.platform_data = &lcdc_screen_info,
},
};
#endif
// i2c
#ifdef CONFIG_I2C0_CONTROLLER_RK29
#define I2C0_ADAP_TYPE I2C_RK29_ADAP
@@ -578,6 +610,9 @@ static int __init rk2928_init_devices(void)
#ifdef CONFIG_RGA_RK30
platform_device_register(&device_rga);
#endif
#ifdef CONFIG_LCDC_RK2928
platform_device_register(&device_lcdc);
#endif
#if defined(CONFIG_FIQ_DEBUGGER) && defined(DEBUG_UART_PHYS)
rk_serial_debug_init(DEBUG_UART_BASE, IRQ_DEBUG_UART, IRQ_UART_SIGNAL, -1);
#endif

6
drivers/video/rockchip/Kconfig Normal file → Executable file
View File

@@ -33,7 +33,11 @@ config LCDC1_RK30
default y if HDMI_RK30
help
Support rk30 lcdc1 if you say y here
config LCDC_RK2928
tristate "rk2928 lcdc support "
depends on FB_ROCKCHIP
help
Driver for rk2928 lcdc .
config DUAL_DISP_IN_KERNEL
bool "implement dual display in kernel"
depends on FB_ROCKCHIP

3
drivers/video/rockchip/Makefile Normal file → Executable file
View File

@@ -1,5 +1,6 @@
obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o rkfb_sysfs.o
obj-$(CONFIG_FB_WIMO) +=wimo.o
obj-$(CONFIG_LCDC_RK30) += chips/rk30_lcdc.o
obj-$(CONFIG_LCDC_RK30) += chips/rk30_lcdc.o
obj-$(CONFIG_LCDC_RK2928) += chips/rk2928_lcdc.o
obj-$(CONFIG_RGA_RK30) += rga/
obj-$(CONFIG_HDMI_RK30) += hdmi/

952
drivers/video/rockchip/chips/rk2928_lcdc.c Executable file
View File

@@ -0,0 +1,952 @@
/*
* drivers/video/rockchip/chips/rk2928_lcdc.c
*
* Copyright (C) 2012 ROCKCHIP, Inc.
*Author:yzq<yzq@rock-chips.com>
* yxj<yxj@rock-chips.com>
*This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/earlysuspend.h>
#include <asm/div64.h>
#include <asm/uaccess.h>
#include "rk2928_lcdc.h"
static int dbg_thresd = 0;
module_param(dbg_thresd, int, S_IRUGO|S_IWUSR);
#define DBG(level,x...) do { if(unlikely(dbg_thresd > level)) printk(KERN_INFO x); } while (0)
static int init_rk2928_lcdc(struct rk_lcdc_device_driver *dev_drv)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
if(lcdc_dev->id == 0) //lcdc0
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc0");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0");
}
else if(lcdc_dev->id == 1)
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc1");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1");
}
else
{
printk(KERN_ERR "invalid lcdc device!\n");
return -EINVAL;
}
if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk)))
{
printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id);
}
clk_enable(lcdc_dev->pd);
clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config
clk_enable(lcdc_dev->aclk);
lcdc_dev->clk_on = 1;
LcdSetBit(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power
LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN |
m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) |
v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync
LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective
return 0;
}
static int rk2928_lcdc_deinit(struct rk2928_lcdc_device *lcdc_dev)
{
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_dev->clk_on = 0;
LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1));
LcdMskReg(lcdc_dev, INT_STATUS, m_HOR_START_INT_EN | m_FRM_START_INT_EN |
m_LINE_FLAG_INT_EN | m_BUS_ERR_INT_EN,v_HOR_START_INT_EN(0) | v_FRM_START_INT_EN(0) |
v_LINE_FLAG_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt
LcdSetBit(lcdc_dev,SYS_CFG,m_LCDC_STANDBY);
LCDC_REG_CFG_DONE();
spin_unlock(&lcdc_dev->reg_lock);
}
else //clk already disabled
{
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
mdelay(1);
return 0;
}
static int rk2928_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen)
{
int ret = -EINVAL;
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
rk_screen *screen = lcdc_dev->screen;
u64 ft;
int fps;
u16 face;
u16 right_margin = screen->right_margin;
u16 lower_margin = screen->lower_margin;
u16 x_res = screen->x_res, y_res = screen->y_res;
// set the rgb or mcu
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
if(screen->type==SCREEN_MCU)
{
printk(KERN_ERR "MCU Screen is not supported by RK2928\n");
}
switch (screen->face)
{
case OUT_P565:
face = OUT_P565;
LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));
break;
case OUT_P666:
face = OUT_P666;
LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));
break;
case OUT_D888_P565:
face = OUT_P888;
LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));
break;
case OUT_D888_P666:
face = OUT_P888;
LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));
break;
case OUT_P888:
face = OUT_P888;
LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_UP_EN, v_DITHER_UP_EN(1));
LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0));
break;
default:
LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_UP_EN, v_DITHER_UP_EN(0));
LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0));
face = screen->face;
break;
}
//use default overlay,set vsyn hsync den dclk polarity
LcdMskReg(lcdc_dev, DSP_CTRL,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY |
m_DEN_POLARITY |m_DCLK_POLARITY | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_BLACK_MODE,
v_DISPLAY_FORMAT(face) | v_HSYNC_POLARITY(screen->pin_hsync) |
v_VSYNC_POLARITY(screen->pin_vsync) | v_DEN_POLARITY(screen->pin_den) |
v_DCLK_POLARITY(screen->pin_dclk) | v_OUTPUT_RB_SWAP(screen->swap_rb) |
v_OUTPUT_RG_SWAP(screen->swap_rg) |v_BLACK_MODE(0));
//set background color to black,set swap according to the screen panel,disable blank mode
LcdMskReg(lcdc_dev, BG_COLOR, m_BG_COLOR ,v_BG_COLOR(0x000000));
LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) |
v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin));
LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) |
v_HASP(screen->hsync_len + screen->left_margin));
LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) |
v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin));
LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)|
v_VASP(screen->vsync_len + screen->upper_margin));
// let above to take effect
LCDC_REG_CFG_DONE();
}
spin_unlock(&lcdc_dev->reg_lock);
ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock);
if(ret)
{
printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id);
}
lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
clk_enable(lcdc_dev->dclk);
ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)*
(screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)*
(dev_drv->pixclock); // one frame time ,(pico seconds)
fps = div64_u64(1000000000000llu,ft);
screen->ft = 1000/fps;
printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps);
if(screen->init)
{
screen->init();
}
printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id);
return 0;
}
//enable layer,open:1,enable;0 disable
static int win0_open(struct rk2928_lcdc_device *lcdc_dev,bool open)
{
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
if(open)
{
if(!lcdc_dev->atv_layer_cnt)
{
LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY);
}
lcdc_dev->atv_layer_cnt++;
}
else
{
lcdc_dev->atv_layer_cnt--;
}
lcdc_dev->driver.layer_par[0]->state = open;
LcdMskReg(lcdc_dev, SYS_CFG, m_W0_EN, v_W0_EN(open));
if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc
{
LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY);
}
LCDC_REG_CFG_DONE();
}
spin_unlock(&lcdc_dev->reg_lock);
printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed");
return 0;
}
static int win1_open(struct rk2928_lcdc_device *lcdc_dev,bool open)
{
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
if(open)
{
if(!lcdc_dev->atv_layer_cnt)
{
printk("lcdc%d wakeup from stanby\n",lcdc_dev->id);
LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY);
}
lcdc_dev->atv_layer_cnt++;
}
else
{
lcdc_dev->atv_layer_cnt--;
}
lcdc_dev->driver.layer_par[1]->state = open;
LcdMskReg(lcdc_dev, SYS_CFG, m_W1_EN, v_W1_EN(open));
if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc
{
printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id);
LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY);
}
LCDC_REG_CFG_DONE();
}
spin_unlock(&lcdc_dev->reg_lock);
printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed");
return 0;
}
static int rk2928_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode)
{
struct rk2928_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk2928_lcdc_device ,driver);
printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
switch(blank_mode)
{
case FB_BLANK_UNBLANK:
LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(0));
break;
case FB_BLANK_NORMAL:
LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(1));
break;
default:
LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(1));
break;
}
LCDC_REG_CFG_DONE();
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int win0_display(struct rk2928_lcdc_device *lcdc_dev,struct layer_par *par )
{
u32 y_addr;
u32 uv_addr;
y_addr = par->smem_start + par->y_offset;
uv_addr = par->cbr_start + par->c_offset;
DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
LcdWrReg(lcdc_dev, WIN0_YRGB_MST,y_addr);
LcdWrReg(lcdc_dev, WIN0_CBR_MST,uv_addr);
LCDC_REG_CFG_DONE();
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int win1_display(struct rk2928_lcdc_device *lcdc_dev,struct layer_par *par )
{
u32 y_addr;
u32 uv_addr;
y_addr = par->smem_start + par->y_offset;
uv_addr = par->cbr_start + par->c_offset;
DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
LcdWrReg(lcdc_dev, WIN1_RGB_MST, y_addr);
LCDC_REG_CFG_DONE();
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int win0_set_par(struct rk2928_lcdc_device *lcdc_dev,rk_screen *screen,
struct layer_par *par )
{
u32 xact, yact, xvir, yvir, xpos, ypos;
u32 ScaleYrgbX = 0x1000;
u32 ScaleYrgbY = 0x1000;
u32 ScaleCbrX = 0x1000;
u32 ScaleCbrY = 0x1000;
xact = par->xact; //active (origin) picture window width/height
yact = par->yact;
xvir = par->xvir; // virtual resolution
yvir = par->yvir;
xpos = par->xpos+screen->left_margin + screen->hsync_len;
ypos = par->ypos+screen->upper_margin + screen->vsync_len;
ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor
ScaleYrgbY = CalScale(yact, par->ysize);
switch (par->format)
{
case YUV422:// yuv422
ScaleCbrX = CalScale((xact/2), par->xsize);
ScaleCbrY = CalScale(yact, par->ysize);
break;
case YUV420: // yuv420
ScaleCbrX = CalScale(xact/2, par->xsize);
ScaleCbrY = CalScale(yact/2, par->ysize);
break;
case YUV444:// yuv444
ScaleCbrX = CalScale(xact, par->xsize);
ScaleCbrY = CalScale(yact, par->ysize);
break;
default:
break;
}
DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
__func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY));
LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY));
LcdMskReg(lcdc_dev, SYS_CFG, m_W0_FORMAT, v_W0_FORMAT(par->format)); //(inf->video_mode==0)
LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact));
LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos));
LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize));
LcdMskReg(lcdc_dev,WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,
v_COLORKEY_EN(1) | v_KEYCOLOR(0));
switch(par->format)
{
case ARGB888:
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_ARGB888_VIRWIDTH(xvir));
//LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1));
break;
case RGB888: //rgb888
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB888_VIRWIDTH(xvir));
//LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1));
break;
case RGB565: //rgb565
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB565_VIRWIDTH(xvir));
break;
case YUV422:
case YUV420:
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_YUV_VIRWIDTH(xvir));
break;
default:
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB888_VIRWIDTH(xvir));
break;
}
LCDC_REG_CFG_DONE();
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int win1_set_par(struct rk2928_lcdc_device *lcdc_dev,rk_screen *screen,
struct layer_par *par )
{
u32 xact, yact, xvir, yvir, xpos, ypos;
u32 ScaleYrgbX = 0x1000;
u32 ScaleYrgbY = 0x1000;
u32 ScaleCbrX = 0x1000;
u32 ScaleCbrY = 0x1000;
xact = par->xact;
yact = par->yact;
xvir = par->xvir;
yvir = par->yvir;
xpos = par->xpos+screen->left_margin + screen->hsync_len;
ypos = par->ypos+screen->upper_margin + screen->vsync_len;
DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
__func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
LcdMskReg(lcdc_dev,SYS_CFG, m_W1_FORMAT, v_W1_FORMAT(par->format));
LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos));
LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize));
// enable win1 color key and set the color to black(rgb=0)
LcdMskReg(lcdc_dev, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0));
switch(par->format)
{
case ARGB888:
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_ARGB888_VIRWIDTH(xvir));
//LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1));
break;
case RGB888: //rgb888
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir));
// LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1));
break;
case RGB565: //rgb565
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB565_VIRWIDTH(xvir));
break;
default:
LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir));
break;
}
LCDC_REG_CFG_DONE();
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int rk2928_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
if(layer_id == 0)
{
win0_open(lcdc_dev,open);
}
else if(layer_id == 1)
{
win1_open(lcdc_dev,open);
}
return 0;
}
static int rk2928_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
struct layer_par *par = NULL;
rk_screen *screen = lcdc_dev->screen;
if(!screen)
{
printk(KERN_ERR "screen is null!\n");
return -ENOENT;
}
if(layer_id==0)
{
par = dev_drv->layer_par[0];
win0_set_par(lcdc_dev,screen,par);
}
else if(layer_id==1)
{
par = dev_drv->layer_par[1];
win1_set_par(lcdc_dev,screen,par);
}
return 0;
}
int rk2928_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
struct layer_par *par = NULL;
rk_screen *screen = lcdc_dev->screen;
unsigned long flags;
int timeout;
if(!screen)
{
printk(KERN_ERR "screen is null!\n");
return -ENOENT;
}
if(layer_id==0)
{
par = dev_drv->layer_par[0];
win0_display(lcdc_dev,par);
}
else if(layer_id==1)
{
par = dev_drv->layer_par[1];
win1_display(lcdc_dev,par);
}
if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt
{
dev_drv->first_frame = 0;
LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR |m_FRM_START_INT_EN ,
v_FRM_START_INT_CLEAR(1) | v_FRM_START_INT_EN(1));
LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective
}
if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn
{
spin_lock_irqsave(&dev_drv->cpl_lock,flags);
init_completion(&dev_drv->frame_done);
spin_unlock_irqrestore(&dev_drv->cpl_lock,flags);
timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->screen->ft+5));
if(!timeout&&(!dev_drv->frame_done.done))
{
printk(KERN_ERR "wait for new frame start time out!\n");
return -ETIMEDOUT;
}
}
return 0;
}
int rk2928_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
u32 panel_size[2];
void __user *argp = (void __user *)arg;
int ret = 0;
switch(cmd)
{
case FBIOGET_PANEL_SIZE: //get panel size
panel_size[0] = lcdc_dev->screen->x_res;
panel_size[1] = lcdc_dev->screen->y_res;
if(copy_to_user(argp, panel_size, 8))
return -EFAULT;
break;
default:
break;
}
return ret;
}
static int rk2928_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
struct layer_par *par = dev_drv->layer_par[layer_id];
spin_lock(&lcdc_dev->reg_lock);
if(lcdc_dev->clk_on)
{
if(layer_id == 0)
{
par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W0_EN);
}
else if( layer_id == 1)
{
par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W1_EN);
}
}
spin_unlock(&lcdc_dev->reg_lock);
return par->state;
}
/***********************************
overlay manager
swap:1 win0 on the top of win1
0 win1 on the top of win0
set : 1 set overlay
0 get overlay state
************************************/
static int rk2928_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
int ovl;
spin_lock(&lcdc_dev->reg_lock);
if(lcdc_dev->clk_on)
{
if(set) //set overlay
{
LcdMskReg(lcdc_dev,DSP_CTRL,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap));
LCDC_REG_CFG_DONE();
ovl = swap;
}
else //get overlay
{
ovl = LcdReadBit(lcdc_dev,DSP_CTRL,m_W0W1_POSITION_SWAP);
}
}
else
{
ovl = -EPERM;
}
spin_unlock(&lcdc_dev->reg_lock);
return ovl;
}
static int rk2928_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,int layer_id)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
return 0;
}
/*******************************************
lcdc fps manager,set or get lcdc fps
set:0 get
1 set
********************************************/
static int rk2928_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
rk_screen * screen = dev_drv->screen;
u64 ft = 0;
u32 dotclk;
int ret;
if(set)
{
ft = div_u64(1000000000000llu,fps);
dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)*
(screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len));
dotclk = div_u64(1000000000000llu,dev_drv->pixclock);
ret = clk_set_rate(lcdc_dev->dclk, dotclk);
if(ret)
{
printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id);
}
dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
}
ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)*
(screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)*
(dev_drv->pixclock); // one frame time ,(pico seconds)
fps = div64_u64(1000000000000llu,ft);
screen->ft = 1000/fps ; //one frame time in ms
return fps;
}
int rk2928_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_dev->clk_on = 0;
LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1));
LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY);
LCDC_REG_CFG_DONE();
spin_unlock(&lcdc_dev->reg_lock);
}
else //clk already disabled
{
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
mdelay(1);
clk_disable(lcdc_dev->dclk);
clk_disable(lcdc_dev->hclk);
clk_disable(lcdc_dev->aclk);
clk_disable(lcdc_dev->pd);
return 0;
}
int rk2928_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv)
{
struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver);
if(!lcdc_dev->clk_on)
{
clk_enable(lcdc_dev->pd);
clk_enable(lcdc_dev->hclk);
clk_enable(lcdc_dev->dclk);
clk_enable(lcdc_dev->aclk);
}
memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0xc4); //resume reg
spin_lock(&lcdc_dev->reg_lock);
if(lcdc_dev->atv_layer_cnt)
{
LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY);
LCDC_REG_CFG_DONE();
}
lcdc_dev->clk_on = 1;
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static irqreturn_t rk2928_lcdc_isr(int irq, void *dev_id)
{
struct rk2928_lcdc_device *lcdc_dev = (struct rk2928_lcdc_device *)dev_id;
LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1));
LCDC_REG_CFG_DONE();
//LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1));
if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync
{
spin_lock(&(lcdc_dev->driver.cpl_lock));
complete(&(lcdc_dev->driver.frame_done));
spin_unlock(&(lcdc_dev->driver.cpl_lock));
}
return IRQ_HANDLED;
}
static struct layer_par lcdc_layer[] = {
[0] = {
.name = "win0",
.id = 0,
.support_3d = true,
},
[1] = {
.name = "win1",
.id = 1,
.support_3d = false,
},
};
static struct rk_lcdc_device_driver lcdc_driver = {
.name = "lcdc",
.def_layer_par = lcdc_layer,
.num_layer = ARRAY_SIZE(lcdc_layer),
.open = rk2928_lcdc_open,
.init_lcdc = init_rk2928_lcdc,
.ioctl = rk2928_lcdc_ioctl,
.suspend = rk2928_lcdc_early_suspend,
.resume = rk2928_lcdc_early_resume,
.set_par = rk2928_lcdc_set_par,
.blank = rk2928_lcdc_blank,
.pan_display = rk2928_lcdc_pan_display,
.load_screen = rk2928_load_screen,
.get_layer_state = rk2928_lcdc_get_layer_state,
.ovl_mgr = rk2928_lcdc_ovl_mgr,
.get_disp_info = rk2928_lcdc_get_disp_info,
.fps_mgr = rk2928_lcdc_fps_mgr,
};
#ifdef CONFIG_PM
static int rk2928_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
{
return 0;
}
static int rk2928_lcdc_resume(struct platform_device *pdev)
{
return 0;
}
#else
#define rk2928_lcdc_suspend NULL
#define rk2928_lcdc_resume NULL
#endif
static int __devinit rk2928_lcdc_probe (struct platform_device *pdev)
{
struct rk2928_lcdc_device *lcdc_dev=NULL;
rk_screen *screen;
struct rk29fb_info *screen_ctr_info;
struct resource *res = NULL;
struct resource *mem;
int ret = 0;
/*************Malloc rk2928lcdc_inf and set it to pdev for drvdata**********/
lcdc_dev = kzalloc(sizeof(struct rk2928_lcdc_device), GFP_KERNEL);
if(!lcdc_dev)
{
dev_err(&pdev->dev, ">>rk2928 lcdc device kmalloc fail!");
return -ENOMEM;
}
platform_set_drvdata(pdev, lcdc_dev);
lcdc_dev->id = pdev->id;
screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data;
screen = kzalloc(sizeof(rk_screen), GFP_KERNEL);
if(!screen)
{
dev_err(&pdev->dev, ">>rk2928 lcdc screen kmalloc fail!");
ret = -ENOMEM;
goto err0;
}
else
{
lcdc_dev->screen = screen;
}
/****************get lcdc0 reg *************************/
res = platform_get_resource(pdev, IORESOURCE_MEM,0);
if (res == NULL)
{
dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id);
ret = -ENOENT;
goto err1;
}
lcdc_dev->reg_phy_base = res->start;
lcdc_dev->len = resource_size(res);
mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name);
if (mem == NULL)
{
dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id);
ret = -ENOENT;
goto err1;
}
lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res));
if (lcdc_dev->reg_vir_base == NULL)
{
dev_err(&pdev->dev, "cannot map IO\n");
ret = -ENXIO;
goto err2;
}
lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base;
printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg);
lcdc_dev->driver.dev=&pdev->dev;
lcdc_dev->driver.screen = screen;
lcdc_dev->driver.screen_ctr_info = screen_ctr_info;
spin_lock_init(&lcdc_dev->reg_lock);
lcdc_dev->irq = platform_get_irq(pdev, 0);
if(lcdc_dev->irq < 0)
{
dev_err(&pdev->dev, "cannot find IRQ\n");
goto err3;
}
ret = request_irq(lcdc_dev->irq, rk2928_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev);
if (ret)
{
dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret);
ret = -EBUSY;
goto err3;
}
ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id);
if(ret < 0)
{
printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id);
goto err4;
}
printk("rk2928 lcdc%d probe ok!\n",lcdc_dev->id);
return 0;
err4:
free_irq(lcdc_dev->irq,lcdc_dev);
err3:
iounmap(lcdc_dev->reg_vir_base);
err2:
release_mem_region(lcdc_dev->reg_phy_base,resource_size(res));
err1:
kfree(screen);
err0:
platform_set_drvdata(pdev, NULL);
kfree(lcdc_dev);
return ret;
}
static int __devexit rk2928_lcdc_remove(struct platform_device *pdev)
{
struct rk2928_lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
rk_fb_unregister(&(lcdc_dev->driver));
rk2928_lcdc_deinit(lcdc_dev);
iounmap(lcdc_dev->reg_vir_base);
release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len);
kfree(lcdc_dev->screen);
kfree(lcdc_dev);
return 0;
}
static void rk2928_lcdc_shutdown(struct platform_device *pdev)
{
struct rk2928_lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
rk_fb_unregister(&(lcdc_dev->driver));
rk2928_lcdc_deinit(lcdc_dev);
/*iounmap(lcdc_dev->reg_vir_base);
release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len);
kfree(lcdc_dev->screen);
kfree(lcdc_dev);*/
}
static struct platform_driver rk2928lcdc_driver = {
.probe = rk2928_lcdc_probe,
.remove = __devexit_p(rk2928_lcdc_remove),
.driver = {
.name = "rk2928-lcdc",
.owner = THIS_MODULE,
},
.suspend = rk2928_lcdc_suspend,
.resume = rk2928_lcdc_resume,
.shutdown = rk2928_lcdc_shutdown,
};
static int __init rk2928_lcdc_init(void)
{
return platform_driver_register(&rk2928lcdc_driver);
}
static void __exit rk2928_lcdc_exit(void)
{
platform_driver_unregister(&rk2928lcdc_driver);
}
fs_initcall(rk2928_lcdc_init);
module_exit(rk2928_lcdc_exit);

452
drivers/video/rockchip/chips/rk2928_lcdc.h Executable file
View File

@@ -0,0 +1,452 @@
#ifndef RK2928_LCDC_H_
#define RK2928_LCDC_H_
#include<linux/rk_fb.h>
#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk))
#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val)
#define LcdRdReg(inf, addr) (inf->preg->addr)
#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk))
#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk))
#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk))
#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val))
#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb()
/********************************************************************
** <20>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD> *
********************************************************************/
/* LCDC<44>ļĴ<C4BC><C4B4><EFBFBD><EFBFBD>ṹ */
typedef volatile struct tagLCDC_REG
{
/* offset 0x00~0xc0 */
unsigned int SYS_CFG; //0x00 system config register
unsigned int DSP_CTRL; //0x0c display control register
unsigned int BG_COLOR; //back ground color register
unsigned int ALPHA_CTRL; //alpha control register
unsigned int INT_STATUS; //0x10 Interrupt status register
unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register
unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register
unsigned int WIN0_YRGB_MST; //0x28 Win0 active YRGB memory start address0
unsigned int WIN0_CBR_MST; //0x2c Win0 active Cbr memory start address0
unsigned int WIN_VIR; //0x38 WIN0 virtual display width/height
unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height
unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel
unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel
unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting
unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting
unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset
unsigned int WIN1_RGB_MST; //0x54 Win1 active YRGB memory start address
unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel
unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel
unsigned int HWC_MST; //0x88 HWC memory start address
unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel
unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2<><32>b01 look up table 0
unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2<><32>b10 look up table 1
unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2<><32>b11 look up table 2
unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point
unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point
unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point
unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point
unsigned int SCL_REG0; //scaler register
unsigned int SCL_REG1;
unsigned int SCL_REG2;
unsigned int SCL_REG3;
unsigned int SCL_REG4;
unsigned int SCL_REG5;
unsigned int SCL_REG6;
unsigned int SCL_REG7;
unsigned int SCL_REG8;
unsigned int reserve[3];
unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH
} LCDC_REG, *pLCDC_REG;
/* SYS_CONFIG */
#define m_W0_EN (1<<0)
#define m_W1_EN (1<<1)
#define m_HWC_EN (1<<2)
#define m_W0_FORMAT (7<<3)
#define m_W1_FORMAT (7<<6)
#define m_W0_AXI_OUTSTANDING_DISABLE (1<<16)
#define m_W1_AXI_OUTSTANDING_DISABLE (1<<17)
#define m_DMA_BURST_LENGTH (3<<18)
#define m_LCDC_STANDBY (1<<22)
#define m_LCDC_AXICLK_AUTO_ENABLE (1<<24) //eanble for low power
#define v_W0_EN(x) (((x)&1)<<0)
#define v_W1_EN(x) (((x)&1)<<1)
#define v_HWC_EN(x) (((x)&1)<<2)
#define v_W0_FORMAT(x) (((x)&7)<<3)
#define v_W1_FORMAT(x) (((x)&7)<<6)
#define v_LCDC_STANDBY(x) (((x)&1)<<22)
#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<24)
#define v_LCDC_DMA_STOP(x) (((x)&1)<<0)
#define v_HWC_RELOAD_EN(x) (((x)&1)<<2)
#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3)
#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4)
#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5)
#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6)
#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8)
#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11)
#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14)
#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17)
#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20)
#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23)
#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26)
#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29)
//LCDC_DSP_CTRL_REG
#define m_DISPLAY_FORMAT (3<<0)
#define m_BLANK_MODE (1<<2)
#define m_BLACK_MODE (1<<3)
#define m_HSYNC_POLARITY (1<<4)
#define m_VSYNC_POLARITY (1<<5)
#define m_DEN_POLARITY (1<<6)
#define m_DCLK_POLARITY (1<<7)
#define m_W0W1_POSITION_SWAP (1<<8)
#define m_OUTPUT_BG_SWAP (1<<9)
#define m_OUTPUT_RB_SWAP (1<<10)
#define m_OUTPUT_RG_SWAP (1<<11)
#define m_DITHER_UP_EN (1<<12)
#define m_DITHER_DOWN_MODE (1<<13)
#define m_DITHER_DOWN_EN (1<<14)
#define m_W1_INTERLACE_READ_MODE (1<<15)
#define m_W2_INTERLACE_READ_MODE (1<<16)
#define m_W0_YRGB_DEFLICK_MODE (1<<17)
#define m_W0_CBR_DEFLICK_MODE (1<<18)
#define m_W1_YRGB_DEFLICK_MODE (1<<19)
#define m_W1_CBR_DEFLICK_MODE (1<<20)
#define m_W0_ALPHA_MODE (1<<21)
#define m_W1_ALPHA_MODE (1<<22)
#define m_W2_ALPHA_MODE (1<<23)
#define m_W0_COLOR_SPACE_CONVERSION (3<<24)
#define m_W1_COLOR_SPACE_CONVERSION (3<<26)
#define m_W2_COLOR_SPACE_CONVERSION (1<<28)
#define m_YCRCB_CLIP_EN (1<<29)
#define m_CBR_FILTER_656 (1<<30)
#define v_DISPLAY_FORMAT(x) (((x)&0x3)<<0)
#define v_BLANK_MODE(x) (((x)&1)<<2)
#define v_BLACK_MODE(x) (((x)&1)<<2)
#define v_HSYNC_POLARITY(x) (((x)&1)<<4)
#define v_VSYNC_POLARITY(x) (((x)&1)<<5)
#define v_DEN_POLARITY(x) (((x)&1)<<6)
#define v_DCLK_POLARITY(x) (((x)&1)<<7)
#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8)
#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<9)
#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<10)
#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<11)
#define v_DITHER_UP_EN(x) (((x)&1)<<12)
#define v_DITHER_DOWN_MODE(x) (((x)&1)<<13)
#define v_DITHER_DOWN_EN(x) (((x)&1)<<14)
#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14)
#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15)
#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16)
#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17)
#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18)
#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19)
#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20)
#define v_W0_ALPHA_MODE(x) (((x)&1)<<21)
#define v_W1_ALPHA_MODE(x) (((x)&1)<<22)
#define v_W2_ALPHA_MODE(x) (((x)&1)<<23)
#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24)
#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26)
#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28)
#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29)
#define v_CBR_FILTER_656(x) (((x)&1)<<30)
//LCDC_BG_COLOR
#define m_BG_COLOR (0xffffff<<0)
#define m_BG_B (0xff<<0)
#define m_BG_G (0xff<<8)
#define m_BG_R (0xff<<16)
#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
#define v_BG_B(x) (((x)&0xff)<<0)
#define v_BG_G(x) (((x)&0xff)<<8)
#define v_BG_R(x) (((x)&0xff)<<16)
//LCDC_ BLEND_CTRL
#define m_HWC_BLEND_EN (1<<0)
#define m_W2_BLEND_EN (1<<1)
#define m_W1_BLEND_EN (1<<2)
#define m_W0_BLEND_EN (1<<3)
#define m_HWC_BLEND_FACTOR (15<<4)
#define m_W2_BLEND_FACTOR (0xff<<8)
#define m_W1_BLEND_FACTOR (0xff<<16)
#define m_W0_BLEND_FACTOR (0xff<<24)
#define v_HWC_BLEND_EN(x) (((x)&1)<<0)
#define v_W2_BLEND_EN(x) (((x)&1)<<1)
#define v_W1_BLEND_EN(x) (((x)&1)<<2)
#define v_W0_BLEND_EN(x) (((x)&1)<<3)
#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
//LCDC_INT_STATUS
#define v_HOR_START_INT_STA (1<<0) //status
#define v_FRM_START_INT_STA (1<<1)
#define v_LINE_FLAG_INT_STA (1<<2)
#define v_BUS_ERR_INT_STA (1<<3)
#define m_HOR_START_INT_EN (1<<4) //enable
#define m_FRM_START_INT_EN (1<<5)
#define m_LINE_FLAG_INT_EN (1<<6)
#define m_BUS_ERR_INT_EN (1<<7)
#define m_HOR_START_INT_CLEAR (1<<8) //auto clear
#define m_FRM_START_INT_CLEAR (1<<9)
#define m_LINE_FLAG_INT_CLEAR (1<<10)
#define m_BUS_ERR_INT_CLEAR (1<<11)
#define m_LINE_FLAG_NUM (0xfff<<12)
#define v_HOR_START_INT_EN(x) (((x)&1)<<4)
#define v_FRM_START_INT_EN(x) (((x)&1)<<5)
#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6)
#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8)
#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9)
#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10)
#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12)
//LCDC_WIN_VIR
#define m_WIN0_VIR (0xfff << 0)
#define m_WIN1_VIR (0xfff << 16)
//LCDC_WINx_VIR ,x is number of words of win0 virtual width
#define v_WIN0_ARGB888_VIRWIDTH(x) (x)
#define v_WIN0_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3))
#define v_WIN0_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0))
#define v_WIN0_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0))
#define v_WIN1_ARGB888_VIRWIDTH(x) (x << 16)
#define v_WIN1_RGB888_VIRWIDTH(x) ((((x*3)>>2)+((x)%3)) << 16)
#define v_WIN1_RGB565_VIRWIDTH(x) ((((x)>>1) + ((x%2)?1:0)) << 16)
#define v_WIN1_YUV_VIRWIDTH(x) ((((x)>>2) +((x%4)?1:0)) << 16 )
//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
#define m_KEYCOLOR (0xffffff<<0)
#define m_KEYCOLOR_B (0xff<<0)
#define m_KEYCOLOR_G (0xff<<8)
#define m_KEYCOLOR_R (0xff<<16)
#define m_COLORKEY_EN (1<<24)
#define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
#define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
#define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
#define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
#define v_COLORKEY_EN(x) (((x)&1)<<24)
//LCDC_DEFLICKER_SCL_OFFSET
#define m_W0_YRGB_VSD_OFFSET (0xff<<0)
#define m_W0_YRGB_VSP_OFFSET (0xff<<8)
#define m_W1_VSD_OFFSET (0xff<<16)
#define m_W1_VSP_OFFSET (0xff<<24)
#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
//AXI MS ID
#define m_W0_YRGB_CH_ID (0xF<<0)
#define m_W0_CBR_CH_ID (0xF<<4)
#define m_W1_YRGB_CH_ID (0xF<<8)
#define m_W2_CH_ID (0xF<<12)
#define m_HWC_CH_ID (0xF<<16)
#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
#define v_W2_CH_ID(x) (((x)&0xF)<<12)
#define v_HWC_CH_ID(x) (((x)&0xF)<<16)
/* Low Bits Mask */
#define m_WORDLO (0xffff<<0)
#define m_WORDHI (0xffff<<16)
#define v_WORDLO(x) (((x)&0xffff)<<0)
#define v_WORDHI(x) (((x)&0xffff)<<16)
//LCDC_WINx_SCL_FACTOR_Y/CBCR
#define v_X_SCL_FACTOR(x) ((x)<<0)
#define v_Y_SCL_FACTOR(x) ((x)<<16)
//LCDC_DSP_HTOTAL_HS_END
#define v_HSYNC(x) ((x)<<0) //hsync pulse width
#define v_HORPRD(x) ((x)<<16) //horizontal period
//LCDC_DSP_HACT_ST_END
#define v_HAEP(x) ((x)<<0) //horizontal active end point
#define v_HASP(x) ((x)<<16) //horizontal active start point
//LCDC_DSP_VTOTAL_VS_END
#define v_VSYNC(x) ((x)<<0)
#define v_VERPRD(x) ((x)<<16)
//LCDC_DSP_VACT_ST_END
#define v_VAEP(x) ((x)<<0)
#define v_VASP(x) ((x)<<16)
#define m_ACTWIDTH (0xffff<<0)
#define m_ACTHEIGHT (0xffff<<16)
#define v_ACTWIDTH(x) (((x)&0xffff)<<0)
#define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
#define m_VIRST_X (0xffff<<0)
#define m_VIRST_Y (0xffff<<16)
#define v_VIRST_X(x) (((x)&0xffff)<<0)
#define v_VIRST_Y(x) (((x)&0xffff)<<16)
#define m_PANELST_X (0x3ff<<0)
#define m_PANELST_Y (0x3ff<<16)
#define v_PANELST_X(x) (((x)&0x3ff)<<0)
#define v_PANELST_Y(x) (((x)&0x3ff)<<16)
#define m_PANELWIDTH (0x3ff<<0)
#define m_PANELHEIGHT (0x3ff<<16)
#define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
#define m_HWC_B (0xff<<0)
#define m_HWC_G (0xff<<8)
#define m_HWC_R (0xff<<16)
#define m_W0_YRGB_HSP_OFFSET (0xff<<24)
#define m_W0_YRGB_HSD_OFFSET (0xff<<24)
#define v_HWC_B(x) (((x)&0xff)<<0)
#define v_HWC_G(x) (((x)&0xff)<<8)
#define v_HWC_R(x) (((x)&0xff)<<16)
#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
//LCDC_WIN0_ACT_INFO
#define v_ACT_WIDTH(x) ((x-1)<<0)
#define v_ACT_HEIGHT(x) ((x-1)<<16)
//LCDC_WIN0_DSP_INFO
#define v_DSP_WIDTH(x) ((x-1)<<0)
#define v_DSP_HEIGHT(x) ((x-1)<<16)
//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning
#define v_DSP_STX(x) (x<<0)
#define v_DSP_STY(x) (x<<16)
//Panel display scanning
#define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
#define m_PANEL_END (0x3ff<<0)
#define m_PANEL_START (0x3ff<<16)
#define v_PANEL_END(x) (((x)&0x3ff)<<0)
#define v_PANEL_START(x) (((x)&0x3ff)<<16)
#define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
//-----------
#define m_HSCALE_FACTOR (0xffff<<0)
#define m_VSCALE_FACTOR (0xffff<<16)
#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
#define m_W0_CBR_HSD_OFFSET (0xff<<0)
#define m_W0_CBR_HSP_OFFSET (0xff<<8)
#define m_W0_CBR_VSD_OFFSET (0xff<<16)
#define m_W0_CBR_VSP_OFFSET (0xff<<24)
#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
#define CalScale(x, y) (((u32)x*0x1000)/y)
struct rk2928_lcdc_device{
int id;
struct rk_lcdc_device_driver driver;
rk_screen *screen;
LCDC_REG *preg; // LCDC reg base address and backup reg
LCDC_REG regbak;
void __iomem *reg_vir_base; // virtual basic address of lcdc register
u32 reg_phy_base; // physical basic address of lcdc register
u32 len; // physical map length of lcdc register
spinlock_t reg_lock; //one time only one process allowed to config the register
bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
unsigned int irq;
struct clk *pd; //lcdc power domain
struct clk *hclk; //lcdc AHP clk
struct clk *dclk; //lcdc dclk
struct clk *aclk; //lcdc share memory frequency
struct clk *aclk_parent; //lcdc aclk divider frequency source
struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable.
struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable.
struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable.
struct clk *pd_display; // display power domain
u32 pixclock;
};
struct lcdc_info{
/*LCD CLK*/
struct rk2928_lcdc_device lcdc0;
};
struct win_set {
volatile u32 y_offset;
volatile u32 c_offset;
};
struct win0_par {
u32 refcount;
u32 pseudo_pal[16];
u32 y_offset;
u32 c_offset;
u32 xpos; //size in panel
u32 ypos;
u32 xsize; //start point in panel
u32 ysize;
enum data_format format;
wait_queue_head_t wait;
struct win_set mirror;
struct win_set displ;
struct win_set done;
u8 par_seted;
u8 addr_seted;
};
#endif