ARM: rockchip: rk3188 add DDR init

arch/arm/mach-rockchip/ddr.h

@@ -0,0 +1,52 @@
+/*
+ *
+ * Copyright (C) 2011-2014 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_ROCKCHIP_DDR_H
+#define __MACH_ROCKCHIP_DDR_H
+
+#define DDR3_800D   (0)     // 5-5-5
+#define DDR3_800E   (1)     // 6-6-6
+#define DDR3_1066E  (2)     // 6-6-6
+#define DDR3_1066F  (3)     // 7-7-7
+#define DDR3_1066G  (4)     // 8-8-8
+#define DDR3_1333F  (5)     // 7-7-7
+#define DDR3_1333G  (6)     // 8-8-8
+#define DDR3_1333H  (7)     // 9-9-9
+#define DDR3_1333J  (8)     // 10-10-10
+#define DDR3_1600G  (9)     // 8-8-8
+#define DDR3_1600H  (10)    // 9-9-9
+#define DDR3_1600J  (11)    // 10-10-10
+#define DDR3_1600K  (12)    // 11-11-11
+#define DDR3_1866J  (13)    // 10-10-10
+#define DDR3_1866K  (14)    // 11-11-11
+#define DDR3_1866L  (15)    // 12-12-12
+#define DDR3_1866M  (16)    // 13-13-13
+#define DDR3_2133K  (17)    // 11-11-11
+#define DDR3_2133L  (18)    // 12-12-12
+#define DDR3_2133M  (19)    // 13-13-13
+#define DDR3_2133N  (20)    // 14-14-14
+#define DDR3_DEFAULT (21)
+#define DDR_DDR2     (22)
+#define DDR_LPDDR    (23)
+#define DDR_LPDDR2   (24)
+
+struct ddr_freq_t {
+    unsigned long screen_ft_us;
+    unsigned long long t0;
+    unsigned long long t1;
+    unsigned long t2;
+};
+
+#endif

arch/arm/mach-rockchip/ddr_reg_resume.inc

@@ -0,0 +1,298 @@
+    0xea00008e ,
+    0xe3a03000 ,
+    0xe92d4010 ,
+    0xe1530002 ,
+    0x37914103 ,
+    0x37804103 ,
+    0x32833001 ,
+    0x3afffffa ,
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+    0xe59f1470 ,
+    0xe5910004 ,
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+    0x3afffffb ,
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+    0xafffffc ,
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+    0xe592100c ,
+    0xe3110002 ,
+    0xafffffc ,
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+    0xe5901008 ,
+    0xe2011007 ,
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+    0xe3a01000 ,
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+    0xe5901014 ,
+    0xe3811101 ,
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+    0xe59011cc ,
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+    0xe58011cc ,
+    0xe590120c ,
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+    0xe580120c ,
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+    0xe580124c ,
+    0xe590128c ,
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+    0xe3a00000 ,
+    0xe2800001 ,
+    0xe3500ffa ,
+    0x3afffffc ,
+    0xe12fff1e ,
+    0xe92d40f0 ,
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+    0xebfffeff ,
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+    0xe8bd40f0 ,
+    0xeaffff1c ,
+    0x20040000 ,
+    0x200200c0 ,
+    0x10128000 ,

arch/arm/mach-rockchip/rk3188.c

@@ -147,3 +147,18 @@ static int __init rk3188_pie_init(void)
 	return 0;
 }
 arch_initcall(rk3188_pie_init);
+
+#define CONFIG_ARCH_RK3188
+#define RK30_DDR_PCTL_BASE RK_DDR_VIRT
+#define RK30_DDR_PUBL_BASE (RK_DDR_VIRT + RK3188_DDR_PCTL_SIZE)
+#define rk_pll_flag() 0 /* FIXME */
+#define sram_printascii(s) do {} while (0) /* FIXME */
+#include "ddr_rk30.c"
+
+static int rk3188_ddr_init(void)
+{
+	if (cpu_is_rk3188())
+		ddr_init(DDR3_DEFAULT, 300);
+	return 0;
+}
+arch_initcall_sync(rk3188_ddr_init);