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media: rockchip: hdmirx: add interface for user to set EDID
Signed-off-by: Chen Shunqing <csq@rock-chips.com> Change-Id: I6fd46c472a35e13db55dc67de34943e7f2194a1c
This commit is contained in:
Chen Shunqing
@@ -121,6 +121,12 @@ enum hdmirx_reg_attr {
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HDMIRX_ATTR_RE = 3,
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};
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enum hdmirx_edid_version {
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HDMIRX_EDID_USER = 0,
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HDMIRX_EDID_340M = 1,
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HDMIRX_EDID_600M = 2,
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};
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struct hdmirx_reg_table {
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int reg_base;
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int reg_end;
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@@ -195,6 +201,7 @@ struct rk_hdmirx_dev {
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struct regmap *vo1_grf;
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struct rk_hdmirx_hdcp *hdcp;
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void __iomem *regs;
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int edid_version;
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int audio_present;
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int hdmi_irq;
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int dma_irq;
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@@ -220,6 +227,7 @@ struct rk_hdmirx_dev {
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u32 cpu_freq_khz;
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u32 bound_cpu;
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u32 wdt_cfg_bound_cpu;
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u8 edid[EDID_BLOCK_SIZE * 2];
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hdmi_codec_plugged_cb plugged_cb;
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spinlock_t dma_rst_lock;
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};
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@@ -234,41 +242,78 @@ static void hdmirx_audio_handle_plugged_change(struct rk_hdmirx_dev *hdmirx_dev,
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static void hdmirx_audio_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en);
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static int hdmirx_set_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev);
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static void hdmirx_cancel_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev);
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static void hdmirx_plugout(struct rk_hdmirx_dev *hdmirx_dev);
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static u8 edid_init_data[] = {
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static u8 edid_init_data_340M[] = {
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0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
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0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
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0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
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0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
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0x09, 0x48, 0x4C, 0x21, 0x08, 0x00, 0x61, 0x40,
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0x01, 0x01, 0x81, 0x00, 0x95, 0x00, 0xA9, 0xC0,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x08, 0xE8,
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0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58,
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0x8A, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
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0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
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0x58, 0x2C, 0x45, 0x00, 0xB9, 0xA8, 0x42, 0x00,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
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0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
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0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
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0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
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0x6E, 0x28, 0x55, 0x00, 0x20, 0xC2, 0x31, 0x00,
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0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
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0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
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0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
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0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA3,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA7,
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0x02, 0x03, 0x36, 0xD2, 0x51, 0x07, 0x16, 0x14,
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0x02, 0x03, 0x2F, 0xD1, 0x51, 0x07, 0x16, 0x14,
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0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F,
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0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09,
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0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
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0x0C, 0x00, 0x30, 0x00, 0x10, 0x44, 0xE3, 0x05,
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0x03, 0x01, 0xE4, 0x0F, 0x00, 0x80, 0x01, 0x02,
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0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58,
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0x2C, 0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00,
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0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F,
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};
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static u8 edid_init_data_600M[] = {
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0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
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0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
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0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
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0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
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0x09, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x08, 0xE8,
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0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58,
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0x8A, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
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0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80,
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0xB0, 0x58, 0x8A, 0x00, 0x20, 0xC2, 0x31, 0x00,
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0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
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0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
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0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
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0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x39,
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0x02, 0x03, 0x21, 0xD2, 0x41, 0x61, 0x23, 0x09,
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0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x66, 0x03,
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0x0C, 0x00, 0x30, 0x00, 0x10, 0x67, 0xD8, 0x5D,
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0xC4, 0x01, 0x78, 0xC0, 0x07, 0xE3, 0x05, 0x03,
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0x01, 0xE4, 0x0F, 0x00, 0xF0, 0x01, 0x08, 0xE8,
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0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58,
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0x8A, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
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0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
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0x58, 0x2C, 0x45, 0x00, 0xB9, 0xA8, 0x42, 0x00,
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0x00, 0x9E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x01, 0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70, 0x5A,
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0x80, 0xB0, 0x58, 0x8A, 0x00, 0xC4, 0x8E, 0x21,
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0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBD,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE8,
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};
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static const struct v4l2_dv_timings_cap hdmirx_timings_cap = {
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@@ -817,6 +862,7 @@ static int hdmirx_write_edid(struct rk_hdmirx_dev *hdmirx_dev,
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return 0;
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}
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memset(&hdmirx_dev->edid, 0, sizeof(hdmirx_dev->edid));
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hdmirx_hpd_ctrl(hdmirx_dev, false);
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hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
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EDID_READ_EN_MASK |
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@@ -857,6 +903,7 @@ static int hdmirx_write_edid(struct rk_hdmirx_dev *hdmirx_dev,
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EDID_WRITE_EN(0));
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hdmirx_dev->edid_blocks_written = edid->blocks;
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memcpy(&hdmirx_dev->edid, edid->edid, edid->blocks * EDID_BLOCK_SIZE);
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if (hpd_up) {
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if (tx_5v_power_present(hdmirx_dev))
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hdmirx_hpd_ctrl(hdmirx_dev, true);
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@@ -871,7 +918,23 @@ static int hdmirx_set_edid(struct file *file, void *fh,
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struct hdmirx_stream *stream = video_drvdata(file);
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struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
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return hdmirx_write_edid(hdmirx_dev, edid, true);
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disable_irq(hdmirx_dev->hdmi_irq);
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disable_irq(hdmirx_dev->dma_irq);
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sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_DIS, RK_IRQ_HDMIRX_HDMI, 0);
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if (tx_5v_power_present(hdmirx_dev))
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hdmirx_plugout(hdmirx_dev);
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hdmirx_write_edid(hdmirx_dev, edid, false);
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hdmirx_dev->edid_version = HDMIRX_EDID_USER;
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enable_irq(hdmirx_dev->hdmi_irq);
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enable_irq(hdmirx_dev->dma_irq);
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sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_EN, RK_IRQ_HDMIRX_HDMI, 0);
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schedule_delayed_work_on(hdmirx_dev->bound_cpu,
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&hdmirx_dev->delayed_work_hotplug,
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msecs_to_jiffies(200));
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return 0;
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}
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static int hdmirx_get_edid(struct file *file, void *fh,
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@@ -880,7 +943,6 @@ static int hdmirx_get_edid(struct file *file, void *fh,
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struct hdmirx_stream *stream = video_drvdata(file);
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struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
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struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
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u32 i;
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memset(edid->reserved, 0, sizeof(edid->reserved));
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@@ -902,26 +964,13 @@ static int hdmirx_get_edid(struct file *file, void *fh,
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if (edid->start_block + edid->blocks > hdmirx_dev->edid_blocks_written)
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edid->blocks = hdmirx_dev->edid_blocks_written - edid->start_block;
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hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
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EDID_READ_EN_MASK |
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EDID_WRITE_EN_MASK,
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EDID_READ_EN(1) |
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EDID_WRITE_EN(0));
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for (i = 0; i < (edid->blocks * EDID_BLOCK_SIZE); i++)
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edid->edid[i] = hdmirx_readl(hdmirx_dev, DMA_STATUS14);
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memcpy(edid->edid, &hdmirx_dev->edid, edid->blocks * EDID_BLOCK_SIZE);
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v4l2_dbg(1, debug, v4l2_dev, "%s: Read EDID: =====\n", __func__);
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if (debug > 0)
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
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edid->edid, edid->blocks * EDID_BLOCK_SIZE, false);
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hdmirx_update_bits(hdmirx_dev, DMA_CONFIG11,
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EDID_READ_EN_MASK |
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EDID_WRITE_EN_MASK,
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EDID_READ_EN(0) |
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EDID_WRITE_EN(0));
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return 0;
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}
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@@ -2308,6 +2357,56 @@ static void hdmirx_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en)
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}
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}
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static void hdmirx_plugin(struct rk_hdmirx_dev *hdmirx_dev)
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{
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cpu_latency_qos_update_request(&hdmirx_dev->pm_qos, 0);
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schedule_delayed_work_on(hdmirx_dev->bound_cpu,
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&hdmirx_dev->delayed_work_heartbeat, msecs_to_jiffies(10));
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sip_wdt_config(WDT_START, 0, 0, 0);
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hdmirx_set_cpu_limit_freq(hdmirx_dev);
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hdmirx_submodule_init(hdmirx_dev);
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hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
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POWERPROVIDED);
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hdmirx_hpd_ctrl(hdmirx_dev, true);
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hdmirx_phy_config(hdmirx_dev);
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hdmirx_audio_setup(hdmirx_dev);
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hdmirx_wait_lock_and_get_timing(hdmirx_dev);
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hdmirx_dma_config(hdmirx_dev);
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hdmirx_interrupts_setup(hdmirx_dev, true);
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hdmirx_audio_handle_plugged_change(hdmirx_dev, 1);
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if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp_start)
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hdmirx_dev->hdcp->hdcp_start(hdmirx_dev->hdcp);
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}
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static void hdmirx_plugout(struct rk_hdmirx_dev *hdmirx_dev)
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{
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hdmirx_audio_handle_plugged_change(hdmirx_dev, 0);
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hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0);
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hdmirx_interrupts_setup(hdmirx_dev, false);
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hdmirx_hpd_ctrl(hdmirx_dev, false);
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hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
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hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
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LINE_FLAG_INT_EN |
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HDMIRX_DMA_IDLE_INT |
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HDMIRX_LOCK_DISABLE_INT |
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LAST_FRAME_AXI_UNFINISH_INT_EN |
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FIFO_OVERFLOW_INT_EN |
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FIFO_UNDERFLOW_INT_EN |
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HDMIRX_AXI_ERROR_INT_EN, 0);
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hdmirx_reset_dma(hdmirx_dev);
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hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
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HDMI_DISABLE | PHY_RESET | PHY_PDDQ,
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HDMI_DISABLE);
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hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x0);
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cancel_delayed_work(&hdmirx_dev->delayed_work_res_change);
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cancel_delayed_work(&hdmirx_dev->delayed_work_audio);
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cpu_latency_qos_update_request(&hdmirx_dev->pm_qos, PM_QOS_DEFAULT_VALUE);
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hdmirx_cancel_cpu_limit_freq(hdmirx_dev);
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cancel_delayed_work(&hdmirx_dev->delayed_work_heartbeat);
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flush_work(&hdmirx_dev->work_wdt_config);
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sip_wdt_config(WDT_STOP, 0, 0, 0);
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}
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static void hdmirx_delayed_work_hotplug(struct work_struct *work)
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{
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struct delayed_work *dwork = to_delayed_work(work);
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@@ -2322,51 +2421,11 @@ static void hdmirx_delayed_work_hotplug(struct work_struct *work)
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v4l2_ctrl_s_ctrl(hdmirx_dev->detect_tx_5v_ctrl, plugin);
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v4l2_dbg(1, debug, v4l2_dev, "%s: plugin:%d\n", __func__, plugin);
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if (plugin) {
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cpu_latency_qos_update_request(&hdmirx_dev->pm_qos, 0);
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schedule_delayed_work_on(hdmirx_dev->bound_cpu,
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&hdmirx_dev->delayed_work_heartbeat, msecs_to_jiffies(10));
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sip_wdt_config(WDT_START, 0, 0, 0);
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hdmirx_set_cpu_limit_freq(hdmirx_dev);
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hdmirx_submodule_init(hdmirx_dev);
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hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
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POWERPROVIDED);
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hdmirx_hpd_ctrl(hdmirx_dev, true);
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hdmirx_phy_config(hdmirx_dev);
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hdmirx_audio_setup(hdmirx_dev);
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hdmirx_wait_lock_and_get_timing(hdmirx_dev);
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hdmirx_dma_config(hdmirx_dev);
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hdmirx_interrupts_setup(hdmirx_dev, true);
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hdmirx_audio_handle_plugged_change(hdmirx_dev, 1);
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if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp_start)
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hdmirx_dev->hdcp->hdcp_start(hdmirx_dev->hdcp);
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} else {
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hdmirx_audio_handle_plugged_change(hdmirx_dev, 0);
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hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED, 0);
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hdmirx_interrupts_setup(hdmirx_dev, false);
|
||||
hdmirx_hpd_ctrl(hdmirx_dev, false);
|
||||
hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6, HDMIRX_DMA_EN, 0);
|
||||
hdmirx_update_bits(hdmirx_dev, DMA_CONFIG4,
|
||||
LINE_FLAG_INT_EN |
|
||||
HDMIRX_DMA_IDLE_INT |
|
||||
HDMIRX_LOCK_DISABLE_INT |
|
||||
LAST_FRAME_AXI_UNFINISH_INT_EN |
|
||||
FIFO_OVERFLOW_INT_EN |
|
||||
FIFO_UNDERFLOW_INT_EN |
|
||||
HDMIRX_AXI_ERROR_INT_EN, 0);
|
||||
hdmirx_reset_dma(hdmirx_dev);
|
||||
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
|
||||
HDMI_DISABLE | PHY_RESET | PHY_PDDQ,
|
||||
HDMI_DISABLE);
|
||||
hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x0);
|
||||
cancel_delayed_work(&hdmirx_dev->delayed_work_res_change);
|
||||
cancel_delayed_work(&hdmirx_dev->delayed_work_audio);
|
||||
cpu_latency_qos_update_request(&hdmirx_dev->pm_qos, PM_QOS_DEFAULT_VALUE);
|
||||
hdmirx_cancel_cpu_limit_freq(hdmirx_dev);
|
||||
cancel_delayed_work(&hdmirx_dev->delayed_work_heartbeat);
|
||||
flush_work(&hdmirx_dev->work_wdt_config);
|
||||
sip_wdt_config(WDT_STOP, 0, 0, 0);
|
||||
}
|
||||
if (plugin)
|
||||
hdmirx_plugin(hdmirx_dev);
|
||||
else
|
||||
hdmirx_plugout(hdmirx_dev);
|
||||
|
||||
mutex_unlock(&hdmirx_dev->work_lock);
|
||||
}
|
||||
|
||||
@@ -2886,7 +2945,10 @@ static void hdmirx_edid_init_config(struct rk_hdmirx_dev *hdmirx_dev)
|
||||
def_edid.pad = 0;
|
||||
def_edid.start_block = 0;
|
||||
def_edid.blocks = EDID_NUM_BLOCKS_MAX;
|
||||
def_edid.edid = edid_init_data;
|
||||
if (hdmirx_dev->edid_version == HDMIRX_EDID_600M)
|
||||
def_edid.edid = edid_init_data_600M;
|
||||
else
|
||||
def_edid.edid = edid_init_data_340M;
|
||||
ret = hdmirx_write_edid(hdmirx_dev, &def_edid, false);
|
||||
if (ret)
|
||||
dev_err(hdmirx_dev->dev, "%s write edid failed!\n", __func__);
|
||||
@@ -2989,12 +3051,63 @@ static ssize_t audio_present_show(struct device *dev,
|
||||
tx_5v_power_present(hdmirx_dev) ? hdmirx_dev->audio_present : 0);
|
||||
}
|
||||
|
||||
static ssize_t edid_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
|
||||
int edid = 0;
|
||||
|
||||
if (hdmirx_dev)
|
||||
edid = hdmirx_dev->edid_version;
|
||||
|
||||
return snprintf(buf, PAGE_SIZE, "%d\n", edid);
|
||||
}
|
||||
|
||||
static ssize_t edid_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
int edid;
|
||||
struct rk_hdmirx_dev *hdmirx_dev = dev_get_drvdata(dev);
|
||||
|
||||
if (!hdmirx_dev)
|
||||
return -EINVAL;
|
||||
|
||||
if (kstrtoint(buf, 10, &edid))
|
||||
return -EINVAL;
|
||||
|
||||
if (edid != HDMIRX_EDID_340M && edid != HDMIRX_EDID_600M)
|
||||
return count;
|
||||
|
||||
if (hdmirx_dev->edid_version != edid) {
|
||||
disable_irq(hdmirx_dev->hdmi_irq);
|
||||
disable_irq(hdmirx_dev->dma_irq);
|
||||
sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_DIS, RK_IRQ_HDMIRX_HDMI, 0);
|
||||
|
||||
if (tx_5v_power_present(hdmirx_dev))
|
||||
hdmirx_plugout(hdmirx_dev);
|
||||
hdmirx_dev->edid_version = edid;
|
||||
hdmirx_edid_init_config(hdmirx_dev);
|
||||
|
||||
enable_irq(hdmirx_dev->hdmi_irq);
|
||||
enable_irq(hdmirx_dev->dma_irq);
|
||||
sip_fiq_control(RK_SIP_FIQ_CTRL_FIQ_EN, RK_IRQ_HDMIRX_HDMI, 0);
|
||||
schedule_delayed_work_on(hdmirx_dev->bound_cpu,
|
||||
&hdmirx_dev->delayed_work_hotplug,
|
||||
msecs_to_jiffies(200));
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR_RO(audio_rate);
|
||||
static DEVICE_ATTR_RO(audio_present);
|
||||
static DEVICE_ATTR_RW(edid);
|
||||
|
||||
static struct attribute *hdmirx_attrs[] = {
|
||||
&dev_attr_audio_rate.attr,
|
||||
&dev_attr_audio_present.attr,
|
||||
&dev_attr_edid.attr,
|
||||
NULL
|
||||
};
|
||||
ATTRIBUTE_GROUPS(hdmirx);
|
||||
@@ -3458,6 +3571,7 @@ static int hdmirx_probe(struct platform_device *pdev)
|
||||
hdmirx_dev->dev = dev;
|
||||
hdmirx_dev->of_node = dev->of_node;
|
||||
hdmirx_dev->cpu_freq_khz = CPU_LIMIT_FREQ_KHZ;
|
||||
hdmirx_dev->edid_version = HDMIRX_EDID_340M;
|
||||
ret = hdmirx_parse_dt(hdmirx_dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -3632,7 +3746,7 @@ static int hdmirx_probe(struct platform_device *pdev)
|
||||
cec_data.dev = hdmirx_dev->dev;
|
||||
cec_data.ops = &hdmirx_cec_ops;
|
||||
cec_data.irq = irq;
|
||||
cec_data.edid = edid_init_data;
|
||||
cec_data.edid = edid_init_data_340M;
|
||||
hdmirx_dev->cec = rk_hdmirx_cec_register(&cec_data);
|
||||
hdmirx_register_hdcp(dev, hdmirx_dev, hdmirx_dev->hdcp1x_enable);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user