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media: rockchip: isp: add isp39

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Change-Id: I5711f268db07523ef3cf2541dacbb9016760d6c3
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2023-12-01 14:32:19 +08:00
committed by Tao Huang
parent b06eecc828
commit 4d27e391e5
36 changed files with 10942 additions and 167 deletions
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4
drivers/media/platform/rockchip/isp/Kconfig
View File

@@ -35,6 +35,10 @@ config VIDEO_ROCKCHIP_ISP_VERSION_V32
bool "isp32 for rv1106 rk3562"
default y if CPU_RV1106 || CPU_RK3562
config VIDEO_ROCKCHIP_ISP_VERSION_V39
bool "isp39 for rk3576"
default y if CPU_RK3576
config VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
bool "Rockchip Image Signal Processing Thunderboot helper"
depends on ROCKCHIP_THUNDER_BOOT

7
drivers/media/platform/rockchip/isp/Makefile
View File

@@ -44,6 +44,13 @@ video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) += \
isp_stats_v32.o \
isp_rockit.o
video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39) += \
capture_v39.o \
isp_params_v39.o \
isp_stats_v39.o \
isp_pdaf.o \
isp_sditf.o
video_rkisp-$(CONFIG_ROCKCHIP_DVBM) += \
isp_dvbm.o

31
drivers/media/platform/rockchip/isp/capture.c
View File

@@ -435,6 +435,9 @@ int rkisp_stream_frame_start(struct rkisp_device *dev, u32 isp_mis)
rkisp_dvbm_event(dev, CIF_ISP_V_START);
rkisp_bridge_update_mi(dev, isp_mis);
if (dev->isp_ver == ISP_V39)
rkisp_sditf_sof(dev, isp_mis);
for (i = 0; i < RKISP_MAX_STREAM; i++) {
if (i == RKISP_STREAM_VIR || i == RKISP_STREAM_LUMA)
continue;
@@ -618,6 +621,7 @@ static void restrict_rsz_resolution(struct rkisp_stream *stream,
struct v4l2_rect *input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
if (stream->id == RKISP_STREAM_VIR ||
stream->id == RKISP_STREAM_LDC ||
(dev->isp_ver == ISP_V30 && stream->id == RKISP_STREAM_BP)) {
max_rsz->width = input_win->width;
max_rsz->height = input_win->height;
@@ -691,6 +695,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
} else if (pixm->width != max_rsz.width &&
pixm->height != max_rsz.height &&
(stream->id == RKISP_STREAM_LUMA ||
stream->id == RKISP_STREAM_LDC ||
(dev->isp_ver == ISP_V30 &&
(stream->id == RKISP_STREAM_BP || stream->id == RKISP_STREAM_FBC)))) {
v4l2_warn(&dev->v4l2_dev,
@@ -760,6 +765,8 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
ALIGN(pixm->width, 16) : pixm->width;
h = (fmt->fmt_type == FMT_FBC) ?
ALIGN(pixm->height, 16) : pixm->height;
if (stream->id == RKISP_STREAM_LDC)
w = ALIGN(pixm->width, 32);
/* mainpath for warp default */
if (dev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP)
h = dev->cap_dev.wrap_line;
@@ -1494,7 +1501,8 @@ static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream,
stream->id == RKISP_STREAM_DMATX2 ||
stream->id == RKISP_STREAM_DMATX3 ||
stream->id == RKISP_STREAM_MPDS ||
stream->id == RKISP_STREAM_BPDS) {
stream->id == RKISP_STREAM_BPDS ||
stream->id == RKISP_STREAM_LDC) {
sel->left = 0;
sel->top = 0;
sel->width = in->width;
@@ -1785,16 +1793,13 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev)
CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
ret = rkisp_register_stream_v32(dev);
} else if (dev->isp_ver == ISP_V32_L) {
st_cfg->max_rsz_width = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_L_UNITE : CIF_ISP_INPUT_W_MAX_V32_L;
st_cfg->max_rsz_height = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
st_cfg = &rkisp_sp_stream_config;
st_cfg->max_rsz_width = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_L_UNITE : CIF_ISP_INPUT_W_MAX_V32_L;
st_cfg->max_rsz_height = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
ret = rkisp_register_stream_v32(dev);
} else if (dev->isp_ver == ISP_V39) {
ret = rkisp_register_stream_v39(dev);
}
INIT_WORK(&cap_dev->fast_work, rkisp_stream_fast);
@@ -1813,6 +1818,8 @@ void rkisp_unregister_stream_vdevs(struct rkisp_device *dev)
rkisp_unregister_stream_v30(dev);
else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L)
rkisp_unregister_stream_v32(dev);
else if (dev->isp_ver == ISP_V39)
rkisp_unregister_stream_v39(dev);
}
void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev)
@@ -1827,4 +1834,16 @@ void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev)
rkisp_mi_v30_isr(mis_val, dev);
else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L)
rkisp_mi_v32_isr(mis_val, dev);
else if (dev->isp_ver == ISP_V39)
rkisp_mi_v39_isr(mis_val, dev);
}
void rkisp_mipi_v3x_isr(unsigned int phy, unsigned int packet,
unsigned int overflow, unsigned int state,
struct rkisp_device *dev)
{
if (state & GENMASK(19, 17))
v4l2_warn(&dev->v4l2_dev, "RD_SIZE_ERR:0x%08x\n", state);
if (state & ISP21_MIPI_DROP_FRM)
v4l2_warn(&dev->v4l2_dev, "MIPI drop frame\n");
}

12
drivers/media/platform/rockchip/isp/capture.h
View File

@@ -51,6 +51,7 @@
#define BPDS_VDEV_NAME DRIVER_NAME "_bypasspath_4x4sampling"
#define LUMA_VDEV_NAME DRIVER_NAME "_lumapath"
#define VIR_VDEV_NAME DRIVER_NAME "_iqtool"
#define LDC_VDEV_NAME DRIVER_NAME "_ldcpath"
#define DMATX0_VDEV_NAME DRIVER_NAME "_rawwr0"
#define DMATX1_VDEV_NAME DRIVER_NAME "_rawwr1"
@@ -91,6 +92,7 @@ enum {
RKISP_STREAM_MPDS,
RKISP_STREAM_BPDS,
RKISP_STREAM_LUMA,
RKISP_STREAM_LDC,
RKISP_STREAM_VIR,
RKISP_MAX_STREAM,
};
@@ -166,6 +168,16 @@ struct stream_config {
struct {
u32 ctrl;
u32 ctrl_shd;
u32 update;
u32 src_size;
u32 dst_size;
u32 scale_hy_offs_mi;
u32 scale_hc_offs_mi;
u32 scale_in_crop_offs;
u32 scale_hy_offs;
u32 scale_hc_offs;
u32 scale_hy_size;
u32 scale_hc_size;
u32 scale_hy;
u32 scale_hcr;
u32 scale_hcb;

10
drivers/media/platform/rockchip/isp/capture_v30.c
View File

@@ -1769,13 +1769,3 @@ void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev)
rkisp_check_idle(dev, ISP_FRAME_BP);
}
}
void rkisp_mipi_v30_isr(unsigned int phy, unsigned int packet,
unsigned int overflow, unsigned int state,
struct rkisp_device *dev)
{
if (state & GENMASK(19, 17))
v4l2_warn(&dev->v4l2_dev, "RD_SIZE_ERR:0x%08x\n", state);
if (state & ISP21_MIPI_DROP_FRM)
v4l2_warn(&dev->v4l2_dev, "MIPI drop frame\n");
}

79
drivers/media/platform/rockchip/isp/capture_v32.c
View File

@@ -348,6 +348,68 @@ static const struct capture_fmt luma_fmts[] = {
},
};
static struct stream_config rkisp_sp_stream_config_lite = {
/* constraints */
.max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L,
.max_rsz_height = CIF_ISP_INPUT_H_MAX_V32_L,
.min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
.min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
.frame_end_id = CIF_MI_SP_FRAME,
/* registers */
.rsz = {
.ctrl = ISP32_SELF_SCALE_CTRL,
.update = ISP32_SELF_SCALE_UPDATE,
.src_size = ISP32_SELF_SCALE_SRC_SIZE,
.dst_size = ISP32_SELF_SCALE_DST_SIZE,
.scale_hy_offs_mi = ISP32_SELF_SCALE_HY_OFFS_MI,
.scale_hc_offs_mi = ISP32_SELF_SCALE_HC_OFFS_MI,
.scale_in_crop_offs = ISP32_SELF_SCALE_IN_CROP_OFFSET,
.scale_hy_offs = ISP32_SELF_SCALE_HY_OFFS,
.scale_hc_offs = ISP32_SELF_SCALE_HC_OFFS,
.scale_hy_size = ISP32_SELF_SCALE_HY_SIZE,
.scale_hc_size = ISP32_SELF_SCALE_HC_SIZE,
.scale_hy = ISP32_SELF_SCALE_HY_FAC,
.scale_hcr = ISP32_SELF_SCALE_HC_FAC,
.scale_vy = ISP32_SELF_SCALE_VY_FAC,
.scale_vc = ISP32_SELF_SCALE_VC_FAC,
.scale_hy_shd = ISP32_SELF_SCALE_HY_FAC_SHD,
.scale_hcr_shd = ISP32_SELF_SCALE_HC_FAC_SHD,
.scale_vy_shd = ISP32_SELF_SCALE_VY_FAC_SHD,
.scale_vc_shd = ISP32_SELF_SCALE_VC_FAC_SHD,
.phase_hy = ISP32_SELF_SCALE_PHASE_HY,
.phase_hc = ISP32_SELF_SCALE_PHASE_HC,
.phase_vy = ISP32_SELF_SCALE_PHASE_VY,
.phase_vc = ISP32_SELF_SCALE_PHASE_VC,
.ctrl_shd = ISP32_SELF_SCALE_CTRL_SHD,
.phase_hy_shd = ISP32_SELF_SCALE_PHASE_HY_SHD,
.phase_hc_shd = ISP32_SELF_SCALE_PHASE_HC_SHD,
.phase_vy_shd = ISP32_SELF_SCALE_PHASE_VY_SHD,
.phase_vc_shd = ISP32_SELF_SCALE_PHASE_VC_SHD,
},
.dual_crop = {
.ctrl = CIF_DUAL_CROP_CTRL,
.yuvmode_mask = CIF_DUAL_CROP_SP_MODE_YUV,
.rawmode_mask = CIF_DUAL_CROP_SP_MODE_RAW,
.h_offset = CIF_DUAL_CROP_S_H_OFFS,
.v_offset = CIF_DUAL_CROP_S_V_OFFS,
.h_size = CIF_DUAL_CROP_S_H_SIZE,
.v_size = CIF_DUAL_CROP_S_V_SIZE,
},
.mi = {
.y_size_init = CIF_MI_SP_Y_SIZE_INIT,
.cb_size_init = CIF_MI_SP_CB_SIZE_INIT,
.cr_size_init = CIF_MI_SP_CR_SIZE_INIT,
.y_base_ad_init = CIF_MI_SP_Y_BASE_AD_INIT,
.cb_base_ad_init = CIF_MI_SP_CB_BASE_AD_INIT,
.cr_base_ad_init = CIF_MI_SP_CR_BASE_AD_INIT,
.y_offs_cnt_init = CIF_MI_SP_Y_OFFS_CNT_INIT,
.cb_offs_cnt_init = CIF_MI_SP_CB_OFFS_CNT_INIT,
.cr_offs_cnt_init = CIF_MI_SP_CR_OFFS_CNT_INIT,
.y_base_ad_shd = CIF_MI_SP_Y_BASE_AD_SHD,
.y_pic_size = ISP3X_MI_SP_WR_Y_PIC_SIZE,
},
};
static struct stream_config rkisp_luma_stream_config = {
.fmts = luma_fmts,
.fmt_size = ARRAY_SIZE(luma_fmts),
@@ -2193,13 +2255,18 @@ static int rkisp_stream_init(struct rkisp_device *dev, u32 id)
case RKISP_STREAM_SP:
strscpy(vdev->name, SP_VDEV_NAME, sizeof(vdev->name));
stream->ops = &rkisp_sp_streams_ops;
stream->config = &rkisp_sp_stream_config;
if (dev->isp_ver == ISP_V32) {
stream->config = &rkisp_sp_stream_config;
stream->config->fmts = sp_fmts;
stream->config->fmt_size = ARRAY_SIZE(sp_fmts);
} else {
stream->config = &rkisp_sp_stream_config_lite;
stream->config->fmts = sp_fmts_lite;
stream->config->fmt_size = ARRAY_SIZE(sp_fmts_lite);
if (dev->hw_dev->unite) {
stream->config->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L_UNITE;
stream->config->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32_L_UNITE;
}
}
break;
case RKISP_STREAM_BP:
@@ -2415,13 +2482,3 @@ end:
rkisp_check_idle(dev, ISP_FRAME_BP);
}
}
void rkisp_mipi_v32_isr(unsigned int phy, unsigned int packet,
unsigned int overflow, unsigned int state,
struct rkisp_device *dev)
{
if (state & GENMASK(19, 17))
v4l2_warn(&dev->v4l2_dev, "RD_SIZE_ERR:0x%08x\n", state);
if (state & ISP21_MIPI_DROP_FRM)
v4l2_warn(&dev->v4l2_dev, "MIPI drop frame\n");
}

1774
drivers/media/platform/rockchip/isp/capture_v39.c Normal file
View File

File diff suppressed because it is too large Load Diff

18
drivers/media/platform/rockchip/isp/capture_v3x.h
View File

@@ -8,23 +8,22 @@
#define RK_MPP_ALIGN 4096
//#define RKISP_STREAM_BP_EN 1
void rkisp_mipi_v3x_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev);
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30)
int rkisp_register_stream_v30(struct rkisp_device *dev);
void rkisp_unregister_stream_v30(struct rkisp_device *dev);
void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev);
void rkisp_mipi_v30_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev);
#else
static inline int rkisp_register_stream_v30(struct rkisp_device *dev) { return -EINVAL; }
static inline void rkisp_unregister_stream_v30(struct rkisp_device *dev) {}
static inline void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev) {}
static inline void rkisp_mipi_v30_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev) {}
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32)
int rkisp_register_stream_v32(struct rkisp_device *dev);
void rkisp_unregister_stream_v32(struct rkisp_device *dev);
void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev);
void rkisp_mipi_v32_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev);
void rkisp_rockit_buf_state_clear(struct rkisp_stream *stream);
int rkisp_rockit_buf_free(struct rkisp_stream *stream);
@@ -38,7 +37,6 @@ int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd);
static inline int rkisp_register_stream_v32(struct rkisp_device *dev) { return -EINVAL; }
static inline void rkisp_unregister_stream_v32(struct rkisp_device *dev) {}
static inline void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev) {}
static inline void rkisp_mipi_v32_isr(u32 phy, u32 packet, u32 overflow, u32 state, struct rkisp_device *dev) {}
static inline void rkisp_rockit_buf_state_clear(struct rkisp_stream *stream) { return; }
static inline int rkisp_rockit_buf_free(struct rkisp_stream *stream) { return -EINVAL; }
@@ -50,6 +48,18 @@ static inline int rkisp_rockit_fps_get(int *dst_fps, struct rkisp_stream *stream
static inline int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd) { return -EINVAL; }
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
int rkisp_register_stream_v39(struct rkisp_device *dev);
void rkisp_unregister_stream_v39(struct rkisp_device *dev);
void rkisp_mi_v39_isr(u32 mis_val, struct rkisp_device *dev);
void rkisp_stream_ldc_end_v39(struct rkisp_device *dev);
#else
static inline int rkisp_register_stream_v39(struct rkisp_device *dev) { return -EINVAL; }
static inline void rkisp_unregister_stream_v39(struct rkisp_device *dev) {}
static inline void rkisp_mi_v39_isr(u32 mis_val, struct rkisp_device *dev) {}
static inline void rkisp_stream_ldc_end_v39(struct rkisp_device *dev) {}
#endif
#if IS_ENABLED(CONFIG_ROCKCHIP_DVBM)
int rkisp_dvbm_get(struct rkisp_device *dev);
int rkisp_dvbm_init(struct rkisp_stream *stream);

2
drivers/media/platform/rockchip/isp/common.h
View File

@@ -75,6 +75,8 @@ enum rkisp_isp_ver {
ISP_V30 = 0x60,
ISP_V32 = 0x70,
ISP_V32_L = 0x80,
ISP_V33 = 0x90,
ISP_V39 = 0xa0,
};
enum rkisp_sd_type {

108
drivers/media/platform/rockchip/isp/csi.c
View File

@@ -416,12 +416,13 @@ int rkisp_expander_config(struct rkisp_device *dev,
{
struct rkmodule_hdr_cfg hdr_cfg;
u32 i, val, num, d0, d1, drop_bit = 0;
u32 output_bit, input_bit, max;
if (dev->isp_ver != ISP_V32)
if (dev->isp_ver != ISP_V39)
return 0;
if (!on) {
rkisp_write(dev, ISP32_EXPD_CTRL, 0, false);
rkisp_write(dev, ISP39_EXPD_CTRL, 0, false);
return 0;
}
@@ -434,72 +435,57 @@ int rkisp_expander_config(struct rkisp_device *dev,
if (cfg->hdr_mode != HDR_COMPR)
return 0;
/* compressed data max 12bit and src data max 20bit */
if (cfg->compr.bit > 20)
drop_bit = cfg->compr.bit - 20;
dev->hdr.compr_bit = cfg->compr.bit - drop_bit;
/* input data (12bit or 16bit) and output data max 20bit */
if (cfg->compr.src_bit > 20)
drop_bit = cfg->compr.src_bit - 20;
output_bit = cfg->compr.src_bit - drop_bit;
dev->hdr.src_bit = output_bit;
input_bit = dev->isp_sdev.in_fmt.bus_width;
num = cfg->compr.segment;
for (i = 0; i < num; i++) {
val = cfg->compr.slope_k[i];
rkisp_write(dev, ISP32_EXPD_K0 + i * 4, val, false);
}
num = cfg->compr.point;
if (num > HDR_COMPR_POINT_MAX)
num = HDR_COMPR_POINT_MAX;
max = (1 << output_bit) - 1;
for (i = 0; i < HDR_COMPR_POINT_MAX; i++) {
if (i < num)
val = cfg->compr.slope_k[i];
else
val = 0;
d0 = 0;
d1 = cfg->compr.data_compr[0];
val = ISP32_EXPD_DATA(d0, d1 > 0xfff ? 0xfff : d1);
rkisp_write(dev, ISP32_EXPD_X00_01, val, false);
if (i < 15)
rkisp_write(dev, ISP39_EXPD_K0 + i * 4, val, false);
else
rkisp_write(dev, ISP39_EXPD_K15 + (i - 15) * 4, val, false);
d1 = cfg->compr.data_src_shitf[0];
val = ISP32_EXPD_DATA(d0, drop_bit ? d1 >> drop_bit : d1);
rkisp_write(dev, ISP32_EXPD_Y00_01, val, false);
for (i = 1; i < num - 1; i += 2) {
d0 = cfg->compr.data_compr[i];
d1 = cfg->compr.data_compr[i + 1];
val = ISP32_EXPD_DATA(d0 > 0xfff ? 0xfff : d0,
d1 > 0xfff ? 0xfff : d1);
rkisp_write(dev, ISP32_EXPD_X00_01 + (i + 1) * 2, val, false);
d0 = cfg->compr.data_src_shitf[i];
d1 = cfg->compr.data_src_shitf[i + 1];
if (drop_bit) {
d0 = d0 >> drop_bit;
d1 = d1 >> drop_bit;
if (i < num) {
d0 = cfg->compr.data_src[i];
val = d0 > max ? max : d0;
} else {
val = max;
}
rkisp_write(dev, ISP39_EXPD_Y0 + i * 4, val, false);
}
max = input_bit > 12 ? 0xffff : 0xfff;
for (i = 0; i < HDR_COMPR_POINT_MAX / 2; i++) {
d0 = cfg->compr.data_compr[i * 2];
d1 = cfg->compr.data_compr[i * 2 + 1];
if (d0 > max || i * 2 >= num)
d0 = max;
if (d1 > max || i * 2 + 1 >= num)
d1 = max;
val = ISP32_EXPD_DATA(d0, d1);
rkisp_write(dev, ISP32_EXPD_Y00_01 + (i + 1) * 2, val, false);
rkisp_write(dev, ISP39_EXPD_X00_01 + i * 4, val, false);
}
/* the last valid point */
val = cfg->compr.data_compr[i];
val = val > 0xfff ? 0xfff : val;
d0 = ISP32_EXPD_DATA(val, val);
val = input_bit > 12 ? 0xffff : 0xfff;
rkisp_write(dev, ISP39_EXPD_IMAX, val, false);
val = (1 << output_bit) - 1;
rkisp_write(dev, ISP39_EXPD_OMAX, val, false);
val = cfg->compr.data_src_shitf[i];
val = drop_bit ? val >> drop_bit : val;
d1 = ISP32_EXPD_DATA(val, val);
num = HDR_COMPR_SEGMENT_16;
for (; i < num - 1; i += 2) {
rkisp_write(dev, ISP32_EXPD_X00_01 + (i + 1) * 2, d0, false);
rkisp_write(dev, ISP32_EXPD_Y00_01 + (i + 1) * 2, d1, false);
}
rkisp_write(dev, ISP32_EXPD_Y16, val, false);
switch (cfg->compr.segment) {
case HDR_COMPR_SEGMENT_12:
num = 1;
break;
case HDR_COMPR_SEGMENT_16:
num = 2;
break;
default:
num = 0;
}
val = ISP32_EXPD_EN |
ISP32_EXPD_MODE(num) |
ISP32_EXPD_K_SHIFT(cfg->compr.k_shift);
val = ISP32_EXPD_EN | ISP32_EXPD_K_SHIFT(cfg->compr.k_shift);
if (input_bit == 16)
val |= ISP39_EXPD_INPUT_16;
rkisp_write(dev, ISP32_EXPD_CTRL, val, false);
return 0;
err:
@@ -647,7 +633,7 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
if (dev->isp_ver >= ISP_V30)
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, true);
/* line counter from isp out, default from mp out */
if (dev->isp_ver == ISP_V32_L)
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP32L_ISP2ENC_CNT_MUX, true);
dev->rdbk_cnt = -1;
dev->rdbk_cnt_x1 = -1;

15
drivers/media/platform/rockchip/isp/dev.c
View File

@@ -545,7 +545,9 @@ static int _set_pipeline_default_fmt(struct rkisp_device *dev, bool is_init)
#endif
}
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L) {
if (dev->isp_ver == ISP_V32 ||
dev->isp_ver == ISP_V32_L ||
dev->isp_ver == ISP_V39) {
struct v4l2_pix_format_mplane pixm = {
.width = width,
.height = height,
@@ -563,6 +565,8 @@ static int _set_pipeline_default_fmt(struct rkisp_device *dev, bool is_init)
width / 4, height / 4, V4L2_PIX_FMT_NV12);
}
}
if (dev->isp_ver == ISP_V39)
rkisp_set_stream_def_fmt(dev, RKISP_STREAM_LDC, width, height, V4L2_PIX_FMT_NV12);
return 0;
}
@@ -730,14 +734,20 @@ static int rkisp_register_platform_subdevs(struct rkisp_device *dev)
if (ret < 0)
goto err_unreg_params_vdev;
ret = rkisp_register_pdaf_vdev(dev);
if (ret < 0)
goto err_unreg_luma_vdev;
ret = isp_subdev_notifier(dev);
if (ret < 0) {
v4l2_err(&dev->v4l2_dev,
"Failed to register subdev notifier(%d)\n", ret);
goto err_unreg_luma_vdev;
goto err_unreg_pdaf_vdev;
}
return 0;
err_unreg_pdaf_vdev:
rkisp_unregister_pdaf_vdev(dev);
err_unreg_luma_vdev:
rkisp_unregister_luma_vdev(&dev->luma_vdev);
err_unreg_params_vdev:
@@ -972,6 +982,7 @@ static int rkisp_plat_remove(struct platform_device *pdev)
v4l2_async_nf_cleanup(&isp_dev->notifier);
v4l2_device_unregister(&isp_dev->v4l2_dev);
v4l2_ctrl_handler_free(&isp_dev->ctrl_handler);
rkisp_unregister_pdaf_vdev(isp_dev);
rkisp_unregister_luma_vdev(&isp_dev->luma_vdev);
rkisp_unregister_params_vdev(&isp_dev->params_vdev);
rkisp_unregister_stats_vdev(&isp_dev->stats_vdev);

22
drivers/media/platform/rockchip/isp/dev.h
View File

@@ -1,5 +1,5 @@
/*
* Rockchip isp1 driver
* Rockchip isp driver
*
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
*
@@ -46,6 +46,8 @@
#include "isp_mipi_luma.h"
#include "procfs.h"
#include "isp_external.h"
#include "isp_pdaf.h"
#include "isp_sditf.h"
#include "version.h"
#define DRIVER_NAME "rkisp"
@@ -76,12 +78,14 @@ enum rkisp_isp_state {
ISP_FRAME_SP = BIT(4),
ISP_FRAME_MPFBC = BIT(5),
ISP_FRAME_BP = BIT(6),
ISP_FRAME_LDC = BIT(7),
ISP_FRAME_VPSS = BIT(8),
ISP_STOP = BIT(8),
ISP_START = BIT(9),
ISP_ERROR = BIT(10),
ISP_MIPI_ERROR = BIT(11),
ISP_CIF_RESET = BIT(12),
ISP_STOP = BIT(16),
ISP_START = BIT(17),
ISP_ERROR = BIT(18),
ISP_MIPI_ERROR = BIT(19),
ISP_CIF_RESET = BIT(20),
};
enum rkisp_isp_inp {
@@ -170,6 +174,7 @@ struct rkisp_sensor_info {
/* struct rkisp_hdr - hdr configured
* @op_mode: hdr optional mode
* @esp_mode: hdr especial mode
* @src_bit: src bit of expander mode
* @index: hdr dma index
* @refcnt: open counter
* @q_tx: dmatx buf list
@@ -180,7 +185,7 @@ struct rkisp_sensor_info {
struct rkisp_hdr {
u8 op_mode;
u8 esp_mode;
u8 compr_bit;
u8 src_bit;
u8 index[HDR_DMA_MAX];
atomic_t refcnt;
struct v4l2_subdev *sensor;
@@ -224,6 +229,7 @@ struct rkisp_device {
struct rkisp_csi_device csi_dev;
struct rkisp_bridge_device br_dev;
struct rkisp_luma_vdev luma_vdev;
struct rkisp_pdaf_vdev pdaf_vdev;
struct rkisp_procfs procfs;
struct rkisp_pipeline pipe;
enum rkisp_isp_ver isp_ver;
@@ -242,6 +248,8 @@ struct rkisp_device {
struct mutex iqlock; /* mutex to serialize the calls of iq */
wait_queue_head_t sync_onoff;
struct rkisp_sditf_device *sditf_dev;
dma_addr_t resmem_addr;
phys_addr_t resmem_pa;
size_t resmem_size;

33
drivers/media/platform/rockchip/isp/dmarx.c
View File

@@ -196,6 +196,31 @@ static const struct capture_fmt rawrd_fmts[] = {
.fmt_type = FMT_YUV,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB16,
.fmt_type = FMT_BAYER,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG16,
.fmt_type = FMT_BAYER,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG16,
.fmt_type = FMT_BAYER,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR16,
.fmt_type = FMT_BAYER,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4L2_PIX_FMT_Y16,
.fmt_type = FMT_BAYER,
.bpp = { 16 },
.mplanes = 1,
}
};
@@ -342,6 +367,13 @@ static int rawrd_config_mi(struct rkisp_stream *stream)
case V4L2_PIX_FMT_VYUY:
val |= CIF_CSI2_DT_YUV422_8b;
break;
case V4L2_PIX_FMT_SRGGB16:
case V4L2_PIX_FMT_SBGGR16:
case V4L2_PIX_FMT_SGRBG16:
case V4L2_PIX_FMT_SGBRG16:
case V4L2_PIX_FMT_Y16:
val |= CIF_CSI2_DT_RAW16;
break;
default:
val |= CIF_CSI2_DT_RAW12;
}
@@ -798,6 +830,7 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
if (stream->ispdev->isp_ver >= ISP_V20 &&
fmt->fmt_type == FMT_BAYER &&
fmt->bpp[0] != 16 &&
!stream->memory &&
stream->id != RKISP_STREAM_DMARX)
bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256);

36
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -111,6 +111,23 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
};
u32 v39_reg[] = {
ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
ISP3X_GAMMA_OUT_CTRL, ISP39_MAIN_SCALE_CTRL, ISP32_SELF_SCALE_CTRL,
ISP39_LDCV_CTRL, ISP39_YUVME_CTRL, ISP39_RGBIR_CTRL,
ISP39_EXPD_CTRL, ISP39_W3A_CTRL0, ISP39_W3A_CTRL1,
ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
};
u32 i, j, *flag, *reg, size;
switch (dev->isp_ver) {
@@ -131,6 +148,10 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
reg = v32_reg;
size = ARRAY_SIZE(v32_reg);
break;
case ISP_V39:
reg = v39_reg;
size = ARRAY_SIZE(v39_reg);
break;
default:
return;
}
@@ -182,10 +203,8 @@ static irqreturn_t mipi_irq_hdl(int irq, void *ctx)
rkisp_mipi_v20_isr(phy, packet, overflow, state, isp);
else if (hw_dev->isp_ver == ISP_V21)
rkisp_mipi_v21_isr(phy, packet, overflow, state, isp);
else if (hw_dev->isp_ver == ISP_V30)
rkisp_mipi_v30_isr(phy, packet, overflow, state, isp);
else
rkisp_mipi_v32_isr(phy, packet, overflow, state, isp);
rkisp_mipi_v3x_isr(phy, packet, overflow, state, isp);
}
} else {
u32 mis_val = readl(base + CIF_MIPI_MIS);
@@ -889,6 +908,11 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
writel(0x37, dev->base_addr + ISP32_MI_WR_WRAP_CTRL);
} else if (dev->isp_ver == ISP_V32_L) {
writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
} else if (dev->isp_ver == ISP_V39) {
writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
writel(ISP39_ADRC_CMPS_BYP_EN, dev->base_addr + ISP3X_DRC_CTRL0);
writel(ISP39_W3A_PDAF2DDR_HOLD_DIS | ISP39_W3A_3A_HOLD_DIS,
dev->base_addr + ISP39_W3A_CTRL0);
}
}
@@ -1362,6 +1386,9 @@ static int __init rkisp_hw_drv_init(void)
ret = platform_driver_register(&rkisp_hw_drv);
if (!ret)
ret = platform_driver_register(&rkisp_plat_drv);
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
platform_driver_register(&rkisp_sditf_drv);
#endif
#if IS_BUILTIN(CONFIG_VIDEO_ROCKCHIP_ISP) && IS_BUILTIN(CONFIG_VIDEO_ROCKCHIP_ISPP)
if (!ret)
ret = rkispp_hw_drv_init();
@@ -1371,6 +1398,9 @@ static int __init rkisp_hw_drv_init(void)
static void __exit rkisp_hw_drv_exit(void)
{
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
platform_driver_unregister(&rkisp_sditf_drv);
#endif
platform_driver_unregister(&rkisp_plat_drv);
platform_driver_unregister(&rkisp_hw_drv);
}

4
drivers/media/platform/rockchip/isp/isp_ispp.h
View File

@@ -40,6 +40,10 @@ enum rkisp_ispp_dev {
DEV_ID1,
DEV_ID2,
DEV_ID3,
DEV_ID4,
DEV_ID5,
DEV_ID6,
DEV_ID7,
DEV_MAX,
};

39
drivers/media/platform/rockchip/isp/isp_params.c
View File

@@ -14,6 +14,7 @@
#include "isp_params_v21.h"
#include "isp_params_v3x.h"
#include "isp_params_v32.h"
#include "isp_params_v39.h"
#include "regs.h"
#define PARAMS_NAME DRIVER_NAME "-input-params"
@@ -92,6 +93,23 @@ static int rkisp_params_unsubs_evt(struct v4l2_fh *fh,
return v4l2_event_unsubscribe(fh, sub);
}
static long rkisp_params_ioctl_default(struct file *file, void *fh,
bool valid_prio, unsigned int cmd, void *arg)
{
struct rkisp_isp_params_vdev *params = video_drvdata(file);
long ret = 0;
switch (cmd) {
case RKISP_CMD_SET_EXPANDER:
rkisp_expander_config(params->dev, arg, true);
break;
default:
ret = -EINVAL;
}
return ret;
}
/* ISP params video device IOCTLs */
static const struct v4l2_ioctl_ops rkisp_params_ioctl = {
.vidioc_reqbufs = vb2_ioctl_reqbufs,
@@ -110,6 +128,7 @@ static const struct v4l2_ioctl_ops rkisp_params_ioctl = {
.vidioc_querycap = rkisp_params_querycap,
.vidioc_subscribe_event = rkisp_params_subs_evt,
.vidioc_unsubscribe_event = rkisp_params_unsubs_evt,
.vidioc_default = rkisp_params_ioctl_default,
};
static int rkisp_params_vb2_queue_setup(struct vb2_queue *vq,
@@ -215,6 +234,8 @@ static void rkisp_params_vb2_stop_streaming(struct vb2_queue *vq)
struct rkisp_buffer *buf;
unsigned long flags;
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s state:0x%x\n", __func__, dev->isp_state);
/* stop params input firstly */
spin_lock_irqsave(&params_vdev->config_lock, flags);
params_vdev->streamon = false;
@@ -248,6 +269,8 @@ rkisp_params_vb2_start_streaming(struct vb2_queue *queue, unsigned int count)
struct rkisp_isp_params_vdev *params_vdev = queue->drv_priv;
unsigned long flags;
v4l2_dbg(1, rkisp_debug, &params_vdev->dev->v4l2_dev,
"%s cnt:%d\n", __func__, count);
params_vdev->hdrtmo_en = false;
params_vdev->afaemode_en = false;
params_vdev->cur_buf = NULL;
@@ -313,7 +336,10 @@ struct v4l2_file_operations rkisp_params_fops = {
.unlocked_ioctl = video_ioctl2,
.poll = rkisp_params_fop_poll,
.open = rkisp_params_fh_open,
.release = rkisp_params_fop_release
.release = rkisp_params_fop_release,
#ifdef CONFIG_COMPAT
.compat_ioctl32 = video_ioctl2,
#endif
};
static int
@@ -345,8 +371,11 @@ static int rkisp_init_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
ret = rkisp_init_params_vdev_v2x(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V30)
ret = rkisp_init_params_vdev_v3x(params_vdev);
else
else if (params_vdev->dev->isp_ver == ISP_V32 ||
params_vdev->dev->isp_ver == ISP_V32_L)
ret = rkisp_init_params_vdev_v32(params_vdev);
else
ret = rkisp_init_params_vdev_v39(params_vdev);
params_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_PARAMS;
return ret;
@@ -362,8 +391,11 @@ static void rkisp_uninit_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
rkisp_uninit_params_vdev_v2x(params_vdev);
else if (params_vdev->dev->isp_ver == ISP_V30)
rkisp_uninit_params_vdev_v3x(params_vdev);
else
else if (params_vdev->dev->isp_ver == ISP_V32 ||
params_vdev->dev->isp_ver == ISP_V32_L)
rkisp_uninit_params_vdev_v32(params_vdev);
else
rkisp_uninit_params_vdev_v39(params_vdev);
}
void rkisp_params_cfg(struct rkisp_isp_params_vdev *params_vdev, u32 frame_id)
@@ -563,4 +595,3 @@ void rkisp_unregister_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
vb2_queue_release(vdev->queue);
rkisp_uninit_params_vdev(params_vdev);
}

2
drivers/media/platform/rockchip/isp/isp_params.h
View File

@@ -8,6 +8,7 @@
#include <linux/rk-isp2-config.h>
#include <linux/rk-isp3-config.h>
#include <linux/rk-isp32-config.h>
#include <linux/rk-isp39-config.h>
#include <linux/rk-preisp.h>
#include "common.h"
@@ -64,6 +65,7 @@ struct rkisp_isp_params_vdev {
struct isp21_isp_params_cfg *isp21_params;
struct isp3x_isp_params_cfg *isp3x_params;
struct isp32_isp_params_cfg *isp32_params;
struct isp39_isp_params_cfg *isp39_params;
};
struct v4l2_format vdev_fmt;
bool streamon;

4903
drivers/media/platform/rockchip/isp/isp_params_v39.c Normal file
View File

File diff suppressed because it is too large Load Diff

177
drivers/media/platform/rockchip/isp/isp_params_v39.h Normal file
View File

@@ -0,0 +1,177 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_PARAM_V39_H
#define _RKISP_PARAM_V39_H
#include "common.h"
#include "isp_params.h"
#define ISP39_3DLUT_BUF_NUM 2
#define ISP39_3DLUT_BUF_SIZE (9 * 9 * 9 * 4)
#define ISP39_LSC_LUT_BUF_NUM 2
#define ISP39_LSC_LUT_TBL_SIZE (9 * 17 * 4)
#define ISP39_LSC_LUT_BUF_SIZE (ISP39_LSC_LUT_TBL_SIZE * 4)
#define ISP39_RAWHISTBIG_ROW_NUM 15
#define ISP39_RAWHISTBIG_COLUMN_NUM 15
#define ISP39_RAWHISTBIG_WEIGHT_REG_SIZE \
(ISP39_RAWHISTBIG_ROW_NUM * ISP39_RAWHISTBIG_COLUMN_NUM)
struct rkisp_isp_params_vdev;
struct rkisp_isp_params_ops_v39 {
void (*dpcc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_dpcc_cfg *arg);
void (*dpcc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*bls_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_bls_cfg *arg);
void (*bls_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*sdg_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_sdg_cfg *arg);
void (*sdg_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*lsc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_lsc_cfg *arg);
void (*lsc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*awbgain_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_awb_gain_cfg *arg);
void (*awbgain_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*debayer_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_debayer_cfg *arg);
void (*debayer_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*ccm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_ccm_cfg *arg);
void (*ccm_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*goc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_gammaout_cfg *arg);
void (*goc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*cproc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_cproc_cfg *arg);
void (*cproc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*rawaf_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_rawaf_meas_cfg *arg);
void (*rawaf_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*rawae0_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg);
void (*rawae0_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*rawae3_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg);
void (*rawae3_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*rawawb_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_rawawb_meas_cfg *arg);
void (*rawawb_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*rawhst0_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg);
void (*rawhst0_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*rawhst3_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg);
void (*rawhst3_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*hdrdrc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_drc_cfg *arg,
enum rkisp_params_type type);
void (*hdrdrc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*hdrmge_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_hdrmge_cfg *arg,
enum rkisp_params_type type);
void (*hdrmge_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*gic_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_gic_cfg *arg);
void (*gic_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*dhaz_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_dhaz_cfg *arg);
void (*dhaz_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*isp3dlut_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_3dlut_cfg *arg);
void (*isp3dlut_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*ldch_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_ldch_cfg *arg);
void (*ldch_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*ynr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_ynr_cfg *arg);
void (*ynr_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*cnr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_cnr_cfg *arg);
void (*cnr_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*sharp_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_sharp_cfg *arg);
void (*sharp_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*bay3d_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_bay3d_cfg *arg);
void (*bay3d_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*gain_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_gain_cfg *arg);
void (*gain_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*cac_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_cac_cfg *arg);
void (*cac_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*csm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_csm_cfg *arg);
void (*cgc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_cgc_cfg *arg);
void (*ie_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*yuvme_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_yuvme_cfg *arg);
void (*yuvme_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*ldcv_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_ldcv_cfg *arg);
void (*ldcv_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
void (*rgbir_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_rgbir_cfg *arg);
void (*rgbir_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
};
struct rkisp_isp_params_val_v39 {
struct tasklet_struct lsc_tasklet;
struct rkisp_dummy_buffer buf_3dlut[ISP39_3DLUT_BUF_NUM];
u32 buf_3dlut_idx;
struct rkisp_dummy_buffer buf_ldch[ISP39_MESH_BUF_NUM];
u32 buf_ldch_idx;
u32 ldch_out_hsize;
struct rkisp_dummy_buffer buf_ldcv[ISP39_MESH_BUF_NUM];
u32 buf_ldcv_idx;
u32 ldcv_out_vsize;
struct rkisp_dummy_buffer buf_cac[ISP39_MESH_BUF_NUM];
u32 buf_cac_idx;
struct rkisp_dummy_buffer buf_info[RKISP_INFO2DDR_BUF_MAX];
u32 buf_info_owner;
u32 buf_info_cnt;
int buf_info_idx;
struct rkisp_dummy_buffer buf_3dnr_iir;
struct rkisp_dummy_buffer buf_3dnr_cur;
struct rkisp_dummy_buffer buf_frm;
struct isp32_hdrmge_cfg last_hdrmge;
struct isp32_hdrmge_cfg cur_hdrmge;
struct isp39_drc_cfg last_hdrdrc;
struct isp39_drc_cfg cur_hdrdrc;
u32 dhaz_blk_num;
bool dhaz_en;
bool drc_en;
bool lsc_en;
bool mge_en;
bool lut3d_en;
bool bay3d_en;
bool is_bigmode;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
int rkisp_init_params_vdev_v39(struct rkisp_isp_params_vdev *params_vdev);
void rkisp_uninit_params_vdev_v39(struct rkisp_isp_params_vdev *params_vdev);
#else
static inline int rkisp_init_params_vdev_v39(struct rkisp_isp_params_vdev *params_vdev)
{
return -EINVAL;
}
static inline void rkisp_uninit_params_vdev_v39(struct rkisp_isp_params_vdev *params_vdev) {}
#endif
#endif /* _RKISP_PARAM_V39_H */

457
drivers/media/platform/rockchip/isp/isp_pdaf.c Normal file
View File

@@ -0,0 +1,457 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-dma-sg.h>
#include "dev.h"
#include "regs.h"
#include "isp_pdaf.h"
static int rkisp_pdaf_enum_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f)
{
if (f->index > 0)
return -EINVAL;
f->pixelformat = V4l2_PIX_FMT_SPD16;
strscpy(f->description, "Shield pix data 16-bit",
sizeof(f->description));
return 0;
}
static int rkisp_pdaf_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
struct video_device *vdev = video_devdata(file);
struct rkisp_pdaf_vdev *pdaf_vdev = video_get_drvdata(vdev);
f->fmt.pix_mp = pdaf_vdev->fmt;
return 0;
}
static int rkisp_pdaf_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
struct video_device *vdev = video_devdata(file);
struct rkisp_pdaf_vdev *pdaf_vdev = video_get_drvdata(vdev);
struct v4l2_pix_format_mplane *pixm;
u32 bytesperline;
if (!f)
return -EINVAL;
if (vb2_is_streaming(&pdaf_vdev->vnode.buf_queue)) {
v4l2_err(vdev->v4l2_dev, "%s queue busy\n", __func__);
return -EBUSY;
}
pixm = &f->fmt.pix_mp;
pixm->num_planes = 1;
pixm->field = V4L2_FIELD_NONE;
pixm->pixelformat = V4l2_PIX_FMT_SPD16;
bytesperline = ALIGN(pixm->width, 8) * 2;
if (pixm->plane_fmt[0].bytesperline > bytesperline)
bytesperline = ALIGN(pixm->plane_fmt[0].bytesperline, 16);
pixm->plane_fmt[0].bytesperline = bytesperline;
pixm->plane_fmt[0].sizeimage = bytesperline * pixm->height;
pdaf_vdev->fmt = *pixm;
return 0;
}
static int rkisp_pdaf_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
{
struct video_device *vdev = video_devdata(file);
struct rkisp_pdaf_vdev *pdaf_vdev = video_get_drvdata(vdev);
struct device *dev = pdaf_vdev->dev->dev;
strscpy(cap->card, vdev->name, sizeof(cap->card));
snprintf(cap->driver, sizeof(cap->driver),
"%s_v%d", dev->driver->name,
pdaf_vdev->dev->isp_ver >> 4);
snprintf(cap->bus_info, sizeof(cap->bus_info),
"platform:%s", dev_name(dev));
cap->version = RKISP_DRIVER_VERSION;
return 0;
}
/* ISP video device IOCTLs */
static const struct v4l2_ioctl_ops rkisp_pdaf_ioctl = {
.vidioc_reqbufs = vb2_ioctl_reqbufs,
.vidioc_querybuf = vb2_ioctl_querybuf,
.vidioc_create_bufs = vb2_ioctl_create_bufs,
.vidioc_qbuf = vb2_ioctl_qbuf,
.vidioc_dqbuf = vb2_ioctl_dqbuf,
.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
.vidioc_expbuf = vb2_ioctl_expbuf,
.vidioc_streamon = vb2_ioctl_streamon,
.vidioc_streamoff = vb2_ioctl_streamoff,
.vidioc_enum_fmt_vid_cap = rkisp_pdaf_enum_fmt,
.vidioc_g_fmt_vid_cap_mplane = rkisp_pdaf_g_fmt,
.vidioc_s_fmt_vid_cap_mplane = rkisp_pdaf_s_fmt,
.vidioc_try_fmt_vid_cap_mplane = rkisp_pdaf_s_fmt,
.vidioc_querycap = rkisp_pdaf_querycap
};
static int rkisp_pdaf_fh_open(struct file *file)
{
struct rkisp_pdaf_vdev *pdaf_vdev = video_drvdata(file);
int ret;
if (!pdaf_vdev->dev->is_probe_end)
return -EINVAL;
ret = v4l2_fh_open(file);
if (!ret) {
ret = v4l2_pipeline_pm_get(&pdaf_vdev->vnode.vdev.entity);
if (ret < 0)
vb2_fop_release(file);
}
return ret;
}
static int rkisp_pdaf_fop_release(struct file *file)
{
struct rkisp_pdaf_vdev *pdaf_vdev = video_drvdata(file);
int ret;
ret = vb2_fop_release(file);
if (!ret)
v4l2_pipeline_pm_put(&pdaf_vdev->vnode.vdev.entity);
return ret;
}
struct v4l2_file_operations rkisp_pdaf_fops = {
.mmap = vb2_fop_mmap,
.unlocked_ioctl = video_ioctl2,
.poll = vb2_fop_poll,
.open = rkisp_pdaf_fh_open,
.release = rkisp_pdaf_fop_release
};
static int rkisp_pdaf_queue_setup(struct vb2_queue *vq,
unsigned int *num_buffers,
unsigned int *num_planes,
unsigned int sizes[],
struct device *alloc_ctxs[])
{
struct rkisp_pdaf_vdev *pdaf_vdev = vq->drv_priv;
struct rkisp_device *dev = pdaf_vdev->dev;
if (!pdaf_vdev->fmt.plane_fmt[0].sizeimage)
return -EINVAL;
*num_planes = 1;
sizes[0] = pdaf_vdev->fmt.plane_fmt[0].sizeimage;
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s count %d, size %d\n",
pdaf_vdev->vnode.vdev.name, *num_buffers, sizes[0]);
return 0;
}
static void rkisp_pdaf_buf_queue(struct vb2_buffer *vb)
{
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
struct rkisp_buffer *buf = to_rkisp_buffer(vbuf);
struct vb2_queue *vq = vb->vb2_queue;
struct rkisp_pdaf_vdev *pdaf_vdev = vq->drv_priv;
struct rkisp_device *dev = pdaf_vdev->dev;
unsigned long lock_flags = 0;
struct sg_table *sgt;
if (dev->hw_dev->is_dma_sg_ops) {
sgt = vb2_dma_sg_plane_desc(vb, 0);
buf->buff_addr[0] = sg_dma_address(sgt->sgl);
} else {
buf->buff_addr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
}
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"pdaf queue buf:0x%x\n", buf->buff_addr[0]);
spin_lock_irqsave(&pdaf_vdev->vbq_lock, lock_flags);
list_add_tail(&buf->queue, &pdaf_vdev->buf_queue);
spin_unlock_irqrestore(&pdaf_vdev->vbq_lock, lock_flags);
}
static void rkisp_pdaf_stop_streaming(struct vb2_queue *vq)
{
struct rkisp_pdaf_vdev *pdaf_vdev = vq->drv_priv;
struct rkisp_device *dev = pdaf_vdev->dev;
struct rkisp_buffer *buf;
unsigned long flags = 0;
bool is_wait = dev->hw_dev->is_shutdown ? false : true;
if (!pdaf_vdev->streaming)
return;
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s state:0x%x\n", __func__, dev->isp_state);
pdaf_vdev->stopping = false;
if (dev->hw_dev->is_single)
rkisp_clear_bits(dev, ISP39_W3A_CTRL0, ISP39_W3A_PDAF_EN, false);
if (IS_HDR_RDBK(dev->rd_mode)) {
spin_lock_irqsave(&dev->hw_dev->rdbk_lock, flags);
if (dev->hw_dev->cur_dev_id != dev->dev_id || dev->hw_dev->is_idle) {
is_wait = false;
rkisp_clear_bits(dev, ISP39_W3A_CTRL0, ISP39_W3A_PDAF_EN, false);
}
spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, flags);
}
if (is_wait && (rkisp_read(dev, ISP39_W3A_CTRL0, false) & ISP39_W3A_PDAF_EN)) {
int ret = wait_event_timeout(pdaf_vdev->done,
!pdaf_vdev->streaming, msecs_to_jiffies(200));
if (!ret) {
rkisp_clear_bits(dev, ISP39_W3A_CTRL0, ISP39_W3A_PDAF_EN, false);
v4l2_warn(&dev->v4l2_dev, "%s timeout\n", __func__);
}
}
pdaf_vdev->streaming = false;
pdaf_vdev->stopping = false;
spin_lock_irqsave(&pdaf_vdev->vbq_lock, flags);
if (pdaf_vdev->curr_buf) {
list_add_tail(&pdaf_vdev->curr_buf->queue, &pdaf_vdev->buf_queue);
if (pdaf_vdev->curr_buf == pdaf_vdev->next_buf)
pdaf_vdev->next_buf = NULL;
pdaf_vdev->curr_buf = NULL;
}
if (pdaf_vdev->next_buf) {
list_add_tail(&pdaf_vdev->next_buf->queue, &pdaf_vdev->buf_queue);
pdaf_vdev->next_buf = NULL;
}
while (!list_empty(&pdaf_vdev->buf_queue)) {
buf = list_first_entry(&pdaf_vdev->buf_queue,
struct rkisp_buffer, queue);
list_del(&buf->queue);
buf->vb.vb2_buf.synced = false;
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
while (!list_empty(&pdaf_vdev->buf_done_list)) {
buf = list_first_entry(&pdaf_vdev->buf_done_list,
struct rkisp_buffer, queue);
list_del(&buf->queue);
buf->vb.vb2_buf.synced = false;
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
spin_unlock_irqrestore(&pdaf_vdev->vbq_lock, flags);
tasklet_disable(&pdaf_vdev->buf_done_tasklet);
}
static int rkisp_pdaf_start_streaming(struct vb2_queue *vq, unsigned int count)
{
struct rkisp_pdaf_vdev *pdaf_vdev = vq->drv_priv;
struct rkisp_device *dev = pdaf_vdev->dev;
u32 val;
if (pdaf_vdev->streaming)
return -EBUSY;
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s cnt:%d\n", __func__, count);
val = pdaf_vdev->fmt.plane_fmt[0].bytesperline;
rkisp_write(dev, ISP39_W3A_CTRL1, val, false);
pdaf_vdev->streaming = true;
tasklet_enable(&pdaf_vdev->buf_done_tasklet);
return 0;
}
static const struct vb2_ops rkisp_pdaf_vb2_ops = {
.queue_setup = rkisp_pdaf_queue_setup,
.buf_queue = rkisp_pdaf_buf_queue,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
.stop_streaming = rkisp_pdaf_stop_streaming,
.start_streaming = rkisp_pdaf_start_streaming,
};
static int rkisp_pdaf_init_vb2_queue(struct vb2_queue *q, struct rkisp_pdaf_vdev *pdaf_vdev)
{
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
q->drv_priv = pdaf_vdev;
q->ops = &rkisp_pdaf_vb2_ops;
q->mem_ops = pdaf_vdev->dev->hw_dev->mem_ops;
q->buf_struct_size = sizeof(struct rkisp_buffer);
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &pdaf_vdev->api_lock;
q->dev = pdaf_vdev->dev->hw_dev->dev;
q->min_buffers_needed = 1;
q->allow_cache_hints = 1;
q->bidirectional = 1;
if (pdaf_vdev->dev->hw_dev->is_dma_contig)
q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
q->gfp_flags = GFP_DMA32;
return vb2_queue_init(q);
}
static void rkisp_pdaf_buf_done_task(unsigned long arg)
{
struct rkisp_pdaf_vdev *pdaf_vdev = (struct rkisp_pdaf_vdev *)arg;
struct rkisp_buffer *buf = NULL;
unsigned long flags = 0;
LIST_HEAD(local_list);
spin_lock_irqsave(&pdaf_vdev->vbq_lock, flags);
list_replace_init(&pdaf_vdev->buf_done_list, &local_list);
spin_unlock_irqrestore(&pdaf_vdev->vbq_lock, flags);
while (!list_empty(&local_list)) {
buf = list_first_entry(&local_list, struct rkisp_buffer, queue);
list_del(&buf->queue);
v4l2_dbg(4, rkisp_debug, &pdaf_vdev->dev->v4l2_dev,
"pdaf seq:%d buf:0x%x done\n",
buf->vb.sequence, buf->buff_addr[0]);
vb2_buffer_done(&buf->vb.vb2_buf,
pdaf_vdev->streaming ? VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR);
}
}
void rkisp_pdaf_update_buf(struct rkisp_device *dev)
{
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_buffer *buf = NULL;
unsigned long flags = 0;
u32 val;
spin_lock_irqsave(&pdaf_vdev->vbq_lock, flags);
if (!pdaf_vdev->next_buf && !list_empty(&pdaf_vdev->buf_queue)) {
buf = list_first_entry(&pdaf_vdev->buf_queue,
struct rkisp_buffer, queue);
list_del(&buf->queue);
pdaf_vdev->next_buf = buf;
}
spin_unlock_irqrestore(&pdaf_vdev->vbq_lock, flags);
if (pdaf_vdev->next_buf) {
val = pdaf_vdev->next_buf->buff_addr[0];
rkisp_write(dev, ISP39_W3A_PDAF_ADDR, val, false);
if (!dev->hw_dev->is_single) {
pdaf_vdev->curr_buf = pdaf_vdev->next_buf;
pdaf_vdev->next_buf = NULL;
}
}
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s BASE:0x%x SHD:0x%x\n", __func__,
rkisp_read(dev, ISP39_W3A_PDAF_ADDR, false),
rkisp_read(dev, ISP39_W3A_PDAF_ADDR_SHD, true));
}
void rkisp_pdaf_isr(struct rkisp_device *dev)
{
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_buffer *buf = NULL;
unsigned long flags = 0;
u32 w3a_ris = rkisp_read(dev, ISP39_W3A_INT_STAT, true);
if (w3a_ris & ISP39_W3A_INT_PDAF_OVF) {
v4l2_err(&dev->v4l2_dev, "pdaf overflow 0x%x\n", w3a_ris);
rkisp_write(dev, ISP39_W3A_INT_STAT, ISP39_W3A_INT_PDAF_OVF, true);
}
if (!(w3a_ris & ISP39_W3A_INT_PDAF))
return;
rkisp_write(dev, ISP39_W3A_INT_STAT, ISP39_W3A_INT_PDAF, true);
if (pdaf_vdev->stopping) {
pdaf_vdev->stopping = false;
pdaf_vdev->streaming = false;
wake_up(&pdaf_vdev->done);
return;
}
spin_lock_irqsave(&pdaf_vdev->vbq_lock, flags);
if (pdaf_vdev->curr_buf) {
buf = pdaf_vdev->curr_buf;
pdaf_vdev->curr_buf = NULL;
}
if (pdaf_vdev->next_buf) {
pdaf_vdev->curr_buf = pdaf_vdev->next_buf;
pdaf_vdev->next_buf = NULL;
}
spin_unlock_irqrestore(&pdaf_vdev->vbq_lock, flags);
rkisp_pdaf_update_buf(dev);
if (buf) {
struct vb2_buffer *vb2_buf = &buf->vb.vb2_buf;
u32 size = pdaf_vdev->fmt.plane_fmt[0].sizeimage;
u64 ns = 0;
u32 seq = 0;
vb2_set_plane_payload(vb2_buf, 0, size);
rkisp_dmarx_get_frame(dev, &seq, NULL, &ns, true);
if (!ns)
ns = ktime_get_ns();
buf->vb.sequence = seq;
buf->vb.vb2_buf.timestamp = ns;
spin_lock_irqsave(&pdaf_vdev->vbq_lock, flags);
list_add_tail(&buf->queue, &pdaf_vdev->buf_done_list);
spin_unlock_irqrestore(&pdaf_vdev->vbq_lock, flags);
tasklet_schedule(&pdaf_vdev->buf_done_tasklet);
}
}
int rkisp_register_pdaf_vdev(struct rkisp_device *dev)
{
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_vdev_node *node = &pdaf_vdev->vnode;
struct video_device *vdev = &node->vdev;
struct media_entity *source, *sink;
int ret;
if (dev->isp_ver != ISP_V39)
return 0;
pdaf_vdev->dev = dev;
INIT_LIST_HEAD(&pdaf_vdev->buf_queue);
spin_lock_init(&pdaf_vdev->vbq_lock);
mutex_init(&pdaf_vdev->api_lock);
init_waitqueue_head(&pdaf_vdev->done);
strscpy(vdev->name, "rkisp-pdaf", sizeof(vdev->name));
vdev->ioctl_ops = &rkisp_pdaf_ioctl;
vdev->fops = &rkisp_pdaf_fops;
vdev->release = video_device_release_empty;
vdev->lock = &pdaf_vdev->api_lock;
vdev->v4l2_dev = &dev->v4l2_dev;
vdev->queue = &node->buf_queue;
vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING;
vdev->vfl_dir = VFL_DIR_RX;
rkisp_pdaf_init_vb2_queue(vdev->queue, pdaf_vdev);
video_set_drvdata(vdev, pdaf_vdev);
node->pad.flags = MEDIA_PAD_FL_SINK;
ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
if (ret < 0) {
v4l2_err(vdev->v4l2_dev,
"could not register Video for Linux device\n");
return ret;
}
ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
if (ret < 0)
goto unreg;
source = &dev->isp_sdev.sd.entity;
sink = &vdev->entity;
ret = media_create_pad_link(source, RKISP_ISP_PAD_SOURCE_STATS,
sink, 0, MEDIA_LNK_FL_ENABLED);
if (ret < 0)
goto unreg;
INIT_LIST_HEAD(&pdaf_vdev->buf_done_list);
tasklet_init(&pdaf_vdev->buf_done_tasklet,
rkisp_pdaf_buf_done_task,
(unsigned long)pdaf_vdev);
tasklet_disable(&pdaf_vdev->buf_done_tasklet);
return 0;
unreg:
video_unregister_device(vdev);
return ret;
}
void rkisp_unregister_pdaf_vdev(struct rkisp_device *dev)
{
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_vdev_node *node = &pdaf_vdev->vnode;
struct video_device *vdev = &node->vdev;
if (dev->isp_ver != ISP_V39)
return;
tasklet_kill(&pdaf_vdev->buf_done_tasklet);
media_entity_cleanup(&vdev->entity);
video_unregister_device(vdev);
}

40
drivers/media/platform/rockchip/isp/isp_pdaf.h Normal file
View File

@@ -0,0 +1,40 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_PDAF_H
#define _RKISP_PDAF_H
#include "common.h"
struct rkisp_pdaf_vdev;
struct rkisp_pdaf_vdev {
struct rkisp_device *dev;
struct rkisp_vdev_node vnode;
spinlock_t vbq_lock;
struct mutex api_lock;
struct list_head buf_queue;
struct list_head buf_done_list;
struct tasklet_struct buf_done_tasklet;
struct v4l2_pix_format_mplane fmt;
struct rkisp_buffer *curr_buf;
struct rkisp_buffer *next_buf;
wait_queue_head_t done;
bool streaming;
bool stopping;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
void rkisp_pdaf_update_buf(struct rkisp_device *dev);
void rkisp_pdaf_isr(struct rkisp_device *dev);
int rkisp_register_pdaf_vdev(struct rkisp_device *dev);
void rkisp_unregister_pdaf_vdev(struct rkisp_device *dev);
#else
static inline void rkisp_pdaf_update_buf(struct rkisp_device *dev) {}
static inline void rkisp_pdaf_isr(struct rkisp_device *dev) {}
static inline int rkisp_register_pdaf_vdev(struct rkisp_device *dev) { return 0; }
static inline void rkisp_unregister_pdaf_vdev(struct rkisp_device *dev) {}
#endif
#endif

243
drivers/media/platform/rockchip/isp/isp_sditf.c Normal file
View File

@@ -0,0 +1,243 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#include <linux/delay.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <media/v4l2-common.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-subdev.h>
#include "dev.h"
#include "isp_vpss.h"
static int rkisp_sditf_get_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct rkisp_sditf_device *sditf = v4l2_get_subdevdata(sd);
struct rkisp_device *dev = sditf->isp;
if (!fmt)
return -EINVAL;
/* get isp out format */
fmt->pad = RKISP_ISP_PAD_SOURCE_PATH;
fmt->which = V4L2_SUBDEV_FORMAT_ACTIVE;
return v4l2_subdev_call(&dev->isp_sdev.sd, pad, get_fmt, NULL, fmt);
}
static int rkisp_sditf_s_stream(struct v4l2_subdev *sd, int on)
{
struct rkisp_sditf_device *sditf = v4l2_get_subdevdata(sd);
struct rkisp_device *dev = sditf->isp;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_isp_subdev *isp_sdev = &dev->isp_sdev;
struct rkisp_stream *stream = &dev->cap_dev.stream[RKISP_STREAM_LDC];
int ret = 0;
if (stream->linked) {
v4l2_err(sd, "isp to vpss online no support for ldcpath link\n");
return -EINVAL;
}
v4l2_dbg(1, rkisp_debug, sd, "%s %d\n", __func__, on);
mutex_lock(&hw->dev_lock);
if (on) {
atomic_inc(&dev->cap_dev.refcnt);
ret = dev->pipe.open(&dev->pipe, &isp_sdev->sd.entity, true);
if (ret < 0)
goto refcnt_dec;
ret = dev->pipe.set_stream(&dev->pipe, true);
if (ret < 0)
goto pipe_close;
sditf->is_on = true;
dev->irq_ends_mask |= ISP_FRAME_VPSS;
goto unlock;
}
sditf->is_on = false;
dev->irq_ends_mask &= ~ISP_FRAME_VPSS;
dev->pipe.set_stream(&dev->pipe, false);
pipe_close:
dev->pipe.close(&dev->pipe);
refcnt_dec:
atomic_dec(&dev->cap_dev.refcnt);
unlock:
mutex_unlock(&hw->dev_lock);
return ret;
}
static int rkisp_sditf_s_power(struct v4l2_subdev *sd, int on)
{
struct rkisp_sditf_device *sditf = v4l2_get_subdevdata(sd);
struct rkisp_device *dev = sditf->isp;
struct rkisp_stream *stream = &dev->cap_dev.stream[0];
int ret = 0;
v4l2_dbg(1, rkisp_debug, sd, "%s %d\n", __func__, on);
if (on) {
sditf->remote_sd = v4l2_get_subdev_hostdata(sd);
ret = v4l2_pipeline_pm_get(&stream->vnode.vdev.entity);
} else {
v4l2_pipeline_pm_put(&stream->vnode.vdev.entity);
}
return ret;
}
void rkisp_sditf_sof(struct rkisp_device *dev, u32 irq)
{
struct rkisp_sditf_device *sditf = dev->sditf_dev;
struct rkisp_vpss_sof info;
if (!sditf || !sditf->is_on || !sditf->remote_sd)
return;
info.irq = irq;
rkisp_dmarx_get_frame(dev, &info.seq, NULL, &info.timestamp, true);
v4l2_subdev_call(sditf->remote_sd, core, ioctl, RKISP_VPSS_CMD_SOF, &info);
}
static long rkisp_sditf_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct rkisp_sditf_device *sditf = v4l2_get_subdevdata(sd);
long ret = 0;
switch (cmd) {
case RKISP_VPSS_CMD_EOF:
rkisp_check_idle(sditf->isp, ISP_FRAME_VPSS);
break;
default:
ret = -ENOIOCTLCMD;
}
return ret;
}
static const struct v4l2_subdev_pad_ops sditf_pad_ops = {
.set_fmt = rkisp_sditf_get_set_fmt,
.get_fmt = rkisp_sditf_get_set_fmt,
};
static const struct v4l2_subdev_video_ops sditf_video_ops = {
.s_stream = rkisp_sditf_s_stream,
};
static const struct v4l2_subdev_core_ops sditf_core_ops = {
.s_power = rkisp_sditf_s_power,
.ioctl = rkisp_sditf_ioctl,
};
static const struct v4l2_subdev_ops sditf_subdev_ops = {
.core = &sditf_core_ops,
.video = &sditf_video_ops,
.pad = &sditf_pad_ops,
};
static int rkisp_sditf_notifier(struct rkisp_sditf_device *sditf)
{
struct v4l2_async_notifier *ntf = &sditf->notifier;
int ret;
v4l2_async_nf_init(ntf);
ret = v4l2_async_subdev_nf_register(&sditf->sd, ntf);
if (ret) {
v4l2_async_nf_cleanup(ntf);
dev_err(sditf->dev, "failed to register async notifier:%d\n", ret);
return ret;
}
return v4l2_async_register_subdev(&sditf->sd);
}
static int rkisp_sditf_attach(struct rkisp_sditf_device *sditf)
{
struct rkisp_device *isp;
struct platform_device *pdev;
struct device_node *np;
np = of_parse_phandle(sditf->dev->of_node, "rockchip,isp", 0);
if (!np || !of_device_is_available(np)) {
dev_err(sditf->dev, "failed to get isp node\n");
return -ENODEV;
}
pdev = of_find_device_by_node(np);
of_node_put(np);
if (!pdev) {
dev_err(sditf->dev, "failed to get isp from node\n");
return -ENODEV;
}
isp = platform_get_drvdata(pdev);
if (!isp) {
dev_err(sditf->dev, "failed to attach isp\n");
return -EINVAL;
}
isp->sditf_dev = sditf;
sditf->isp = isp;
return 0;
}
static int rkisp_sditf_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rkisp_sditf_device *sditf;
struct v4l2_subdev *sd;
int ret;
sditf = devm_kzalloc(dev, sizeof(*sditf), GFP_KERNEL);
if (!sditf)
return -ENOMEM;
dev_set_drvdata(dev, sditf);
sditf->dev = dev;
sd = &sditf->sd;
v4l2_subdev_init(sd, &sditf_subdev_ops);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_COMPOSER;
strscpy(sd->name, dev_name(dev), sizeof(sd->name));
strscpy(sd->name, dev_name(dev), sizeof(sd->name));
v4l2_set_subdevdata(sd, sditf);
sd->dev = dev;
ret = rkisp_sditf_attach(sditf);
if (ret < 0)
return ret;
sditf->pad.flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&sd->entity, 1, &sditf->pad);
if (ret < 0)
return ret;
return rkisp_sditf_notifier(sditf);
}
static int rkisp_sditf_remove(struct platform_device *pdev)
{
struct rkisp_sditf_device *sditf = platform_get_drvdata(pdev);
struct v4l2_subdev *sd = &sditf->sd;
v4l2_async_nf_unregister(&sditf->notifier);
v4l2_async_nf_cleanup(&sditf->notifier);
media_entity_cleanup(&sd->entity);
v4l2_async_unregister_subdev(sd);
return 0;
}
static const struct of_device_id rkisp_sditf_of_match[] = {
{
.compatible = "rockchip,rkisp-sditf",
},
};
struct platform_driver rkisp_sditf_drv = {
.probe = rkisp_sditf_probe,
.remove = rkisp_sditf_remove,
.driver = {
.name = "rkisp_sditf",
.of_match_table = of_match_ptr(rkisp_sditf_of_match),
},
};
EXPORT_SYMBOL(rkisp_sditf_drv);

28
drivers/media/platform/rockchip/isp/isp_sditf.h Normal file
View File

@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_SDITF_H
#define _RKISP_SDITF_H
/* struct rkisp_sditf_device
* isp subdev interface link other media device
*/
struct rkisp_sditf_device {
struct device *dev;
struct rkisp_device *isp;
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_async_notifier notifier;
struct v4l2_subdev *remote_sd;
bool is_on;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
extern struct platform_driver rkisp_sditf_drv;
void rkisp_sditf_sof(struct rkisp_device *dev, u32 irq);
#else
static inline void rkisp_sditf_sof(struct rkisp_device *dev, u32 irq) {}
#endif
#endif

38
drivers/media/platform/rockchip/isp/isp_stats.c
View File

@@ -14,6 +14,7 @@
#include "isp_stats_v21.h"
#include "isp_stats_v3x.h"
#include "isp_stats_v32.h"
#include "isp_stats_v39.h"
#define STATS_NAME DRIVER_NAME "-statistics"
#define RKISP_ISP_STATS_REQ_BUFS_MIN 2
@@ -149,13 +150,16 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
unsigned long flags;
stats_buf->vaddr[0] = vb2_plane_vaddr(vb, 0);
if (dev->isp_ver == ISP_V32) {
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V39) {
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
stats_buf->buff_addr[0] = sg_dma_address(sgt->sgl);
}
if (stats_buf->vaddr[0])
if (stats_buf->vaddr[0]) {
memset(stats_buf->vaddr[0], 0, size);
if (vb->vb2_queue->mem_ops->prepare)
vb->vb2_queue->mem_ops->prepare(vb->planes[0].mem_priv);
}
spin_lock_irqsave(&stats_dev->rd_lock, flags);
if (dev->isp_ver == ISP_V32 && dev->is_pre_on) {
struct rkisp32_isp_stat_buffer *buf = stats_dev->stats_buf[0].vaddr;
@@ -181,10 +185,13 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
static void rkisp_stats_vb2_stop_streaming(struct vb2_queue *vq)
{
struct rkisp_isp_stats_vdev *stats_vdev = vq->drv_priv;
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *buf;
unsigned long flags;
int i;
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s state:0x%x\n", __func__, dev->isp_state);
/* Make sure no new work queued in isr before draining wq */
spin_lock_irqsave(&stats_vdev->irq_lock, flags);
stats_vdev->streamon = false;
@@ -223,8 +230,11 @@ rkisp_stats_vb2_start_streaming(struct vb2_queue *queue,
{
struct rkisp_isp_stats_vdev *stats_vdev = queue->drv_priv;
v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev,
"%s cnt:%d\n", __func__, count);
stats_vdev->cur_buf = NULL;
stats_vdev->ops->rdbk_enable(stats_vdev, false);
if (stats_vdev->ops->rdbk_enable)
stats_vdev->ops->rdbk_enable(stats_vdev, false);
stats_vdev->streamon = true;
kfifo_reset(&stats_vdev->rd_kfifo);
tasklet_enable(&stats_vdev->rd_tasklet);
@@ -248,7 +258,8 @@ static int rkisp_stats_init_vb2_queue(struct vb2_queue *q,
q->io_modes = VB2_MMAP | VB2_USERPTR;
q->drv_priv = stats_vdev;
q->ops = &rkisp_stats_vb2_ops;
if (stats_vdev->dev->isp_ver == ISP_V32) {
if (stats_vdev->dev->isp_ver == ISP_V32 ||
stats_vdev->dev->isp_ver == ISP_V39) {
q->mem_ops = stats_vdev->dev->hw_dev->mem_ops;
if (stats_vdev->dev->hw_dev->is_dma_contig)
q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
@@ -258,7 +269,7 @@ static int rkisp_stats_init_vb2_queue(struct vb2_queue *q,
q->buf_struct_size = sizeof(struct rkisp_buffer);
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &stats_vdev->dev->iqlock;
q->dev = stats_vdev->dev->dev;
q->dev = stats_vdev->dev->hw_dev->dev;
return vb2_queue_init(q);
}
@@ -295,8 +306,11 @@ static void rkisp_init_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_init_stats_vdev_v2x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V30)
rkisp_init_stats_vdev_v3x(stats_vdev);
else
else if (stats_vdev->dev->isp_ver == ISP_V32 ||
stats_vdev->dev->isp_ver == ISP_V32_L)
rkisp_init_stats_vdev_v32(stats_vdev);
else
rkisp_init_stats_vdev_v39(stats_vdev);
}
static void rkisp_uninit_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
@@ -309,13 +323,17 @@ static void rkisp_uninit_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_uninit_stats_vdev_v2x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V30)
rkisp_uninit_stats_vdev_v3x(stats_vdev);
else
else if (stats_vdev->dev->isp_ver == ISP_V32 ||
stats_vdev->dev->isp_ver == ISP_V32_L)
rkisp_uninit_stats_vdev_v32(stats_vdev);
else
rkisp_uninit_stats_vdev_v39(stats_vdev);
}
void rkisp_stats_rdbk_enable(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
{
stats_vdev->ops->rdbk_enable(stats_vdev, en);
if (stats_vdev->ops->rdbk_enable)
stats_vdev->ops->rdbk_enable(stats_vdev, en);
}
void rkisp_stats_first_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev)
@@ -328,12 +346,16 @@ void rkisp_stats_first_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_stats_first_ddr_config_v3x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V32)
rkisp_stats_first_ddr_config_v32(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V39)
rkisp_stats_first_ddr_config_v39(stats_vdev);
}
void rkisp_stats_next_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev)
{
if (stats_vdev->dev->isp_ver == ISP_V32)
rkisp_stats_next_ddr_config_v32(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V39)
rkisp_stats_next_ddr_config_v39(stats_vdev);
}
void rkisp_stats_isr(struct rkisp_isp_stats_vdev *stats_vdev,

456
drivers/media/platform/rockchip/isp/isp_stats_v39.c Normal file
View File

@@ -0,0 +1,456 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#include <linux/delay.h>
#include <linux/kfifo.h>
#include <linux/rk-isp32-config.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-core.h>
#include "dev.h"
#include "regs.h"
#include "common.h"
#include "isp_stats.h"
#include "isp_stats_v39.h"
#include "isp_params_v39.h"
static u32 isp3_stats_read(struct rkisp_isp_stats_vdev *stats_vdev, u32 addr)
{
return rkisp_read(stats_vdev->dev, addr, true);
}
static void isp3_stats_write(struct rkisp_isp_stats_vdev *stats_vdev,
u32 addr, u32 value)
{
rkisp_write(stats_vdev->dev, addr, value, true);
}
static int
rkisp_stats_get_dhaz_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp39_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
struct rkisp_isp_params_val_v39 *priv_val = params_vdev->priv_val;
struct isp39_isp_params_cfg *params_rec = params_vdev->isp39_params;
struct isp39_dhaz_cfg *arg_rec = &params_rec->others.dhaz_cfg;
struct isp39_dhaz_stat *dhaz;
int value, i, j, timeout;
if (!pbuf)
return 0;
value = isp3_stats_read(stats_vdev, ISP3X_DHAZ_CTRL);
if (value & ISP_DHAZ_ENMUX) {
dhaz = &pbuf->stat.dhaz;
value = isp3_stats_read(stats_vdev, ISP39_DHAZ_ADP_RD0);
dhaz->adp_air_base = (value >> 16) & 0xFFFF;
dhaz->adp_wt = value & 0xFFFF;
value = isp3_stats_read(stats_vdev, ISP39_DHAZ_ADP_RD1);
dhaz->adp_tmax = value & 0xFFFF;
for (i = 0; i < priv_val->dhaz_blk_num; i++) {
value = ISP39_DHAZ_IIR_RD_ID(i) | ISP39_DHAZ_IIR_RD_P;
isp3_stats_write(stats_vdev, ISP39_DHAZ_HIST_RW, value);
timeout = 5;
while (timeout--) {
value = isp3_stats_read(stats_vdev, ISP39_DHAZ_HIST_RW);
if (value & ISP39_DHAZ_IIR_RDATA_VAL)
break;
udelay(2);
}
if (timeout < 0) {
v4l2_warn(&dev->v4l2_dev, "%s read:%d timeout\n", __func__, i);
goto end;
}
for (j = 0; j < ISP39_DHAZ_HIST_IIR_NUM / 2; j++) {
value = isp3_stats_read(stats_vdev, ISP39_DHAZ_HIST_IIR0 + 4 * j);
dhaz->hist_iir[i][2 * j] = value & 0xFFFF;
dhaz->hist_iir[i][2 * j + 1] = value >> 16;
}
}
if (!dev->hw_dev->is_single) {
arg_rec->hist_iir_wr = true;
memcpy(arg_rec->hist_iir, dhaz->hist_iir, sizeof(dhaz->hist_iir));
}
pbuf->meas_type |= ISP39_STAT_DHAZ;
}
end:
return 0;
}
static int
rkisp_stats_get_bay3d_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp39_stat_buffer *pbuf)
{
struct isp39_bay3d_stat *bay3d;
u32 i, value;
if (!pbuf)
return 0;
value = isp3_stats_read(stats_vdev, ISP3X_BAY3D_CTRL);
if (value & 0x1) {
bay3d = &pbuf->stat.bay3d;
value = isp3_stats_read(stats_vdev, ISP39_BAY3D_SIGSUM);
bay3d->tnr_auto_sigma_count = value;
for (i = 0; i < ISP39_BAY3D_TNRSIG_NUM / 2; i++) {
value = isp3_stats_read(stats_vdev, ISP39_BAY3D_TNRSIGYO0 + i * 4);
bay3d->tnr_auto_sigma_calc[i * 2] = value & 0xfff;
bay3d->tnr_auto_sigma_calc[i * 2 + 1] = (value >> 16) & 0xfff;
}
pbuf->meas_type |= ISP39_STAT_BAY3D;
}
return 0;
}
static int
rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *buf;
unsigned long flags;
u32 val, addr = 0, offset = 0;
int ret = 0;
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) {
buf = list_first_entry(&stats_vdev->stat,
struct rkisp_buffer, queue);
list_del(&buf->queue);
stats_vdev->nxt_buf = buf;
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (stats_vdev->nxt_buf) {
addr = stats_vdev->nxt_buf->buff_addr[0];
val = stats_vdev->nxt_buf->buff_addr[0];
rkisp_write(dev, ISP39_W3A_AEBIG_ADDR, val, false);
offset = sizeof(struct isp39_rawae_stat) + sizeof(struct isp39_rawhist_stat);
val += offset;
rkisp_write(dev, ISP39_W3A_AE0_ADDR, val, false);
val += offset;
rkisp_write(dev, ISP39_W3A_AF_ADDR, val, false);
offset = sizeof(struct isp39_rawaf_stat);
val += offset;
rkisp_write(dev, ISP39_W3A_AWB_ADDR, val, false);
if (!dev->hw_dev->is_single) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
} else if (stats_vdev->stats_buf[0].mem_priv) {
addr = stats_vdev->stats_buf[0].dma_addr;
val = stats_vdev->stats_buf[0].dma_addr;
rkisp_write(dev, ISP39_W3A_AEBIG_ADDR, val, false);
offset = sizeof(struct isp39_rawae_stat) + sizeof(struct isp39_rawhist_stat);
val += offset;
rkisp_write(dev, ISP39_W3A_AE0_ADDR, val, false);
val += offset;
rkisp_write(dev, ISP39_W3A_AF_ADDR, val, false);
offset = sizeof(struct isp39_rawaf_stat);
val += offset;
rkisp_write(dev, ISP39_W3A_AWB_ADDR, val, false);
} else {
ret = -EINVAL;
}
if (addr)
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s BASE:0x%x SHD AEBIG:0x%x AE0:0x%x AF:0x%x AWB:0x%x\n",
__func__, addr,
isp3_stats_read(stats_vdev, ISP39_W3A_AEBIG_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AE0_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AF_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AWB_ADDR_SHD));
return ret;
}
static void
rkisp_stats_info2ddr(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp39_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_val_v39 *priv_val;
struct rkisp_dummy_buffer *buf;
int idx, buf_fd = -1;
u32 reg = 0, ctrl, mask;
priv_val = dev->params_vdev.priv_val;
if (!priv_val->buf_info_owner && priv_val->buf_info_idx >= 0) {
priv_val->buf_info_idx = -1;
rkisp_clear_bits(dev, ISP3X_GAIN_CTRL, ISP3X_GAIN_2DDR_EN, false);
rkisp_clear_bits(dev, ISP3X_RAWAWB_CTRL, ISP32_RAWAWB_2DDR_PATH_EN, false);
return;
}
if (priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_GAIN) {
reg = ISP3X_GAIN_CTRL;
ctrl = ISP3X_GAIN_2DDR_EN;
mask = ISP3X_GAIN_2DDR_EN;
} else {
reg = ISP3X_RAWAWB_CTRL;
ctrl = ISP32_RAWAWB_2DDR_PATH_EN;
mask = ISP32_RAWAWB_2DDR_PATH_EN | ISP32_RAWAWB_2DDR_PATH_DS;
}
idx = priv_val->buf_info_idx;
if (idx >= 0) {
buf = &priv_val->buf_info[idx];
rkisp_finish_buffer(dev, buf);
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s data:0x%x 0x%x:0x%x\n", __func__,
*(u32 *)buf->vaddr, reg, rkisp_read(dev, reg, true));
if (*(u32 *)buf->vaddr != RKISP_INFO2DDR_BUF_INIT && pbuf &&
(reg != ISP3X_RAWAWB_CTRL ||
!(rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR))) {
pbuf->stat.info2ddr.buf_fd = buf->dma_fd;
pbuf->stat.info2ddr.owner = priv_val->buf_info_owner;
pbuf->meas_type |= ISP39_STAT_INFO2DDR;
buf_fd = buf->dma_fd;
} else if (reg == ISP3X_RAWAWB_CTRL &&
rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR) {
v4l2_warn(&dev->v4l2_dev, "rawawb2ddr path error idx:%d\n", idx);
} else {
u32 v0 = rkisp_read(dev, reg, false);
u32 v1 = rkisp_read_reg_cache(dev, reg);
if ((v0 & mask) != (v1 & mask))
rkisp_write(dev, reg, v0 | (v1 & mask), false);
}
if (buf_fd == -1)
return;
}
/* get next unused buf to hw */
for (idx = 0; idx < priv_val->buf_info_cnt; idx++) {
buf = &priv_val->buf_info[idx];
if (*(u32 *)buf->vaddr == RKISP_INFO2DDR_BUF_INIT)
break;
}
if (idx == priv_val->buf_info_cnt) {
rkisp_clear_bits(dev, reg, ctrl, false);
priv_val->buf_info_idx = -1;
} else {
buf = &priv_val->buf_info[idx];
rkisp_write(dev, ISP3X_MI_GAIN_WR_BASE, buf->dma_addr, false);
if (dev->hw_dev->is_single)
rkisp_write(dev, ISP3X_MI_WR_CTRL2, ISP3X_GAINSELF_UPD, true);
if (priv_val->buf_info_idx < 0)
rkisp_set_bits(dev, reg, 0, ctrl, false);
priv_val->buf_info_idx = idx;
}
}
static void
rkisp_stats_send_meas_v39(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work)
{
struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev;
struct rkisp_buffer *cur_buf = stats_vdev->cur_buf;
struct rkisp39_stat_buffer *cur_stat_buf = NULL;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 cur_frame_id = meas_work->frame_id;
bool is_dummy = false;
unsigned long flags;
if (!stats_vdev->rdbk_drop) {
if (!cur_buf && stats_vdev->stats_buf[0].mem_priv) {
rkisp_finish_buffer(stats_vdev->dev, &stats_vdev->stats_buf[0]);
cur_stat_buf = stats_vdev->stats_buf[0].vaddr;
cur_stat_buf->frame_id = -1;
is_dummy = true;
} else if (cur_buf) {
cur_stat_buf = cur_buf->vaddr[0];
}
/* config buf for next frame */
stats_vdev->cur_buf = NULL;
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
rkisp_stats_update_buf(stats_vdev);
cur_frame_id = meas_work->frame_id;
} else {
cur_buf = NULL;
}
if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB && cur_stat_buf)
cur_stat_buf->meas_type |= ISP39_STAT_RAWAWB;
if (meas_work->isp3a_ris & ISP3X_3A_RAWAF && cur_stat_buf)
cur_stat_buf->meas_type |= ISP39_STAT_RAWAF;
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG && cur_stat_buf)
cur_stat_buf->meas_type |= ISP39_STAT_RAWAE3;
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG && cur_stat_buf)
cur_stat_buf->meas_type |= ISP39_STAT_RAWHST3;
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0 && cur_stat_buf)
cur_stat_buf->meas_type |= ISP39_STAT_RAWAE0;
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0 && cur_stat_buf)
cur_stat_buf->meas_type |= ISP39_STAT_RAWHST0;
if (meas_work->isp_ris & ISP3X_FRAME) {
rkisp_stats_get_dhaz_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_bay3d_stats(stats_vdev, cur_stat_buf);
}
if (is_dummy) {
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!list_empty(&stats_vdev->stat)) {
cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue);
list_del(&cur_buf->queue);
} else {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (cur_buf) {
memcpy(cur_buf->vaddr[0], cur_stat_buf, size);
cur_stat_buf = cur_buf->vaddr[0];
}
}
if (cur_buf && cur_stat_buf) {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
cur_stat_buf->stat.info2ddr.buf_fd = -1;
cur_stat_buf->stat.info2ddr.owner = 0;
rkisp_stats_info2ddr(stats_vdev, cur_stat_buf);
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
cur_buf->vb.sequence = cur_frame_id;
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
v4l2_dbg(4, rkisp_debug, &stats_vdev->dev->v4l2_dev,
"%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x\n",
__func__,
cur_frame_id, params_vdev->cur_frame_id, meas_work->isp3a_ris,
cur_buf, !cur_stat_buf ? 0 : cur_stat_buf->meas_type);
}
static void
rkisp_stats_isr_v39(struct rkisp_isp_stats_vdev *stats_vdev,
u32 isp_ris, u32 isp3a_ris)
{
struct rkisp_isp_readout_work work;
u32 cur_frame_id, isp_mis_tmp = 0;
u32 temp_isp3a_ris;
rkisp_dmarx_get_frame(stats_vdev->dev, &cur_frame_id, NULL, NULL, true);
temp_isp3a_ris = isp3_stats_read(stats_vdev, ISP3X_ISP_3A_RIS);
isp_mis_tmp = temp_isp3a_ris;
if (isp_mis_tmp) {
isp3_stats_write(stats_vdev, ISP3X_ISP_3A_ICR, isp_mis_tmp);
isp_mis_tmp &= isp3_stats_read(stats_vdev, ISP3X_ISP_3A_MIS);
if (isp_mis_tmp)
v4l2_err(stats_vdev->vnode.vdev.v4l2_dev,
"isp3A icr 3A info err: 0x%x 0x%x\n",
isp_mis_tmp, isp3a_ris);
}
rkisp_pdaf_isr(stats_vdev->dev);
if (isp_ris & ISP3X_FRAME) {
work.readout = RKISP_ISP_READOUT_MEAS;
work.frame_id = cur_frame_id;
work.isp_ris = isp_ris;
work.isp3a_ris = temp_isp3a_ris;
work.timestamp = ktime_get_ns();
rkisp_stats_send_meas_v39(stats_vdev, &work);
}
}
static void
rkisp_get_stat_size_v39(struct rkisp_isp_stats_vdev *stats_vdev,
unsigned int sizes[])
{
int mult = stats_vdev->dev->unite_div;
sizes[0] = ALIGN(sizeof(struct rkisp39_stat_buffer), 16);
sizes[0] *= mult;
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v39,
.send_meas = rkisp_stats_send_meas_v39,
.get_stat_size = rkisp_get_stat_size_v39,
};
void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
u32 val, size = 0;
if (!stats_vdev->streamon || dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
rkisp_get_stat_size_v39(stats_vdev, &size);
stats_vdev->stats_buf[0].is_need_vaddr = true;
stats_vdev->stats_buf[0].size = size;
if (rkisp_alloc_buffer(dev, &stats_vdev->stats_buf[0]))
v4l2_warn(&dev->v4l2_dev, "stats alloc buf fail\n");
else
memset(stats_vdev->stats_buf[0].vaddr, 0, size);
if (rkisp_stats_update_buf(stats_vdev) < 0) {
v4l2_err(&dev->v4l2_dev, "no stats buf to enable w3a\n");
return;
}
rkisp_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false);
val = ISP39_W3A_EN | ISP39_W3A_AUTO_CLR_EN | ISP39_W3A_FORCE_UPD;
if (pdaf_vdev->streaming) {
val |= ISP39_W3A_PDAF_EN;
rkisp_pdaf_update_buf(dev);
if (pdaf_vdev->next_buf) {
pdaf_vdev->curr_buf = pdaf_vdev->next_buf;
pdaf_vdev->next_buf = NULL;
}
}
rkisp_write(dev, ISP39_W3A_CTRL0, val, false);
rkisp_write(dev, ISP39_W3A_WR_SIZE, size, false);
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
}
void rkisp_stats_next_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
if (!stats_vdev->streamon || dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
/* pingpong buf */
if (hw->is_single) {
rkisp_stats_update_buf(stats_vdev);
if (pdaf_vdev->streaming)
rkisp_pdaf_update_buf(dev);
}
}
void rkisp_init_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
}
void rkisp_uninit_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev)
{
}

28
drivers/media/platform/rockchip/isp/isp_stats_v39.h Normal file
View File

@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_STATS_V39_H
#define _RKISP_STATS_V39_H
#include <linux/rk-isp1-config.h>
#include <linux/interrupt.h>
#include <linux/kfifo.h>
#include "common.h"
#define ISP39_RD_STATS_BUF_SIZE 0x10000
struct rkisp_isp_stats_vdev;
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_stats_next_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_stats_next_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif
#endif /* _RKISP_STATS_V39_H */

19
drivers/media/platform/rockchip/isp/isp_vpss.h Normal file
View File

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_VPSS_H
#define _RKISP_VPSS_H
#define RKISP_VPSS_CMD_SOF \
_IOW('V', BASE_VIDIOC_PRIVATE + 0, struct rkisp_vpss_sof)
#define RKISP_VPSS_CMD_EOF \
_IO('V', BASE_VIDIOC_PRIVATE + 1)
struct rkisp_vpss_sof {
u32 irq;
u32 seq;
u64 timestamp;
};
#endif

138
drivers/media/platform/rockchip/isp/procfs.c
View File

@@ -828,6 +828,140 @@ static void isp32_show(struct rkisp_device *dev, struct seq_file *p)
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
}
static void isp39_show(struct rkisp_device *dev, struct seq_file *p)
{
u32 full_range_flg = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
static const char * const effect[] = { "OFF", "BLACKWHITE" };
u32 val, val1, val2;
val = rkisp_read(dev, ISP3X_GIC_CONTROL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "GIC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_CAC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CAC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
seq_printf(p, "%-10s %s(0x%x)\n", "SDG", (val & BIT(6)) ? "ON" : "OFF", val);
seq_printf(p, "%-10s %s(0x%x) (gain0:0x%08x 0x%08x gain1:0x%x 0x%x)\n", "AWBGAIN",
(val & BIT(7)) ? "ON" : "OFF", val,
rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_G, false),
rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_RB, false),
rkisp_read(dev, ISP32_ISP_AWB1_GAIN_G, false),
rkisp_read(dev, ISP32_ISP_AWB1_GAIN_RB, false));
val = rkisp_read(dev, ISP3X_DPCC0_MODE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "DPCC0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_DPCC1_MODE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "DPCC1", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_BLS_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "BLS", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_LSC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "LSC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_DEBAYER_CONTROL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "DEBAYER", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_CCM_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CCM", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_GAMMA_OUT_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "GAMMA_OUT", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_CPROC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CPROC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_IMG_EFF_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) (effect: %s)\n", "IE", (val & 1) ? "ON" : "OFF",
val, effect[!!val]);
val = rkisp_read(dev, ISP3X_DRC_CTRL0, false);
seq_printf(p, "%-10s %s(0x%x)\n", "HDRDRC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_HDRMGE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "HDRMGE", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_BAY3D_CTRL, false);
val1 = rkisp_read(dev, ISP39_BAY3D_CTRL1, false);
val2 = rkisp_read(dev, ISP39_BAY3D_CTRL2, false);
seq_printf(p, "%-10s %s(0x%x 0x%x 0x%x)\n", "BAY3D",
(val & 1) ? "ON" : "OFF", val, val1, val2);
val = rkisp_read(dev, ISP3X_YNR_GLOBAL_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "YNR", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_CNR_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CNR", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_SHARP_EN, false);
seq_printf(p, "%-10s %s(0x%x)\n", "SHARP", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_DHAZ_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "DHAZ", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_3DLUT_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "3DLUT", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_LDCH_STS, false);
seq_printf(p, "%-10s %s(0x%x)\n", "LDCH", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP39_LDCV_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "LDCV", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP39_YUVME_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "YUVME", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP39_RGBIR_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RGBIR", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
val1 = rkisp_read(dev, ISP3X_ISP_CC_COEFF_0, false);
seq_printf(p, "%-10s %s(0x%x), y_offs:0x%x c_offs:0x%x\n"
"\t coeff Y:0x%x 0x%x 0x%x CB:0x%x 0x%x 0x%x CR:0x%x 0x%x 0x%x\n",
"CSM", (val & full_range_flg) ? "FULL" : "LIMIT", val,
(val1 >> 24) & 0x3f,
(val1 >> 16) & 0xff ? (val1 >> 16) & 0xff : 128,
val1 & 0x1ff,
rkisp_read(dev, ISP3X_ISP_CC_COEFF_1, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_2, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_3, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_4, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_5, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_6, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_7, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_8, false));
val = rkisp_read(dev, ISP3X_GAIN_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "GAIN", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAF_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAF", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAWB_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAWB", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAE_LITE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAE0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAE_BIG1_BASE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAE3", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWHIST_LITE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWHIST0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWHIST_BIG1_BASE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWHIST3", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_ISP_CTRL1, true);
seq_printf(p, "%-10s %s(0x%x)\n", "BigMode", val & BIT(28) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP32_BLS_ISP_OB_PREDGAIN, false);
seq_printf(p, "%-10s %s(0x%x)\n", "OB", val ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_ISP_DEBUG1, true);
seq_printf(p, "%-10s space full status group (0x%x)\n"
"\t ibuf2:0x%x ibuf1:0x%x ibuf0:0x%x mpfbc_infifo:0x%x\n"
"\t r1fifo:0x%x r0fifo:0x%x outfifo:0x%x lafifo:0x%x\n",
"DEBUG1", val,
val >> 28, (val >> 24) & 0xf, (val >> 20) & 0xf, (val >> 16) & 0xf,
(val >> 12) & 0xf, (val >> 8) & 0xf, (val >> 4) & 0xf, val & 0xf);
val = rkisp_read(dev, ISP3X_ISP_DEBUG2, true);
seq_printf(p, "%-10s 0x%x\n"
"\t bay3d_fifo_full iir:%d cur:%d\n"
"\t module outform vertical counter:%d, out frame counter:%d\n"
"\t isp output line counter:%d\n",
"DEBUG2", val, !!(val & BIT(31)), !!(val & BIT(30)),
(val >> 16) & 0x3fff, (val >> 14) & 0x3, val & 0x3fff);
val = rkisp_read(dev, ISP3X_ISP_DEBUG3, true);
seq_printf(p, "%-10s isp pipeline group (0x%x)\n"
"\t mge(%d %d) rawnr(%d %d) bay3d(%d %d) tmo(%d %d)\n"
"\t gic(%d %d) dbr(%d %d) debayer(%d %d) dhaz(%d %d)\n"
"\t lut3d(%d %d) ldch(%d %d) ynr(%d %d) shp(%d %d)\n"
"\t cgc(%d %d) cac(%d %d) isp_out(%d %d) isp_in(%d %d)\n",
"DEBUG3", val,
!!(val & BIT(31)), !!(val & BIT(30)), !!(val & BIT(29)), !!(val & BIT(28)),
!!(val & BIT(27)), !!(val & BIT(26)), !!(val & BIT(25)), !!(val & BIT(24)),
!!(val & BIT(23)), !!(val & BIT(22)), !!(val & BIT(21)), !!(val & BIT(20)),
!!(val & BIT(19)), !!(val & BIT(18)), !!(val & BIT(17)), !!(val & BIT(16)),
!!(val & BIT(15)), !!(val & BIT(14)), !!(val & BIT(13)), !!(val & BIT(12)),
!!(val & BIT(11)), !!(val & BIT(10)), !!(val & BIT(9)), !!(val & BIT(8)),
!!(val & BIT(7)), !!(val & BIT(6)), !!(val & BIT(5)), !!(val & BIT(4)),
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
val = rkisp_read(dev, ISP32_ISP_DEBUG4, true);
seq_printf(p, "%-10s isp pipeline group (0x%x)\n"
"\t expd(%d %d) ynr(%d %d)\n",
"DEBUG4", val,
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
}
static int isp_show(struct seq_file *p, void *v)
{
struct rkisp_device *dev = p->private;
@@ -949,6 +1083,10 @@ static int isp_show(struct seq_file *p, void *v)
if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32))
isp32_show(dev, p);
break;
case ISP_V39:
if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39))
isp39_show(dev, p);
break;
default:
break;
}

101
drivers/media/platform/rockchip/isp/regs.c
View File

@@ -348,20 +348,21 @@ static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in
struct v4l2_rect *out_c, bool async)
{
struct rkisp_device *dev = stream->ispdev;
u32 rsz_ctrl = 0, val, hy, hc;
u32 rsz_ctrl = 0, hy = 1, hc = 1, reg, val, in_w, out_w;
bool is_avg = false;
rkisp_unite_write(dev, ISP32_SELF_SCALE_HY_OFFS, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_HC_OFFS, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_PHASE_HY, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_PHASE_HC, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_PHASE_VY, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_PHASE_VC, 0, true);
val = in_y->width | in_y->height << 16;
rkisp_write(dev, ISP32_SELF_SCALE_SRC_SIZE, val, false);
val = out_y->width | out_y->height << 16;
rkisp_write(dev, ISP32_SELF_SCALE_DST_SIZE, val, false);
in_w = in_y->width;
out_w = out_y->width;
if (dev->unite_div > ISP_UNITE_DIV1) {
in_w = in_y->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
out_w /= 2;
}
val = in_w | in_y->height << 16;
reg = stream->config->rsz.src_size;
rkisp_unite_write(dev, reg, val, false);
val = out_w | out_y->height << 16;
reg = stream->config->rsz.dst_size;
rkisp_unite_write(dev, reg, val, false);
if (in_y->width != out_y->width) {
rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE | CIF_RSZ_CTRL_SCALE_HC_ENABLE;
@@ -373,8 +374,10 @@ static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in
hy = ((in_y->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->width - 1);
hc = ((in_c->width - 1) * ISP32_SCALE_BIL_FACTOR) / (out_c->width - 1);
}
rkisp_write(dev, ISP32_SELF_SCALE_HY_FAC, hy, false);
rkisp_write(dev, ISP32_SELF_SCALE_HC_FAC, hc, false);
reg = stream->config->rsz.scale_hy;
rkisp_unite_write(dev, reg, hy, false);
reg = stream->config->rsz.scale_hcr;
rkisp_unite_write(dev, reg, hc, false);
}
if (in_y->height != out_y->height) {
@@ -385,15 +388,71 @@ static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in
} else {
val = ((in_y->height - 1) * ISP32_SCALE_BIL_FACTOR) / (out_y->height - 1);
}
rkisp_write(dev, ISP32_SELF_SCALE_VY_FAC, val, false);
rkisp_write(dev, ISP32_SELF_SCALE_VC_FAC, val, false);
reg = stream->config->rsz.scale_vy;
rkisp_unite_write(dev, reg, val, false);
reg = stream->config->rsz.scale_vc;
rkisp_unite_write(dev, reg, val, false);
}
rkisp_write(dev, ISP32_SELF_SCALE_CTRL, rsz_ctrl, false);
if (dev->unite_div > ISP_UNITE_DIV1) {
u32 right_fst_point_y = out_w * hy;
u32 right_fst_point_c = out_w / 2 * hc;
u32 left_in_used_size_y = right_fst_point_y / ISP32_SCALE_BIL_FACTOR;
u32 left_in_used_size_c = right_fst_point_c / ISP32_SCALE_BIL_FACTOR * 2;
u32 phase_left_y = right_fst_point_y & 0xfff;
u32 phase_left_c = right_fst_point_c & 0xfff;
u32 right_scl_need_size_y = in_y->width - left_in_used_size_y;
u32 right_scl_need_size_c = in_y->width - left_in_used_size_c;
u32 right_scl_in_size_y = in_w - right_scl_need_size_y;
u32 right_scl_in_size_c = in_w - right_scl_need_size_c;
u32 scl_in_hy_offs = right_scl_in_size_y - RKMOUDLE_UNITE_EXTEND_PIXEL;
u32 scl_in_hc_offs = right_scl_in_size_c - RKMOUDLE_UNITE_EXTEND_PIXEL;
/* left isp */
reg = stream->config->rsz.scale_hy_offs;
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
reg = stream->config->rsz.scale_hc_offs;
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
reg = stream->config->rsz.scale_hy_offs_mi;
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
reg = stream->config->rsz.scale_hc_offs_mi;
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
reg = stream->config->rsz.scale_in_crop_offs;
rkisp_idx_write(dev, reg, 0, ISP_UNITE_LEFT, false);
reg = stream->config->rsz.scale_hy_size;
rkisp_idx_write(dev, reg, out_w, ISP_UNITE_LEFT, false);
reg = stream->config->rsz.scale_hc_size;
rkisp_idx_write(dev, reg, out_w, ISP_UNITE_LEFT, false);
/* right isp */
reg = stream->config->rsz.scale_hy_size;
rkisp_idx_write(dev, reg, out_w, ISP_UNITE_RIGHT, false);
reg = stream->config->rsz.scale_hc_size;
rkisp_idx_write(dev, reg, out_w, ISP_UNITE_RIGHT, false);
reg = stream->config->rsz.scale_hy_offs;
rkisp_idx_write(dev, reg, phase_left_y, ISP_UNITE_RIGHT, false);
reg = stream->config->rsz.scale_hc_offs;
rkisp_idx_write(dev, reg, phase_left_c, ISP_UNITE_RIGHT, false);
reg = stream->config->rsz.scale_hy_offs_mi;
rkisp_idx_write(dev, reg, out_w & 15, ISP_UNITE_RIGHT, false);
reg = stream->config->rsz.scale_hc_offs_mi;
rkisp_idx_write(dev, reg, out_w & 15, ISP_UNITE_RIGHT, false);
reg = stream->config->rsz.scale_in_crop_offs;
val = scl_in_hc_offs << 4 | scl_in_hy_offs;
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
rsz_ctrl |= ISP32_SCL_CLIP_EN;
reg = stream->config->rsz.ctrl;
rkisp_idx_write(dev, reg, rsz_ctrl | ISP32_SCL_IN_CLIP_EN,
ISP_UNITE_RIGHT, false);
}
reg = stream->config->rsz.ctrl;
rkisp_write(dev, reg, rsz_ctrl, false);
val = ISP32_SCALE_FORCE_UPD;
if (async && dev->hw_dev->is_single)
val = ISP32_SCALE_GEN_UPD;
rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, val, true);
reg = stream->config->rsz.update;
rkisp_write(dev, reg, val, false);
}
void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
@@ -403,7 +462,8 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
struct rkisp_device *dev = stream->ispdev;
int i = 0;
if (dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP) {
if (dev->isp_ver == ISP_V39 ||
(dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP)) {
set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async);
return;
}
@@ -428,7 +488,8 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
void rkisp_disable_rsz(struct rkisp_stream *stream, bool async)
{
rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false);
if (stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP)
if (stream->ispdev->isp_ver == ISP_V39 ||
(stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP))
return;
update_rsz_shadow(stream, async);
}

1
drivers/media/platform/rockchip/isp/regs.h
View File

@@ -405,6 +405,7 @@
#define CIF_CSI2_DT_RAW8 0x2A
#define CIF_CSI2_DT_RAW10 0x2B
#define CIF_CSI2_DT_RAW12 0x2C
#define CIF_CSI2_DT_RAW16 0x2e
#define CIF_CSI2_DT_SPD 0x2F
/* MIPI_IMSC, MIPI_RIS, MIPI_MIS, MIPI_ICR, MIPI_ISR */

562
drivers/media/platform/rockchip/isp/regs_v3x.h
View File

@@ -223,6 +223,16 @@
#define ISP3X_CCM_BOUND_BIT (ISP3X_CCM_BASE + 0x00048)
#define ISP32_CCM_ENHANCE0 (ISP3X_CCM_BASE + 0x0004c)
#define ISP32_CCM_ENHANCE1 (ISP3X_CCM_BASE + 0x00050)
#define ISP39_CCM_HF_THD (ISP3X_CCM_BASE + 0x00054)
#define ISP39_HF_FACTOR0 (ISP3X_CCM_BASE + 0x00058)
#define ISP39_HF_FACTOR1 (ISP3X_CCM_BASE + 0x0005c)
#define ISP39_HF_FACTOR2 (ISP3X_CCM_BASE + 0x00060)
#define ISP39_HF_FACTOR3 (ISP3X_CCM_BASE + 0x00064)
#define ISP39_HF_FACTOR4 (ISP3X_CCM_BASE + 0x00068)
#define ISP39_HF_FACTOR5 (ISP3X_CCM_BASE + 0x0006c)
#define ISP39_HF_FACTOR6 (ISP3X_CCM_BASE + 0x00070)
#define ISP39_HF_FACTOR7 (ISP3X_CCM_BASE + 0x00074)
#define ISP39_HF_FACTOR8 (ISP3X_CCM_BASE + 0x00078)
#define ISP3X_CPROC_BASE 0x00000800
#define ISP3X_CPROC_CTRL (ISP3X_CPROC_BASE + 0x00000)
@@ -320,6 +330,45 @@
#define ISP3X_MAIN_RESIZE_HC_OFFS_MI_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00074)
#define ISP3X_MAIN_RESIZE_IN_CROP_OFFSET (ISP3X_MAIN_RESIZE_BASE + 0x00078)
#define ISP39_MAIN_SCALE_BASE 0x00000c00
#define ISP39_MAIN_SCALE_CTRL (ISP39_MAIN_SCALE_BASE + 0x0000)
#define ISP39_MAIN_SCALE_UPDATE (ISP39_MAIN_SCALE_BASE + 0x0004)
#define ISP39_MAIN_SCALE_SRC_SIZE (ISP39_MAIN_SCALE_BASE + 0x0008)
#define ISP39_MAIN_SCALE_DST_SIZE (ISP39_MAIN_SCALE_BASE + 0x000c)
#define ISP39_MAIN_SCALE_HY_FAC (ISP39_MAIN_SCALE_BASE + 0x0010)
#define ISP39_MAIN_SCALE_HC_FAC (ISP39_MAIN_SCALE_BASE + 0x0014)
#define ISP39_MAIN_SCALE_VY_FAC (ISP39_MAIN_SCALE_BASE + 0x0018)
#define ISP39_MAIN_SCALE_VC_FAC (ISP39_MAIN_SCALE_BASE + 0x001c)
#define ISP39_MAIN_SCALE_HY_OFFS (ISP39_MAIN_SCALE_BASE + 0x0020)
#define ISP39_MAIN_SCALE_HC_OFFS (ISP39_MAIN_SCALE_BASE + 0x0024)
#define ISP39_MAIN_SCALE_PHASE_HY (ISP39_MAIN_SCALE_BASE + 0x0030)
#define ISP39_MAIN_SCALE_PHASE_HC (ISP39_MAIN_SCALE_BASE + 0x0034)
#define ISP39_MAIN_SCALE_PHASE_VY (ISP39_MAIN_SCALE_BASE + 0x0038)
#define ISP39_MAIN_SCALE_PHASE_VC (ISP39_MAIN_SCALE_BASE + 0x003c)
#define ISP39_MAIN_SCALE_HY_SIZE (ISP39_MAIN_SCALE_BASE + 0x0040)
#define ISP39_MAIN_SCALE_HC_SIZE (ISP39_MAIN_SCALE_BASE + 0x0044)
#define ISP39_MAIN_SCALE_HY_OFFS_MI (ISP39_MAIN_SCALE_BASE + 0x0048)
#define ISP39_MAIN_SCALE_HC_OFFS_MI (ISP39_MAIN_SCALE_BASE + 0x004c)
#define ISP39_MAIN_SCALE_IN_CROP_OFFSET (ISP39_MAIN_SCALE_BASE + 0x0050)
#define ISP39_MAIN_SCALE_CTRL_SHD (ISP39_MAIN_SCALE_BASE + 0x0080)
#define ISP39_MAIN_SCALE_SRC_SIZE_SHD (ISP39_MAIN_SCALE_BASE + 0x0088)
#define ISP39_MAIN_SCALE_DST_SIZE_SHD (ISP39_MAIN_SCALE_BASE + 0x008c)
#define ISP39_MAIN_SCALE_HY_FAC_SHD (ISP39_MAIN_SCALE_BASE + 0x0090)
#define ISP39_MAIN_SCALE_HC_FAC_SHD (ISP39_MAIN_SCALE_BASE + 0x0094)
#define ISP39_MAIN_SCALE_VY_FAC_SHD (ISP39_MAIN_SCALE_BASE + 0x0098)
#define ISP39_MAIN_SCALE_VC_FAC_SHD (ISP39_MAIN_SCALE_BASE + 0x009c)
#define ISP39_MAIN_SCALE_HY_OFFS_SHD (ISP39_MAIN_SCALE_BASE + 0x00a0)
#define ISP39_MAIN_SCALE_HC_OFFS_SHD (ISP39_MAIN_SCALE_BASE + 0x00a4)
#define ISP39_MAIN_SCALE_PHASE_HY_SHD (ISP39_MAIN_SCALE_BASE + 0x00b0)
#define ISP39_MAIN_SCALE_PHASE_HC_SHD (ISP39_MAIN_SCALE_BASE + 0x00b4)
#define ISP39_MAIN_SCALE_PHASE_VY_SHD (ISP39_MAIN_SCALE_BASE + 0x00b8)
#define ISP39_MAIN_SCALE_PHASE_VC_SHD (ISP39_MAIN_SCALE_BASE + 0x00bc)
#define ISP39_MAIN_SCALE_HY_SIZE_SHD (ISP39_MAIN_SCALE_BASE + 0x00c0)
#define ISP39_MAIN_SCALE_HC_SIZE_SHD (ISP39_MAIN_SCALE_BASE + 0x00c4)
#define ISP39_MAIN_SCALE_HY_OFFS_MI_SHD (ISP39_MAIN_SCALE_BASE + 0x00c8)
#define ISP39_MAIN_SCALE_HC_OFFS_MI_SHD (ISP39_MAIN_SCALE_BASE + 0x00cc)
#define ISP39_MAIN_SCALE_IN_CROP_OFFSET_SHD (ISP39_MAIN_SCALE_BASE + 0x00d0)
#define ISP32_BP_RESIZE_BASE 0x00000E00
#define ISP32_BP_RESIZE_CTRL (ISP32_BP_RESIZE_BASE + 0x00000)
#define ISP32_BP_RESIZE_SCALE_HY (ISP32_BP_RESIZE_BASE + 0x00004)
@@ -425,6 +474,25 @@
#define ISP32_SELF_SCALE_HC_OFFS_MI_SHD (ISP32_SELF_SCALE_BASE + 0x00cc)
#define ISP32_SELF_SCALE_IN_CROP_OFFSET_SHD (ISP32_SELF_SCALE_BASE + 0x00d0)
#define ISP39_LDCV_BASE 0x00001100
#define ISP39_LDCV_CTRL (ISP39_LDCV_BASE + 0x00000)
#define ISP39_LDCV_BIC_TABLE0 (ISP39_LDCV_BASE + 0x00004)
#define ISP39_LDCV_BIC_TABLE1 (ISP39_LDCV_BASE + 0x00008)
#define ISP39_LDCV_BIC_TABLE2 (ISP39_LDCV_BASE + 0x0000c)
#define ISP39_LDCV_BIC_TABLE3 (ISP39_LDCV_BASE + 0x00010)
#define ISP39_LDCV_BIC_TABLE4 (ISP39_LDCV_BASE + 0x00014)
#define ISP39_LDCV_BIC_TABLE5 (ISP39_LDCV_BASE + 0x00018)
#define ISP39_LDCV_BIC_TABLE6 (ISP39_LDCV_BASE + 0x0001c)
#define ISP39_LDCV_BIC_TABLE7 (ISP39_LDCV_BASE + 0x00020)
#define ISP39_LDCV_BIC_TABLE8 (ISP39_LDCV_BASE + 0x00024)
#define ISP39_LDCV_WR_ADDR (ISP39_LDCV_BASE + 0x00028)
#define ISP39_LDCV_WR_STRIDE (ISP39_LDCV_BASE + 0x0002c)
#define ISP39_LDCV_LAST_OFFSET (ISP39_LDCV_BASE + 0x00030)
#define ISP39_LDCV_SCL_WR_ADDR (ISP39_LDCV_BASE + 0x00034)
#define ISP39_LDCV_SCL_WR_STRIDE (ISP39_LDCV_BASE + 0x00038)
#define ISP39_LDCV_OUT_SIZE (ISP39_LDCV_BASE + 0x0003c)
#define ISP39_LDCV_WR_C_ADDR (ISP39_LDCV_BASE + 0x00040)
#define ISP3X_MI_BASE 0x00001400
#define ISP3X_MI_WR_CTRL (ISP3X_MI_BASE + 0x00000)
#define ISP3X_MI_WR_INIT (ISP3X_MI_BASE + 0x00004)
@@ -601,6 +669,7 @@
#define ISP3X_MI_LUT_LDCH_RD_V_SIZE (ISP3X_MI_BASE + 0x0055C)
#define ISP3X_MI_DBR_WR_BASE (ISP3X_MI_BASE + 0x00560)
#define ISP3X_MI_DBR_WR_SIZE (ISP3X_MI_BASE + 0x00564)
#define ISP39_W3A_WR_SIZE (ISP3X_MI_BASE + 0x00564)
#define ISP3X_MI_DBR_WR_LENGTH (ISP3X_MI_BASE + 0x00568)
#define ISP3X_MI_DBR_WR_BASE_SHD (ISP3X_MI_BASE + 0x0056C)
#define ISP3X_MI_DBR_RD_BASE (ISP3X_MI_BASE + 0x00570)
@@ -689,6 +758,18 @@
#define ISP3X_CSI2RX_ISP_LINECNT_RO (ISP3X_CSI2RX_BASE + 0x000b0)
#define ISP3X_CSI2RX_VERSION (ISP3X_CSI2RX_BASE + 0x000fc)
#define ISP39_YUVME_BASE 0x00002100
#define ISP39_YUVME_CTRL (ISP39_YUVME_BASE + 0x00000)
#define ISP39_YUVME_PARA0 (ISP39_YUVME_BASE + 0x00004)
#define ISP39_YUVME_PARA1 (ISP39_YUVME_BASE + 0x00008)
#define ISP39_YUVME_PARA2 (ISP39_YUVME_BASE + 0x0000c)
#define ISP39_YUVME_SIGMA0 (ISP39_YUVME_BASE + 0x00010)
#define ISP39_YUVME_SIGMA1 (ISP39_YUVME_BASE + 0x00014)
#define ISP39_YUVME_SIGMA2 (ISP39_YUVME_BASE + 0x00018)
#define ISP39_YUVME_SIGMA3 (ISP39_YUVME_BASE + 0x0001c)
#define ISP39_YUVME_SIGMA4 (ISP39_YUVME_BASE + 0x00020)
#define ISP39_YUVME_SIGMA5 (ISP39_YUVME_BASE + 0x00024)
#define ISP3X_LSC_BASE 0x00002200
#define ISP3X_LSC_CTRL (ISP3X_LSC_BASE + 0x00000)
#define ISP3X_LSC_R_TABLE_ADDR (ISP3X_LSC_BASE + 0x00004)
@@ -752,6 +833,30 @@
#define ISP32_DEBAYER_C_FILTER_IIR_0 (ISP3X_DEBAYER_BASE + 0x00030)
#define ISP32_DEBAYER_C_FILTER_IIR_1 (ISP3X_DEBAYER_BASE + 0x00034)
#define ISP32_DEBAYER_C_FILTER_BF (ISP3X_DEBAYER_BASE + 0x00038)
#define ISP39_DEBAYER_LUMA_DX (ISP3X_DEBAYER_BASE + 0x00004)
#define ISP39_DEBAYER_G_INTERP (ISP3X_DEBAYER_BASE + 0x00010)
#define ISP39_DEBAYER_G_INTERP_FILTER1 (ISP3X_DEBAYER_BASE + 0x00014)
#define ISP39_DEBAYER_G_INTERP_FILTER2 (ISP3X_DEBAYER_BASE + 0x00018)
#define ISP39_DEBAYER_G_INTERP_OFFSET_ALPHA (ISP3X_DEBAYER_BASE + 0x0001c)
#define ISP39_DEBAYER_G_INTERP_DRCT_OFFSET0 (ISP3X_DEBAYER_BASE + 0x00020)
#define ISP39_DEBAYER_G_INTERP_DRCT_OFFSET1 (ISP3X_DEBAYER_BASE + 0x00024)
#define ISP39_DEBAYER_G_INTERP_DRCT_OFFSET2 (ISP3X_DEBAYER_BASE + 0x00028)
#define ISP39_DEBAYER_G_INTERP_DRCT_OFFSET3 (ISP3X_DEBAYER_BASE + 0x0002c)
#define ISP39_DEBAYER_G_FILTER_MODE_OFFSET (ISP3X_DEBAYER_BASE + 0x00050)
#define ISP39_DEBAYER_G_FILTER_FILTER (ISP3X_DEBAYER_BASE + 0x00054)
#define ISP39_DEBAYER_G_FILTER_VSIGMA0 (ISP3X_DEBAYER_BASE + 0x00058)
#define ISP39_DEBAYER_G_FILTER_VSIGMA1 (ISP3X_DEBAYER_BASE + 0x0005c)
#define ISP39_DEBAYER_G_FILTER_VSIGMA2 (ISP3X_DEBAYER_BASE + 0x00060)
#define ISP39_DEBAYER_G_FILTER_VSIGMA3 (ISP3X_DEBAYER_BASE + 0x00064)
#define ISP39_DEBAYER_C_FILTER_GUIDE_GAUS (ISP3X_DEBAYER_BASE + 0x00070)
#define ISP39_DEBAYER_C_FILTER_CE_GAUS (ISP3X_DEBAYER_BASE + 0x00074)
#define ISP39_DEBAYER_C_FILTER_ALPHA_GAUS (ISP3X_DEBAYER_BASE + 0x00078)
#define ISP39_DEBAYER_C_FILTER_LOG_OFFSET (ISP3X_DEBAYER_BASE + 0x0007c)
#define ISP39_DEBAYER_C_FILTER_ALPHA (ISP3X_DEBAYER_BASE + 0x00080)
#define ISP39_DEBAYER_C_FILTER_EDGE (ISP3X_DEBAYER_BASE + 0x00084)
#define ISP39_DEBAYER_C_FILTER_IIR_0 (ISP3X_DEBAYER_BASE + 0x00088)
#define ISP39_DEBAYER_C_FILTER_IIR_1 (ISP3X_DEBAYER_BASE + 0x0008c)
#define ISP39_DEBAYER_C_FILTER_BF (ISP3X_DEBAYER_BASE + 0x00090)
#define ISP3X_CAC_BASE 0x00002600
#define ISP3X_CAC_CTRL (ISP3X_CAC_BASE + 0x00000)
@@ -846,6 +951,38 @@
#define ISP32_YNR_NLM_COE (ISP3X_YNR_BASE + 0x000f4)
#define ISP32_YNR_NLM_WEIGHT (ISP3X_YNR_BASE + 0x000f8)
#define ISP32_YNR_NLM_NR_WEIGHT (ISP3X_YNR_BASE + 0x000fc)
#define ISP39_YNR_GAUSS_COEFF (ISP3X_YNR_BASE + 0x00030)
#define ISP39_YNR_LOW_GAIN_ADJ_0_3 (ISP3X_YNR_BASE + 0x00034)
#define ISP39_YNR_LOW_GAIN_ADJ_4_7 (ISP3X_YNR_BASE + 0x00038)
#define ISP39_YNR_LOW_GAIN_ADJ_8 (ISP3X_YNR_BASE + 0x0003C)
#define ISP39_YNR_SGM_DX_0_1 (ISP3X_YNR_BASE + 0x00040)
#define ISP39_YNR_SGM_DX_2_3 (ISP3X_YNR_BASE + 0x00044)
#define ISP39_YNR_SGM_DX_4_5 (ISP3X_YNR_BASE + 0x00048)
#define ISP39_YNR_SGM_DX_6_7 (ISP3X_YNR_BASE + 0x0004c)
#define ISP39_YNR_SGM_DX_8_9 (ISP3X_YNR_BASE + 0x00050)
#define ISP39_YNR_SGM_DX_10_11 (ISP3X_YNR_BASE + 0x00054)
#define ISP39_YNR_SGM_DX_12_13 (ISP3X_YNR_BASE + 0x00058)
#define ISP39_YNR_SGM_DX_14_15 (ISP3X_YNR_BASE + 0x0005c)
#define ISP39_YNR_SGM_DX_16 (ISP3X_YNR_BASE + 0x00060)
#define ISP39_YNR_LSGM_Y_0_1 (ISP3X_YNR_BASE + 0x00070)
#define ISP39_YNR_LSGM_Y_2_3 (ISP3X_YNR_BASE + 0x00074)
#define ISP39_YNR_LSGM_Y_4_5 (ISP3X_YNR_BASE + 0x00078)
#define ISP39_YNR_LSGM_Y_6_7 (ISP3X_YNR_BASE + 0x0007c)
#define ISP39_YNR_LSGM_Y_8_9 (ISP3X_YNR_BASE + 0x00080)
#define ISP39_YNR_LSGM_Y_10_11 (ISP3X_YNR_BASE + 0x00084)
#define ISP39_YNR_LSGM_Y_12_13 (ISP3X_YNR_BASE + 0x00088)
#define ISP39_YNR_LSGM_Y_14_15 (ISP3X_YNR_BASE + 0x0008c)
#define ISP39_YNR_LSGM_Y_16 (ISP3X_YNR_BASE + 0x00090)
#define ISP39_YNR_RNR_STRENGTH03 (ISP3X_YNR_BASE + 0x000d0)
#define ISP39_YNR_RNR_STRENGTH47 (ISP3X_YNR_BASE + 0x000d4)
#define ISP39_YNR_RNR_STRENGTH8B (ISP3X_YNR_BASE + 0x000d8)
#define ISP39_YNR_RNR_STRENGTHCF (ISP3X_YNR_BASE + 0x000dc)
#define ISP39_YNR_RNR_STRENGTH16 (ISP3X_YNR_BASE + 0x000e0)
#define ISP39_YNR_NLM_STRONG_EDGE (ISP3X_YNR_BASE + 0x000ec)
#define ISP39_YNR_NLM_SIGMA_GAIN (ISP3X_YNR_BASE + 0x000f0)
#define ISP39_YNR_NLM_COE (ISP3X_YNR_BASE + 0x000f4)
#define ISP39_YNR_NLM_WEIGHT (ISP3X_YNR_BASE + 0x000f8)
#define ISP39_YNR_NLM_NR_WEIGHT (ISP3X_YNR_BASE + 0x000fc)
#define ISP3X_CNR_BASE 0x00002800
#define ISP3X_CNR_CTRL (ISP3X_CNR_BASE + 0x00000)
@@ -878,6 +1015,17 @@
#define ISP32_CNR_SIGMA2 (ISP3X_CNR_BASE + 0x00038)
#define ISP32_CNR_SIGMA3 (ISP3X_CNR_BASE + 0x0003c)
#define ISP32_CNR_IIR_GLOBAL_GAIN (ISP3X_CNR_BASE + 0x00040)
#define ISP39_CNR_WGT_SIGMA0 (ISP3X_CNR_BASE + 0x00044)
#define ISP39_CNR_WGT_SIGMA1 (ISP3X_CNR_BASE + 0x00048)
#define ISP39_CNR_WGT_SIGMA2 (ISP3X_CNR_BASE + 0x0004c)
#define ISP39_CNR_WGT_SIGMA3 (ISP3X_CNR_BASE + 0x00050)
#define ISP39_CNR_GAUS_X_SIGMAR0 (ISP3X_CNR_BASE + 0x00054)
#define ISP39_CNR_GAUS_X_SIGMAR1 (ISP3X_CNR_BASE + 0x00058)
#define ISP39_CNR_GAUS_X_SIGMAR2 (ISP3X_CNR_BASE + 0x0005c)
#define ISP39_CNR_GAUS_Y_SIGMAR0 (ISP3X_CNR_BASE + 0x00060)
#define ISP39_CNR_GAUS_Y_SIGMAR1 (ISP3X_CNR_BASE + 0x00064)
#define ISP39_CNR_GAUS_Y_SIGMAR2 (ISP3X_CNR_BASE + 0x00068)
#define ISP39_CNR_GAUS_Y_SIGMAR3 (ISP3X_CNR_BASE + 0x0006c)
#define ISP3X_SHARP_BASE 0x00002900
#define ISP3X_SHARP_EN (ISP3X_SHARP_BASE + 0x00000)
@@ -919,6 +1067,37 @@
#define ISP32L_SHARP_CLIP_NEG_0 (ISP3X_SHARP_BASE + 0x00090)
#define ISP32L_SHARP_CLIP_NEG_1 (ISP3X_SHARP_BASE + 0x00094)
#define ISP32L_SHARP_CLIP_NEG_2 (ISP3X_SHARP_BASE + 0x00098)
#define ISP39_SHARP_ALPHA (ISP3X_SHARP_BASE + 0x00004)
#define ISP39_SHARP_LOCAL_STRG_0 (ISP3X_SHARP_BASE + 0x00028)
#define ISP39_SHARP_LOCAL_STRG_1 (ISP3X_SHARP_BASE + 0x0002c)
#define ISP39_SHARP_LOCAL_STRG_2 (ISP3X_SHARP_BASE + 0x00030)
#define ISP39_SHARP_POS_CLIP_0 (ISP3X_SHARP_BASE + 0x00034)
#define ISP39_SHARP_POS_CLIP_1 (ISP3X_SHARP_BASE + 0x00038)
#define ISP39_SHARP_POS_CLIP_2 (ISP3X_SHARP_BASE + 0x0003c)
#define ISP39_SHARP_DETAILBF_COEF (ISP3X_SHARP_BASE + 0x00044)
#define ISP3X_SHARP_IMGLPF_COEF_0 (ISP3X_SHARP_BASE + 0x00048)
#define ISP3X_SHARP_IMGLPF_COEF_1 (ISP3X_SHARP_BASE + 0x0004C)
#define ISP39_SHARP_CLIP_NEG_0 (ISP3X_SHARP_BASE + 0x0008c)
#define ISP39_SHARP_CLIP_NEG_1 (ISP3X_SHARP_BASE + 0x00090)
#define ISP39_SHARP_CLIP_NEG_2 (ISP3X_SHARP_BASE + 0x00094)
#define ISP39_SHARP_TEXTURE0 (ISP3X_SHARP_BASE + 0x000a0)
#define ISP39_SHARP_TEXTURE1 (ISP3X_SHARP_BASE + 0x000a4)
#define ISP39_SHARP_TEXTURE_LUT0 (ISP3X_SHARP_BASE + 0x000a8)
#define ISP39_SHARP_TEXTURE_LUT1 (ISP3X_SHARP_BASE + 0x000ac)
#define ISP39_SHARP_TEXTURE_LUT2 (ISP3X_SHARP_BASE + 0x000b0)
#define ISP39_SHARP_TEXTURE_LUT3 (ISP3X_SHARP_BASE + 0x000b4)
#define ISP39_SHARP_TEXTURE_LUT4 (ISP3X_SHARP_BASE + 0x000b8)
#define ISP39_SHARP_TEXTURE_LUT5 (ISP3X_SHARP_BASE + 0x000bc)
#define ISP39_SHARP_TEXTURE2 (ISP3X_SHARP_BASE + 0x000c0)
#define ISP39_SHARP_DETAIL_STRG_LUT0 (ISP3X_SHARP_BASE + 0x000c4)
#define ISP39_SHARP_DETAIL_STRG_LUT1 (ISP3X_SHARP_BASE + 0x000c8)
#define ISP39_SHARP_DETAIL_STRG_LUT2 (ISP3X_SHARP_BASE + 0x000cc)
#define ISP39_SHARP_DETAIL_STRG_LUT3 (ISP3X_SHARP_BASE + 0x000d0)
#define ISP39_SHARP_DETAIL_STRG_LUT4 (ISP3X_SHARP_BASE + 0x000d4)
#define ISP39_SHARP_DETAIL_STRG_LUT5 (ISP3X_SHARP_BASE + 0x000d8)
#define ISP39_SHARP_DETAIL_STRG_LUT6 (ISP3X_SHARP_BASE + 0x000dc)
#define ISP39_SHARP_DETAIL_STRG_LUT7 (ISP3X_SHARP_BASE + 0x000e0)
#define ISP39_SHARP_DETAIL_STRG_LUT8 (ISP3X_SHARP_BASE + 0x000e4)
#define ISP3X_BAY3D_BASE 0x00002C00
#define ISP3X_BAY3D_CTRL (ISP3X_BAY3D_BASE + 0x00000)
@@ -984,6 +1163,144 @@
#define ISP32_BAY3D_SIGGAUS (ISP3X_BAY3D_BASE + 0x000F4)
#define ISP32_BAY3D_WRMI (ISP3X_BAY3D_BASE + 0x000F8)
#define ISP32_BAY3D_RDMI (ISP3X_BAY3D_BASE + 0x000FC)
#define ISP39_BAY3D_CTRL1 (ISP3X_BAY3D_BASE + 0x00004)
#define ISP39_BAY3D_CTRL2 (ISP3X_BAY3D_BASE + 0x00008)
#define ISP39_BAY3D_TRANS0 (ISP3X_BAY3D_BASE + 0x0000c)
#define ISP39_BAY3D_TRANS1 (ISP3X_BAY3D_BASE + 0x00010)
#define ISP39_BAY3D_CURDGAIN (ISP3X_BAY3D_BASE + 0x00014)
#define ISP39_BAY3D_CURSIG_X0 (ISP3X_BAY3D_BASE + 0x00018)
#define ISP39_BAY3D_CURSIG_X1 (ISP3X_BAY3D_BASE + 0x0001c)
#define ISP39_BAY3D_CURSIG_X2 (ISP3X_BAY3D_BASE + 0x00020)
#define ISP39_BAY3D_CURSIG_X3 (ISP3X_BAY3D_BASE + 0x00024)
#define ISP39_BAY3D_CURSIG_X4 (ISP3X_BAY3D_BASE + 0x00028)
#define ISP39_BAY3D_CURSIG_X5 (ISP3X_BAY3D_BASE + 0x0002c)
#define ISP39_BAY3D_CURSIG_X6 (ISP3X_BAY3D_BASE + 0x00030)
#define ISP39_BAY3D_CURSIG_X7 (ISP3X_BAY3D_BASE + 0x00034)
#define ISP39_BAY3D_CURSIG_Y0 (ISP3X_BAY3D_BASE + 0x00038)
#define ISP39_BAY3D_CURSIG_Y1 (ISP3X_BAY3D_BASE + 0x0003c)
#define ISP39_BAY3D_CURSIG_Y2 (ISP3X_BAY3D_BASE + 0x00040)
#define ISP39_BAY3D_CURSIG_Y3 (ISP3X_BAY3D_BASE + 0x00044)
#define ISP39_BAY3D_CURSIG_Y4 (ISP3X_BAY3D_BASE + 0x00048)
#define ISP39_BAY3D_CURSIG_Y5 (ISP3X_BAY3D_BASE + 0x0004c)
#define ISP39_BAY3D_CURSIG_Y6 (ISP3X_BAY3D_BASE + 0x00050)
#define ISP39_BAY3D_CURSIG_Y7 (ISP3X_BAY3D_BASE + 0x00054)
#define ISP39_BAY3D_CURGAIN_OFF (ISP3X_BAY3D_BASE + 0x00058)
#define ISP39_BAY3D_CURSIG_OFF (ISP3X_BAY3D_BASE + 0x0005c)
#define ISP39_BAY3D_CURWTH (ISP3X_BAY3D_BASE + 0x00060)
#define ISP39_BAY3D_CURBFALP (ISP3X_BAY3D_BASE + 0x00064)
#define ISP39_BAY3D_CURWDC0 (ISP3X_BAY3D_BASE + 0x00068)
#define ISP39_BAY3D_CURWDC1 (ISP3X_BAY3D_BASE + 0x0006c)
#define ISP39_BAY3D_CURWDC2 (ISP3X_BAY3D_BASE + 0x00070)
#define ISP39_BAY3D_CURWDY0 (ISP3X_BAY3D_BASE + 0x00074)
#define ISP39_BAY3D_CURWDY1 (ISP3X_BAY3D_BASE + 0x00078)
#define ISP39_BAY3D_CURWDY2 (ISP3X_BAY3D_BASE + 0x0007c)
#define ISP39_BAY3D_IIRDGAIN (ISP3X_BAY3D_BASE + 0x00080)
#define ISP39_BAY3D_IIRSIG_X0 (ISP3X_BAY3D_BASE + 0x00084)
#define ISP39_BAY3D_IIRSIG_X1 (ISP3X_BAY3D_BASE + 0x00088)
#define ISP39_BAY3D_IIRSIG_X2 (ISP3X_BAY3D_BASE + 0x0008c)
#define ISP39_BAY3D_IIRSIG_X3 (ISP3X_BAY3D_BASE + 0x00090)
#define ISP39_BAY3D_IIRSIG_X4 (ISP3X_BAY3D_BASE + 0x00094)
#define ISP39_BAY3D_IIRSIG_X5 (ISP3X_BAY3D_BASE + 0x00098)
#define ISP39_BAY3D_IIRSIG_X6 (ISP3X_BAY3D_BASE + 0x0009c)
#define ISP39_BAY3D_IIRSIG_X7 (ISP3X_BAY3D_BASE + 0x000a0)
#define ISP39_BAY3D_IIRSIG_Y0 (ISP3X_BAY3D_BASE + 0x000a4)
#define ISP39_BAY3D_IIRSIG_Y1 (ISP3X_BAY3D_BASE + 0x000a8)
#define ISP39_BAY3D_IIRSIG_Y2 (ISP3X_BAY3D_BASE + 0x000ac)
#define ISP39_BAY3D_IIRSIG_Y3 (ISP3X_BAY3D_BASE + 0x000b0)
#define ISP39_BAY3D_IIRSIG_Y4 (ISP3X_BAY3D_BASE + 0x000b4)
#define ISP39_BAY3D_IIRSIG_Y5 (ISP3X_BAY3D_BASE + 0x000b8)
#define ISP39_BAY3D_IIRSIG_Y6 (ISP3X_BAY3D_BASE + 0x000bc)
#define ISP39_BAY3D_IIRSIG_Y7 (ISP3X_BAY3D_BASE + 0x000c0)
#define ISP39_BAY3D_IIRGAIN_OFF (ISP3X_BAY3D_BASE + 0x000c4)
#define ISP39_BAY3D_IIRSIG_OFF (ISP3X_BAY3D_BASE + 0x000c8)
#define ISP39_BAY3D_IIRWTH (ISP3X_BAY3D_BASE + 0x000cc)
#define ISP39_BAY3D_IIRWDC0 (ISP3X_BAY3D_BASE + 0x000d0)
#define ISP39_BAY3D_IIRWDC1 (ISP3X_BAY3D_BASE + 0x000d4)
#define ISP39_BAY3D_IIRWDC2 (ISP3X_BAY3D_BASE + 0x000d8)
#define ISP39_BAY3D_IIRWDY0 (ISP3X_BAY3D_BASE + 0x000dc)
#define ISP39_BAY3D_IIRWDY1 (ISP3X_BAY3D_BASE + 0x000e0)
#define ISP39_BAY3D_IIRWDY2 (ISP3X_BAY3D_BASE + 0x000e4)
#define ISP39_BAY3D_BFCOEF (ISP3X_BAY3D_BASE + 0x000e8)
/* BAY3D_3A00 */
#define ISP39_BAY3D_TNRSIG_X0 (ISP3X_BAYNR_BASE + 0x00000)
#define ISP39_BAY3D_TNRSIG_X1 (ISP3X_BAYNR_BASE + 0x00004)
#define ISP39_BAY3D_TNRSIG_X2 (ISP3X_BAYNR_BASE + 0x00008)
#define ISP39_BAY3D_TNRSIG_X3 (ISP3X_BAYNR_BASE + 0x0000c)
#define ISP39_BAY3D_TNRSIG_X4 (ISP3X_BAYNR_BASE + 0x00010)
#define ISP39_BAY3D_TNRSIG_X5 (ISP3X_BAYNR_BASE + 0x00014)
#define ISP39_BAY3D_TNRSIG_X6 (ISP3X_BAYNR_BASE + 0x00018)
#define ISP39_BAY3D_TNRSIG_X7 (ISP3X_BAYNR_BASE + 0x0001c)
#define ISP39_BAY3D_TNRSIG_X8 (ISP3X_BAYNR_BASE + 0x00020)
#define ISP39_BAY3D_TNRSIG_X9 (ISP3X_BAYNR_BASE + 0x00024)
#define ISP39_BAY3D_TNRSIG_Y0 (ISP3X_BAYNR_BASE + 0x00028)
#define ISP39_BAY3D_TNRSIG_Y1 (ISP3X_BAYNR_BASE + 0x0002c)
#define ISP39_BAY3D_TNRSIG_Y2 (ISP3X_BAYNR_BASE + 0x00030)
#define ISP39_BAY3D_TNRSIG_Y3 (ISP3X_BAYNR_BASE + 0x00034)
#define ISP39_BAY3D_TNRSIG_Y4 (ISP3X_BAYNR_BASE + 0x00038)
#define ISP39_BAY3D_TNRSIG_Y5 (ISP3X_BAYNR_BASE + 0x0003c)
#define ISP39_BAY3D_TNRSIG_Y6 (ISP3X_BAYNR_BASE + 0x00040)
#define ISP39_BAY3D_TNRSIG_Y7 (ISP3X_BAYNR_BASE + 0x00044)
#define ISP39_BAY3D_TNRSIG_Y8 (ISP3X_BAYNR_BASE + 0x00048)
#define ISP39_BAY3D_TNRSIG_Y9 (ISP3X_BAYNR_BASE + 0x0004c)
#define ISP39_BAY3D_TNRHIW0 (ISP3X_BAYNR_BASE + 0x00050)
#define ISP39_BAY3D_TNRHIW1 (ISP3X_BAYNR_BASE + 0x00054)
#define ISP39_BAY3D_TNRHIW2 (ISP3X_BAYNR_BASE + 0x00058)
#define ISP39_BAY3D_TNRLOW0 (ISP3X_BAYNR_BASE + 0x0005c)
#define ISP39_BAY3D_TNRLOW1 (ISP3X_BAYNR_BASE + 0x00060)
#define ISP39_BAY3D_TNRLOW2 (ISP3X_BAYNR_BASE + 0x00064)
#define ISP39_BAY3D_TNRGF3 (ISP3X_BAYNR_BASE + 0x00068)
#define ISP39_BAY3D_TNRSIGSCL (ISP3X_BAYNR_BASE + 0x0006c)
#define ISP39_BAY3D_TNRVIIR (ISP3X_BAYNR_BASE + 0x00070)
#define ISP39_BAY3D_TNRLFSCL (ISP3X_BAYNR_BASE + 0x00074)
#define ISP39_BAY3D_TNRLFSCLTH (ISP3X_BAYNR_BASE + 0x00078)
#define ISP39_BAY3D_TNRDSWGTSCL (ISP3X_BAYNR_BASE + 0x0007c)
#define ISP39_BAY3D_TNRWLSTSCL (ISP3X_BAYNR_BASE + 0x00080)
#define ISP39_BAY3D_TNRWGT0SCL0 (ISP3X_BAYNR_BASE + 0x00084)
#define ISP39_BAY3D_TNRWGT1SCL1 (ISP3X_BAYNR_BASE + 0x00088)
#define ISP39_BAY3D_TNRWGT1SCL2 (ISP3X_BAYNR_BASE + 0x0008c)
#define ISP39_BAY3D_TNRWGTOFF (ISP3X_BAYNR_BASE + 0x00090)
#define ISP39_BAY3D_TNRWGT1OFF (ISP3X_BAYNR_BASE + 0x00094)
#define ISP39_BAY3D_TNRSIGORG (ISP3X_BAYNR_BASE + 0x00098)
#define ISP39_BAY3D_TNRWLO_THL (ISP3X_BAYNR_BASE + 0x0009c)
#define ISP39_BAY3D_TNRWLO_THH (ISP3X_BAYNR_BASE + 0x000a0)
#define ISP39_BAY3D_TNRWHI_THL (ISP3X_BAYNR_BASE + 0x000a4)
#define ISP39_BAY3D_TNRWHI_THH (ISP3X_BAYNR_BASE + 0x000a8)
#define ISP39_BAY3D_TNRKEEP (ISP3X_BAYNR_BASE + 0x000ac)
#define ISP39_BAY3D_PIXMAX (ISP3X_BAYNR_BASE + 0x000b0)
#define ISP39_BAY3D_SIGNUMTH (ISP3X_BAYNR_BASE + 0x000b4)
#define ISP39_BAY3D_TNRMO_STR (ISP3X_BAYNR_BASE + 0x000b8)
#define ISP39_BAY3D_SIGSUM (ISP3X_BAYNR_BASE + 0x000d4)
#define ISP39_BAY3D_TNRSIGYO0 (ISP3X_BAYNR_BASE + 0x000d8)
#define ISP39_BAY3D_TNRSIGYO1 (ISP3X_BAYNR_BASE + 0x000dc)
#define ISP39_BAY3D_TNRSIGYO2 (ISP3X_BAYNR_BASE + 0x000e0)
#define ISP39_BAY3D_TNRSIGYO3 (ISP3X_BAYNR_BASE + 0x000e4)
#define ISP39_BAY3D_TNRSIGYO4 (ISP3X_BAYNR_BASE + 0x000e8)
#define ISP39_BAY3D_TNRSIGYO5 (ISP3X_BAYNR_BASE + 0x000ec)
#define ISP39_BAY3D_TNRSIGYO6 (ISP3X_BAYNR_BASE + 0x000f0)
#define ISP39_BAY3D_TNRSIGYO7 (ISP3X_BAYNR_BASE + 0x000f4)
#define ISP39_BAY3D_TNRSIGYO8 (ISP3X_BAYNR_BASE + 0x000f8)
#define ISP39_BAY3D_TNRSIGYO9 (ISP3X_BAYNR_BASE + 0x000fc)
#define ISP39_RGBIR_BASE 0x00002E00
#define ISP39_RGBIR_CTRL (ISP39_RGBIR_BASE + 0x00000)
#define ISP39_RGBIR_THETA (ISP39_RGBIR_BASE + 0x00004)
#define ISP39_RGBIR_DELTA (ISP39_RGBIR_BASE + 0x00008)
#define ISP39_RGBIR_SCALE0 (ISP39_RGBIR_BASE + 0x0000c)
#define ISP39_RGBIR_SCALE1 (ISP39_RGBIR_BASE + 0x00010)
#define ISP39_RGBIR_SCALE2 (ISP39_RGBIR_BASE + 0x00014)
#define ISP39_RGBIR_SCALE3 (ISP39_RGBIR_BASE + 0x00018)
#define ISP39_RGBIR_LUMA_POINT0 (ISP39_RGBIR_BASE + 0x0001c)
#define ISP39_RGBIR_LUMA_POINT1 (ISP39_RGBIR_BASE + 0x00020)
#define ISP39_RGBIR_LUMA_POINT2 (ISP39_RGBIR_BASE + 0x00024)
#define ISP39_RGBIR_LUMA_POINT3 (ISP39_RGBIR_BASE + 0x00028)
#define ISP39_RGBIR_LUMA_POINT4 (ISP39_RGBIR_BASE + 0x0002c)
#define ISP39_RGBIR_LUMA_POINT5 (ISP39_RGBIR_BASE + 0x00030)
#define ISP39_RGBIR_SCALE_MAP0 (ISP39_RGBIR_BASE + 0x00034)
#define ISP39_RGBIR_SCALE_MAP1 (ISP39_RGBIR_BASE + 0x00038)
#define ISP39_RGBIR_SCALE_MAP2 (ISP39_RGBIR_BASE + 0x0003c)
#define ISP39_RGBIR_SCALE_MAP3 (ISP39_RGBIR_BASE + 0x00040)
#define ISP39_RGBIR_SCALE_MAP4 (ISP39_RGBIR_BASE + 0x00044)
#define ISP39_RGBIR_SCALE_MAP5 (ISP39_RGBIR_BASE + 0x00048)
#define ISP3X_GIC_BASE 0x00002F00
#define ISP3X_GIC_CONTROL (ISP3X_GIC_BASE + 0x00000)
@@ -1034,6 +1351,91 @@
#define ISP32_BLS_ISP_OB_PREDGAIN (ISP3X_BLS_BASE + 0x0006c)
#define ISP32_BLS_ISP_OB_MAX (ISP3X_BLS_BASE + 0x00070)
#define ISP39_EXPD_BASE 0x00003100
#define ISP39_EXPD_K15 (ISP39_EXPD_BASE + 0x00000)
#define ISP39_EXPD_K16 (ISP39_EXPD_BASE + 0x00004)
#define ISP39_EXPD_K17 (ISP39_EXPD_BASE + 0x00008)
#define ISP39_EXPD_K18 (ISP39_EXPD_BASE + 0x0000c)
#define ISP39_EXPD_K19 (ISP39_EXPD_BASE + 0x00010)
#define ISP39_EXPD_K20 (ISP39_EXPD_BASE + 0x00014)
#define ISP39_EXPD_K21 (ISP39_EXPD_BASE + 0x00018)
#define ISP39_EXPD_K22 (ISP39_EXPD_BASE + 0x0001c)
#define ISP39_EXPD_K23 (ISP39_EXPD_BASE + 0x00020)
#define ISP39_EXPD_K24 (ISP39_EXPD_BASE + 0x00024)
#define ISP39_EXPD_K25 (ISP39_EXPD_BASE + 0x00028)
#define ISP39_EXPD_K26 (ISP39_EXPD_BASE + 0x0002c)
#define ISP39_EXPD_K27 (ISP39_EXPD_BASE + 0x00030)
#define ISP39_EXPD_K28 (ISP39_EXPD_BASE + 0x00034)
#define ISP39_EXPD_K29 (ISP39_EXPD_BASE + 0x00038)
#define ISP39_EXPD_K30 (ISP39_EXPD_BASE + 0x0003c)
#define ISP39_EXPD_K31 (ISP39_EXPD_BASE + 0x00040)
#define ISP39_EXPD_IMAX (ISP39_EXPD_BASE + 0x00044)
#define ISP39_EXPD_OMAX (ISP39_EXPD_BASE + 0x00048)
#define ISP39_EXPD_CTRL (ISP39_EXPD_BASE + 0x00100)
#define ISP39_EXPD_X00_01 (ISP39_EXPD_BASE + 0x00104)
#define ISP39_EXPD_X02_03 (ISP39_EXPD_BASE + 0x00108)
#define ISP39_EXPD_X04_05 (ISP39_EXPD_BASE + 0x0010C)
#define ISP39_EXPD_X06_07 (ISP39_EXPD_BASE + 0x00110)
#define ISP39_EXPD_X08_09 (ISP39_EXPD_BASE + 0x00114)
#define ISP39_EXPD_X10_11 (ISP39_EXPD_BASE + 0x00118)
#define ISP39_EXPD_X12_13 (ISP39_EXPD_BASE + 0x0011C)
#define ISP39_EXPD_X14_15 (ISP39_EXPD_BASE + 0x00120)
#define ISP39_EXPD_X16_17 (ISP39_EXPD_BASE + 0x00124)
#define ISP39_EXPD_X18_19 (ISP39_EXPD_BASE + 0x00128)
#define ISP39_EXPD_X20_21 (ISP39_EXPD_BASE + 0x0012c)
#define ISP39_EXPD_X22_23 (ISP39_EXPD_BASE + 0x00130)
#define ISP39_EXPD_X24_25 (ISP39_EXPD_BASE + 0x00134)
#define ISP39_EXPD_X26_27 (ISP39_EXPD_BASE + 0x00138)
#define ISP39_EXPD_X28_29 (ISP39_EXPD_BASE + 0x0013c)
#define ISP39_EXPD_X30_31 (ISP39_EXPD_BASE + 0x00140)
#define ISP39_EXPD_Y0 (ISP39_EXPD_BASE + 0x00144)
#define ISP39_EXPD_Y1 (ISP39_EXPD_BASE + 0x00148)
#define ISP39_EXPD_Y2 (ISP39_EXPD_BASE + 0x0014c)
#define ISP39_EXPD_Y3 (ISP39_EXPD_BASE + 0x00150)
#define ISP39_EXPD_Y4 (ISP39_EXPD_BASE + 0x00154)
#define ISP39_EXPD_Y5 (ISP39_EXPD_BASE + 0x00158)
#define ISP39_EXPD_Y6 (ISP39_EXPD_BASE + 0x0015c)
#define ISP39_EXPD_Y7 (ISP39_EXPD_BASE + 0x00160)
#define ISP39_EXPD_Y8 (ISP39_EXPD_BASE + 0x00164)
#define ISP39_EXPD_Y9 (ISP39_EXPD_BASE + 0x00168)
#define ISP39_EXPD_Y10 (ISP39_EXPD_BASE + 0x0016c)
#define ISP39_EXPD_Y11 (ISP39_EXPD_BASE + 0x00170)
#define ISP39_EXPD_Y12 (ISP39_EXPD_BASE + 0x00174)
#define ISP39_EXPD_Y13 (ISP39_EXPD_BASE + 0x00178)
#define ISP39_EXPD_Y14 (ISP39_EXPD_BASE + 0x0017c)
#define ISP39_EXPD_Y15 (ISP39_EXPD_BASE + 0x00180)
#define ISP39_EXPD_Y16 (ISP39_EXPD_BASE + 0x00184)
#define ISP39_EXPD_Y17 (ISP39_EXPD_BASE + 0x00188)
#define ISP39_EXPD_Y18 (ISP39_EXPD_BASE + 0x0018c)
#define ISP39_EXPD_Y19 (ISP39_EXPD_BASE + 0x00190)
#define ISP39_EXPD_Y20 (ISP39_EXPD_BASE + 0x00194)
#define ISP39_EXPD_Y21 (ISP39_EXPD_BASE + 0x00198)
#define ISP39_EXPD_Y22 (ISP39_EXPD_BASE + 0x0019c)
#define ISP39_EXPD_Y23 (ISP39_EXPD_BASE + 0x001a0)
#define ISP39_EXPD_Y24 (ISP39_EXPD_BASE + 0x001a4)
#define ISP39_EXPD_Y25 (ISP39_EXPD_BASE + 0x001a8)
#define ISP39_EXPD_Y26 (ISP39_EXPD_BASE + 0x001ac)
#define ISP39_EXPD_Y27 (ISP39_EXPD_BASE + 0x001b0)
#define ISP39_EXPD_Y28 (ISP39_EXPD_BASE + 0x001b4)
#define ISP39_EXPD_Y29 (ISP39_EXPD_BASE + 0x001b8)
#define ISP39_EXPD_Y30 (ISP39_EXPD_BASE + 0x001bc)
#define ISP39_EXPD_Y31 (ISP39_EXPD_BASE + 0x001c0)
#define ISP39_EXPD_K0 (ISP39_EXPD_BASE + 0x001c4)
#define ISP39_EXPD_K1 (ISP39_EXPD_BASE + 0x001c8)
#define ISP39_EXPD_K2 (ISP39_EXPD_BASE + 0x001cc)
#define ISP39_EXPD_K3 (ISP39_EXPD_BASE + 0x001d0)
#define ISP39_EXPD_K4 (ISP39_EXPD_BASE + 0x001d4)
#define ISP39_EXPD_K5 (ISP39_EXPD_BASE + 0x001d8)
#define ISP39_EXPD_K6 (ISP39_EXPD_BASE + 0x001dc)
#define ISP39_EXPD_K7 (ISP39_EXPD_BASE + 0x001e0)
#define ISP39_EXPD_K8 (ISP39_EXPD_BASE + 0x001e4)
#define ISP39_EXPD_K9 (ISP39_EXPD_BASE + 0x001e8)
#define ISP39_EXPD_K10 (ISP39_EXPD_BASE + 0x001ec)
#define ISP39_EXPD_K11 (ISP39_EXPD_BASE + 0x001f0)
#define ISP39_EXPD_K12 (ISP39_EXPD_BASE + 0x001f4)
#define ISP39_EXPD_K13 (ISP39_EXPD_BASE + 0x001f8)
#define ISP39_EXPD_K14 (ISP39_EXPD_BASE + 0x001fc)
#define ISP32_EXPD_BASE 0x00003200
#define ISP32_EXPD_CTRL (ISP32_EXPD_BASE + 0x00000)
#define ISP32_EXPD_X00_01 (ISP32_EXPD_BASE + 0x00004)
@@ -1296,6 +1698,20 @@
#define ISP3X_DRC_IIRWG_GAIN (ISP3X_DRC_BASE + 0x0008c)
#define ISP32_DRC_LUM3X2_CTRL (ISP3X_DRC_BASE + 0x00090)
#define ISP32_DRC_LUM3X2_GAS (ISP3X_DRC_BASE + 0x00094)
#define ISP39_DRC_BILAT0 (ISP3X_DRC_BASE + 0x0000c)
#define ISP39_DRC_BILAT1 (ISP3X_DRC_BASE + 0x00010)
#define ISP39_DRC_BILAT2 (ISP3X_DRC_BASE + 0x00014)
#define ISP39_DRC_BILAT3 (ISP3X_DRC_BASE + 0x00018)
#define ISP39_DRC_BILAT4 (ISP3X_DRC_BASE + 0x0001c)
#define ISP39_DRC_SFTHD_Y0 (ISP3X_DRC_BASE + 0x00090)
#define ISP39_DRC_SFTHD_Y1 (ISP3X_DRC_BASE + 0x00094)
#define ISP39_DRC_SFTHD_Y2 (ISP3X_DRC_BASE + 0x00098)
#define ISP39_DRC_SFTHD_Y3 (ISP3X_DRC_BASE + 0x0009c)
#define ISP39_DRC_SFTHD_Y4 (ISP3X_DRC_BASE + 0x000a0)
#define ISP39_DRC_SFTHD_Y5 (ISP3X_DRC_BASE + 0x000a4)
#define ISP39_DRC_SFTHD_Y6 (ISP3X_DRC_BASE + 0x000a8)
#define ISP39_DRC_SFTHD_Y7 (ISP3X_DRC_BASE + 0x000ac)
#define ISP39_DRC_SFTHD_Y8 (ISP3X_DRC_BASE + 0x000b0)
#define ISP3X_BAYNR_BASE 0x00003A00
#define ISP3X_BAYNR_CTRL (ISP3X_BAYNR_BASE + 0x00000)
@@ -1348,6 +1764,7 @@
#define ISP32_LDCH_BIC_TABLE6 (ISP3X_LDCH_BASE + 0x0001c)
#define ISP32_LDCH_BIC_TABLE7 (ISP3X_LDCH_BASE + 0x00020)
#define ISP32_LDCH_BIC_TABLE8 (ISP3X_LDCH_BASE + 0x00024)
#define ISP39_LDCH_OUT_SIZE (ISP3X_LDCH_BASE + 0x00028)
#define ISP3X_DHAZ_BASE 0x00003C00
#define ISP3X_DHAZ_CTRL (ISP3X_DHAZ_BASE + 0x00000)
@@ -1455,6 +1872,64 @@
#define ISP32_DHAZ_ENH_LUMA5 (ISP3X_DHAZ_BASE + 0x001a4)
#define ISP32L_DHAZ_STAB_FRAME (ISP3X_DHAZ_BASE + 0x001f8)
#define ISP32L_DHAZ_PRE_FRAME (ISP3X_DHAZ_BASE + 0x001fc)
#define ISP39_DHAZ_ENHANCE (ISP3X_DHAZ_BASE + 0x00014)
#define ISP39_DHAZ_IIR0 (ISP3X_DHAZ_BASE + 0x00018)
#define ISP39_DHAZ_IIR1 (ISP3X_DHAZ_BASE + 0x0001c)
#define ISP39_DHAZ_SOFT_CFG0 (ISP3X_DHAZ_BASE + 0x00020)
#define ISP39_DHAZ_SOFT_CFG1 (ISP3X_DHAZ_BASE + 0x00024)
#define ISP39_DHAZ_BF_SIGMA (ISP3X_DHAZ_BASE + 0x00028)
#define ISP39_DHAZ_BF_WET (ISP3X_DHAZ_BASE + 0x0002c)
#define ISP39_DHAZ_ENH_CURVE0 (ISP3X_DHAZ_BASE + 0x00030)
#define ISP39_DHAZ_ENH_CURVE1 (ISP3X_DHAZ_BASE + 0x00034)
#define ISP39_DHAZ_ENH_CURVE2 (ISP3X_DHAZ_BASE + 0x00038)
#define ISP39_DHAZ_ENH_CURVE3 (ISP3X_DHAZ_BASE + 0x0003c)
#define ISP39_DHAZ_ENH_CURVE4 (ISP3X_DHAZ_BASE + 0x00040)
#define ISP39_DHAZ_ENH_CURVE5 (ISP3X_DHAZ_BASE + 0x00044)
#define ISP39_DHAZ_GAUS (ISP3X_DHAZ_BASE + 0x00048)
#define ISP39_DHAZ_ENH_LUMA0 (ISP3X_DHAZ_BASE + 0x0004c)
#define ISP39_DHAZ_ENH_LUMA1 (ISP3X_DHAZ_BASE + 0x00050)
#define ISP39_DHAZ_ENH_LUMA2 (ISP3X_DHAZ_BASE + 0x00054)
#define ISP39_DHAZ_ENH_LUMA3 (ISP3X_DHAZ_BASE + 0x00058)
#define ISP39_DHAZ_ENH_LUMA4 (ISP3X_DHAZ_BASE + 0x0005c)
#define ISP39_DHAZ_ENH_LUMA5 (ISP3X_DHAZ_BASE + 0x00060)
#define ISP39_DHAZ_ADP_WR0 (ISP3X_DHAZ_BASE + 0x00064)
#define ISP39_DHAZ_ADP_WR1 (ISP3X_DHAZ_BASE + 0x00068)
#define ISP39_DHAZ_DDR_SIZE (ISP3X_DHAZ_BASE + 0x0006c)
#define ISP39_DHAZ_GAIN_IDX0 (ISP3X_DHAZ_BASE + 0x00080)
#define ISP39_DHAZ_GAIN_IDX1 (ISP3X_DHAZ_BASE + 0x00084)
#define ISP39_DHAZ_GAIN_IDX2 (ISP3X_DHAZ_BASE + 0x00088)
#define ISP39_DHAZ_GAIN_IDX3 (ISP3X_DHAZ_BASE + 0x0008c)
#define ISP39_DHAZ_GAIN_LUT0 (ISP3X_DHAZ_BASE + 0x00090)
#define ISP39_DHAZ_GAIN_LUT1 (ISP3X_DHAZ_BASE + 0x00094)
#define ISP39_DHAZ_GAIN_LUT2 (ISP3X_DHAZ_BASE + 0x00098)
#define ISP39_DHAZ_GAIN_LUT3 (ISP3X_DHAZ_BASE + 0x0009c)
#define ISP39_DHAZ_GAIN_LUT4 (ISP3X_DHAZ_BASE + 0x000a0)
#define ISP39_DHAZ_GAIN_LUT5 (ISP3X_DHAZ_BASE + 0x000a4)
#define ISP39_DHAZ_GAIN_FUSE (ISP3X_DHAZ_BASE + 0x000a8)
#define ISP39_DHAZ_ADP_HF (ISP3X_DHAZ_BASE + 0x00100)
#define ISP39_DHAZ_BLOCK_SIZE (ISP3X_DHAZ_BASE + 0x00104)
#define ISP39_DHAZ_THUMB_SIZE (ISP3X_DHAZ_BASE + 0x00108)
#define ISP39_DHAZ_HIST_CFG (ISP3X_DHAZ_BASE + 0x0010c)
#define ISP39_DHAZ_HIST_GAIN (ISP3X_DHAZ_BASE + 0x00110)
#define ISP39_DHAZ_BLEND_WET0 (ISP3X_DHAZ_BASE + 0x00114)
#define ISP39_DHAZ_BLEND_WET1 (ISP3X_DHAZ_BASE + 0x00118)
#define ISP39_DHAZ_BLEND_WET2 (ISP3X_DHAZ_BASE + 0x0011c)
#define ISP39_DHAZ_BLEND_WET3 (ISP3X_DHAZ_BASE + 0x00120)
#define ISP39_DHAZ_BLEND_WET4 (ISP3X_DHAZ_BASE + 0x00124)
#define ISP39_DHAZ_BLEND_WET5 (ISP3X_DHAZ_BASE + 0x00128)
#define ISP39_DHAZ_HIST_IIR0 (ISP3X_DHAZ_BASE + 0x0012c)
#define ISP39_DHAZ_HIST_IIR1 (ISP3X_DHAZ_BASE + 0x00130)
#define ISP39_DHAZ_HIST_IIR2 (ISP3X_DHAZ_BASE + 0x00134)
#define ISP39_DHAZ_HIST_IIR3 (ISP3X_DHAZ_BASE + 0x00138)
#define ISP39_DHAZ_HIST_IIR4 (ISP3X_DHAZ_BASE + 0x0013c)
#define ISP39_DHAZ_HIST_IIR5 (ISP3X_DHAZ_BASE + 0x00140)
#define ISP39_DHAZ_HIST_IIR6 (ISP3X_DHAZ_BASE + 0x00144)
#define ISP39_DHAZ_HIST_IIR7 (ISP3X_DHAZ_BASE + 0x00148)
#define ISP39_DHAZ_HIST_RW (ISP3X_DHAZ_BASE + 0x0014c)
#define ISP39_DHAZ_CTRL_SHD (ISP3X_DHAZ_BASE + 0x00180)
#define ISP39_DHAZ_ADP_RD0 (ISP3X_DHAZ_BASE + 0x00184)
#define ISP39_DHAZ_ADP_RD1 (ISP3X_DHAZ_BASE + 0x00188)
#define ISP39_DHAZ_LINE_CNT (ISP3X_DHAZ_BASE + 0x0018c)
#define ISP3X_3DLUT_BASE 0x00003E00
#define ISP3X_3DLUT_CTRL (ISP3X_3DLUT_BASE + 0x00000)
@@ -1466,6 +1941,33 @@
#define ISP3X_GAIN_G1_G2 (ISP3X_GAIN_BASE + 0x00008)
#define ISP3X_GAIN_FIFO_STATUS (ISP3X_GAIN_BASE + 0x0000C)
#define ISP39_COMMON3A_BASE 0x00004000
#define ISP39_W3A_CTRL0 (ISP39_COMMON3A_BASE + 0x00000)
#define ISP39_W3A_CTRL1 (ISP39_COMMON3A_BASE + 0x00004)
#define ISP39_W3A_INT_EN (ISP39_COMMON3A_BASE + 0x00010)
#define ISP39_W3A_INT_STAT (ISP39_COMMON3A_BASE + 0x00014)
#define ISP39_W3A_INT_MASK (ISP39_COMMON3A_BASE + 0x00018)
#define ISP39_W3A_AEBIG_ADDR (ISP39_COMMON3A_BASE + 0x00020)
#define ISP39_W3A_AE0_ADDR (ISP39_COMMON3A_BASE + 0x00024)
#define ISP39_W3A_AF_ADDR (ISP39_COMMON3A_BASE + 0x00030)
#define ISP39_W3A_AWB_ADDR (ISP39_COMMON3A_BASE + 0x00034)
#define ISP39_W3A_PDAF_ADDR (ISP39_COMMON3A_BASE + 0x00038)
#define ISP39_W3A_AEBIG_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00040)
#define ISP39_W3A_AE0_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00044)
#define ISP39_W3A_AF_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00050)
#define ISP39_W3A_AWB_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00054)
#define ISP39_W3A_PDAF_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00058)
#define ISP39_VI3A_CTRL0 (ISP39_COMMON3A_BASE + 0x00080)
#define ISP39_VI3A_CTRL1 (ISP39_COMMON3A_BASE + 0x00084)
#define ISP39_VI3A_INT_EN (ISP39_COMMON3A_BASE + 0x00090)
#define ISP39_VI3A_INT_STAT (ISP39_COMMON3A_BASE + 0x00094)
#define ISP39_VI3A_INT_MASK (ISP39_COMMON3A_BASE + 0x00098)
#define ISP39_VI3A_BLS_FIXED_0 (ISP39_COMMON3A_BASE + 0x000a0)
#define ISP39_VI3A_BLS_FIXED_1 (ISP39_COMMON3A_BASE + 0x000a4)
#define ISP39_VI3A_GAIN_0 (ISP39_COMMON3A_BASE + 0x000a8)
#define ISP39_VI3A_GAIN_1 (ISP39_COMMON3A_BASE + 0x000ac)
#define ISP39_W3A_DBG0 (ISP39_COMMON3A_BASE + 0x000f0)
#define ISP3X_RAWAE_LITE_BASE 0x00004500
#define ISP3X_RAWAE_LITE_CTRL (ISP3X_RAWAE_LITE_BASE + 0x00000)
#define ISP3X_RAWAE_LITE_BLK_SIZ (ISP3X_RAWAE_LITE_BASE + 0x00004)
@@ -1596,6 +2098,13 @@
#define ISP3X_RAWAF_RAM_DATA (ISP3X_RAWAF_BASE + 0x000E0)
#define ISP32L_RAWAF_CORING_H (ISP3X_RAWAF_BASE + 0x000AC)
#define ISP32L_RAWAF_CORING_V (ISP3X_RAWAF_BASE + 0x000BC)
#define ISP39_RAWAF_HIGHLIT_CNT_WINB (ISP3X_RAWAF_BASE + 0x0001C)
#define ISP39_RAWAF_H1IIR_SUMB (ISP3X_RAWAF_BASE + 0x00020)
#define ISP39_RAWAF_H2IIR_SUMB (ISP3X_RAWAF_BASE + 0x00024)
#define ISP39_RAWAF_V1IIR_SUMB (ISP3X_RAWAF_BASE + 0x00028)
#define ISP39_RAWAF_V2IIR_SUMB (ISP3X_RAWAF_BASE + 0x0002c)
#define ISP39_RAWAF_HVIIR_VAR_SHIFT (ISP3X_RAWAF_BASE + 0x000cc)
#define ISP39_RAWAF_THRES (ISP3X_RAWAF_BASE + 0x000d8)
#define ISP3X_RAWAWB_BASE 0x00005000
#define ISP3X_RAWAWB_CTRL (ISP3X_RAWAWB_BASE + 0x0000)
@@ -1907,6 +2416,7 @@
#define ISP3X_SW_CGC_RATIO_EN BIT(29)
/* ISP CTRL1 */
#define ISP39_YUVME_FST_FRAME BIT(18)
#define ISP32_SHP_FST_FRAME BIT(19)
#define ISP3X_YNR_FST_FRAME BIT(23)
#define ISP3X_ADRC_FST_FRAME BIT(24)
@@ -1941,6 +2451,7 @@
#define ISP3X_AFM_LUM_OF BIT(13)
#define ISP3X_SIAF_FIN BIT(14)
#define ISP3X_SIHST_RDY BIT(15)
#define ISP39_LDCV_END BIT(15)
#define ISP3X_LSC_LUT_ERR BIT(16)
#define ISP3X_FLASH_CAP BIT(17)
#define ISP3X_EXP_END BIT(18)
@@ -1989,6 +2500,8 @@
#define ISP3X_SCL_HPHASE_EN BIT(10)
#define ISP3X_SCL_CLIP_EN BIT(11)
#define ISP3X_SCL_IN_CLIP_EN BIT(12)
#define ISP32_SCL_CLIP_EN BIT(13)
#define ISP32_SCL_IN_CLIP_EN BIT(14)
#define ISP32_SCALE_AVG_H_EN BIT(8)
#define ISP32_SCALE_AVG_V_EN BIT(9)
@@ -1999,6 +2512,17 @@
#define ISP32_SCALE_BIL_FACTOR BIT(12)
#define ISP32_SCALE_AVE_FACTOR BIT(16)
/* LDCV */
#define ISP39_LDCV_EN BIT(0)
#define ISP39_LDCV_OUTPUT_YUV400 0
#define ISP39_LDCV_OUTPUT_YUYV BIT(2)
#define ISP39_LDCV_OUTPUT_YUV422 BIT(3)
#define ISP39_LDCV_OUTPUT_YUV420 GENMASK(3, 2)
#define ISP39_LDCV_UV_SWAP BIT(4)
#define ISP39_LDCV_LUT_MODE(x) ((x & 0x3) << 24)
#define ISP39_LDCV_FORCE_UPD BIT(26)
#define ISP39_LDCV_EN_SHD BIT(31)
/* mi interrupt */
#define ISP3X_MI_MP_FRAME BIT(0)
#define ISP3X_MI_SP_FRAME BIT(1)
@@ -2198,6 +2722,7 @@
#define ISP3X_LDCH_EN BIT(0)
#define ISP3X_LDCH_LUT_MODE(x) (((x) & 0x3) << 24)
#define ISP3X_LDCH_MAP_ERR BIT(29)
#define ISP3X_LDCH_FORCE_UPD BIT(31)
/* DHAZ */
#define ISP3X_DHAZ_ENMUX BIT(0)
@@ -2210,6 +2735,12 @@
#define ISP3X_DHAZ_SOFT_WR_EN BIT(25)
#define ISP3X_DHAZ_ROUND_EN BIT(26)
#define ISP39_DHAZ_IIR_RD_ID(x) ((x) & 0xff)
#define ISP39_DHAZ_IIR_RD_P BIT(8)
#define ISP39_DHAZ_IIR_RDATA_VAL BIT(9)
#define ISP39_DHAZ_IIR_WR_ID(x) (((x) & 0xff) << 16)
#define ISP39_DHAZ_IIR_WR_CLEAR BIT(24)
/* HDRTMO */
/* HDRDRC */
@@ -2217,6 +2748,8 @@
#define ISP3X_DRC_IIR_WEIGHT_MASK GENMASK(22, 16)
#define ISP39_ADRC_CMPS_BYP_EN BIT(2)
/* HDRMGE */
/* RAWNR */
@@ -2225,6 +2758,7 @@
#define ISP32_EXPD_EN BIT(0)
#define ISP32_EXPD_K_SHIFT(a) (((a) & 0xf) << 4)
#define ISP32_EXPD_MODE(a) (((a) & 0x3) << 8)
#define ISP39_EXPD_INPUT_16 BIT(8)
#define ISP32_EXPD_DATA(a, b) ((a) | (b) << 16)
@@ -2239,6 +2773,7 @@
#define ISP3X_CCM_HIGHY_ADJ_DIS BIT(1)
#define ISP32_CCM_ENH_ADJ_EN BIT(2)
#define ISP32_CCM_ASYM_ADJ_EN BIT(3)
#define ISP39_CCM_SAT_DECAY_EN BIT(4)
/* 3DLUT */
#define ISP3X_3DLUT_EN BIT(0)
@@ -2256,6 +2791,33 @@
#define ISP3X_LSC_SECTOR_16X16 BIT(2)
#define ISP3X_LSC_PRE_RD_ST_MODE BIT(4)
/* COMMON3A */
#define ISP39_W3A_EN BIT(0)
#define ISP39_W3A_PDAF_EN BIT(1)
#define ISP39_W3A_3A_HOLD_DIS BIT(2)
#define ISP39_W3A_PDAF2DDR_HOLD_DIS BIT(3)
#define ISP39_W3A_AUTO_CLR_EN BIT(4)
#define ISP39_W3A_CLK_GATING_DIS BIT(5)
#define ISP39_W3A_FORCE_UPD BIT(31)
#define ISP39_W3A_INT_AEBIG BIT(0)
#define ISP39_W3A_INT_AE0 BIT(1)
#define ISP39_W3A_INT_AF BIT(4)
#define ISP39_W3A_INI_AWB BIT(5)
#define ISP39_W3A_INT_PDAF BIT(6)
#define ISP39_W3A_INT_ERR BIT(16)
#define ISP39_W3A_INT_ERR_MASK GENMASK(31, 16)
#define ISP39_W3A_INT_AEBIG_OVF BIT(16)
#define ISP39_W3A_INT_AE0_OVF BIT(17)
#define ISP39_W3A_INT_AF_HIIR_OVF BIT(20)
#define ISP39_W3A_INT_AF_VIIR_OVF BIT(21)
#define ISP39_W3A_INT_AF_AEHGL_OVF BIT(22)
#define ISP39_W3A_INT_AWB_OVF BIT(23)
#define ISP39_W3A_INT_PDAF_OVF BIT(24)
#define ISP39_W3A_INT_WCFIFO_WR_ERR BIT(30)
#define ISP39_W3A_INT_WCFIFO_RD_ERR BIT(31)
/* RAWAE */
#define ISP3X_RAWAE_LITE_EN BIT(0)
#define ISP3X_RAWAE_LITE_WNDNUM BIT(1)

90
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -224,6 +224,10 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
break;
case ISP_V39:
max_w = CIF_ISP_INPUT_W_MAX_V39;
max_h = CIF_ISP_INPUT_H_MAX_V39;
break;
default:
max_w = CIF_ISP_INPUT_W_MAX;
max_h = CIF_ISP_INPUT_H_MAX;
@@ -596,11 +600,6 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
val = rkisp_read(dev, ISP_HDRMGE_BASE, false) & 0xf;
}
if (mode & T_START_C)
rkisp_expander_config(dev, NULL, true);
else
rkisp_expander_config(dev, NULL, false);
if (is_feature_on) {
if ((ISP2X_MODULE_HDRMGE & ~iq_feature) && (val & SW_HDRMGE_EN)) {
v4l2_err(&dev->v4l2_dev, "hdrmge is not supported\n");
@@ -661,13 +660,15 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
rkisp_update_regs(dev, CTRL_VI_ISP_PATH, SUPER_IMP_COLOR_CR);
rkisp_update_regs(dev, DUAL_CROP_M_H_OFFS, ISP3X_DUAL_CROP_FBC_V_SIZE);
rkisp_update_regs(dev, ISP_ACQ_H_OFFS, DUAL_CROP_CTRL);
rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, MI_WR_CTRL);
rkisp_update_regs(dev, ISP39_LDCV_BIC_TABLE0, MI_WR_CTRL);
rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, ISP39_LDCV_CTRL);
rkisp_update_regs(dev, ISP32_BP_RESIZE_SCALE_HY, SELF_RESIZE_CTRL);
rkisp_update_regs(dev, MAIN_RESIZE_SCALE_HY, ISP32_BP_RESIZE_CTRL);
rkisp_update_regs(dev, ISP_GAMMA_OUT_CTRL, MAIN_RESIZE_CTRL);
rkisp_update_regs(dev, MI_RD_CTRL2, ISP_LSC_CTRL);
rkisp_update_regs(dev, MI_MP_WR_Y_BASE, MI_WR_CTRL2 - 4);
rkisp_update_regs(dev, ISP_LSC_XGRAD_01, ISP_RAWAWB_RAM_DATA);
rkisp_update_regs(dev, ISP39_W3A_CTRL1, ISP3X_RAWAWB_RAM_DATA_BASE);
rkisp_update_regs(dev, ISP_LSC_XGRAD_01, ISP39_W3A_CTRL0);
if (dev->isp_ver == ISP_V20 &&
(rkisp_read(dev, ISP_DHAZ_CTRL, false) & ISP_DHAZ_ENMUX ||
rkisp_read(dev, ISP_HDRTMO_CTRL, false) & ISP_HDRTMO_EN)) {
@@ -677,15 +678,17 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true);
rkisp_write(dev, MI_WR_INIT, ISP21_SP_FORCE_UPD | ISP21_MP_FORCE_UPD, true);
} else {
if (dev->isp_ver == ISP_V32_L)
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
if (dev->isp_ver == ISP_V39)
rkisp_write(dev, ISP39_MAIN_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
}
/* sensor mode & index */
if (dev->isp_ver >= ISP_V21) {
val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
val |= ISP21_SENSOR_INDEX(dev->multi_index);
if (dev->isp_ver == ISP_V32_L)
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
val |= ISP32L_SENSOR_MODE(dev->multi_mode);
else
val |= ISP21_SENSOR_MODE(dev->multi_mode);
@@ -845,6 +848,11 @@ run_next:
dev->irq_ends_mask |= ISP_FRAME_BP;
else
dev->irq_ends_mask &= ~ISP_FRAME_BP;
if (dev->isp_ver == ISP_V39 &&
rkisp_read(dev, ISP39_LDCV_CTRL, true) & ISP39_LDCV_EN_SHD)
dev->irq_ends_mask |= ISP_FRAME_LDC;
else
dev->irq_ends_mask &= ~ISP_FRAME_LDC;
if (hw->is_frm_buf) {
val = ISP32L_WR_FRM_BUF_EN | ISP32L_RD_FRM_BUF_EN |
@@ -1117,7 +1125,7 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
}
/* check output stream is off */
val = ISP_FRAME_MP | ISP_FRAME_SP | ISP_FRAME_MPFBC | ISP_FRAME_BP;
val = ISP_FRAME_MP | ISP_FRAME_SP | ISP_FRAME_MPFBC | ISP_FRAME_BP | ISP_FRAME_VPSS;
if (!(dev->irq_ends_mask & val)) {
u32 state = dev->isp_state;
struct rkisp_stream *s;
@@ -1158,10 +1166,10 @@ end:
static void rkisp_set_state(u32 *state, u32 val)
{
u32 mask = 0xff;
u32 mask = 0xffff;
if (val < ISP_STOP)
mask = 0xff00;
mask = 0xffff0000;
*state &= mask;
*state |= val;
}
@@ -1179,7 +1187,7 @@ static void rkisp_config_ism(struct rkisp_device *dev)
/* isp2.0 no ism */
if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 ||
dev->isp_ver == ISP_V32_L)
dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
return;
if (dev->unite_div > ISP_UNITE_DIV1)
@@ -1765,7 +1773,7 @@ static int rkisp_config_isp(struct rkisp_device *dev)
irq_mask |= ISP2X_LSC_LUT_ERR;
if (dev->is_pre_on)
irq_mask |= CIF_ISP_FRAME_IN;
rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true);
rkisp_unite_set_bits(dev, CIF_ISP_IMSC, 0, irq_mask, true);
if ((dev->isp_ver == ISP_V20 ||
dev->isp_ver == ISP_V21) &&
@@ -2401,6 +2409,34 @@ static const struct ispsd_in_fmt rkisp_isp_input_formats[] = {
.mipi_dt = CIF_CSI2_DT_RAW12,
.yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
.bus_width = 12,
}, {
.name = "SRGGB16_1X16",
.mbus_code = MEDIA_BUS_FMT_SRGGB16_1X16,
.fmt_type = FMT_BAYER,
.mipi_dt = CIF_CSI2_DT_RAW16,
.bayer_pat = RAW_RGGB,
.bus_width = 16,
}, {
.name = "SBGGR12_1X16",
.mbus_code = MEDIA_BUS_FMT_SBGGR16_1X16,
.fmt_type = FMT_BAYER,
.mipi_dt = CIF_CSI2_DT_RAW16,
.bayer_pat = RAW_BGGR,
.bus_width = 16,
}, {
.name = "SGBRG12_1X16",
.mbus_code = MEDIA_BUS_FMT_SGBRG16_1X16,
.fmt_type = FMT_BAYER,
.mipi_dt = CIF_CSI2_DT_RAW16,
.bayer_pat = RAW_GBRG,
.bus_width = 16,
}, {
.name = "SGRBG12_1X16",
.mbus_code = MEDIA_BUS_FMT_SGRBG16_1X16,
.fmt_type = FMT_BAYER,
.mipi_dt = CIF_CSI2_DT_RAW16,
.bayer_pat = RAW_GRBG,
.bus_width = 16,
}
};
@@ -2703,6 +2739,10 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd,
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
break;
case ISP_V39:
max_w = CIF_ISP_INPUT_W_MAX_V39;
max_h = CIF_ISP_INPUT_H_MAX_V39;
break;
default:
max_w = CIF_ISP_INPUT_W_MAX;
max_h = CIF_ISP_INPUT_H_MAX;
@@ -3270,10 +3310,20 @@ static int rkisp_subdev_link_setup(struct media_entity *entity,
stream = &dev->cap_dev.stream[RKISP_STREAM_VIR];
} else if (!strcmp(remote->entity->name, SP_VDEV_NAME)) {
stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
if (flags & MEDIA_LNK_FL_ENABLED &&
dev->cap_dev.stream[RKISP_STREAM_LDC].linked)
goto err;
} else if (!strcmp(remote->entity->name, MP_VDEV_NAME)) {
stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
if (flags & MEDIA_LNK_FL_ENABLED &&
dev->br_dev.linked)
(dev->br_dev.linked ||
dev->cap_dev.stream[RKISP_STREAM_LDC].linked))
goto err;
} else if (!strcmp(remote->entity->name, LDC_VDEV_NAME)) {
stream = &dev->cap_dev.stream[RKISP_STREAM_LDC];
if (flags & MEDIA_LNK_FL_ENABLED &&
(dev->cap_dev.stream[RKISP_STREAM_MP].linked ||
dev->cap_dev.stream[RKISP_STREAM_SP].linked))
goto err;
} else if (!strcmp(remote->entity->name, BRIDGE_DEV_NAME)) {
if (flags & MEDIA_LNK_FL_ENABLED &&
@@ -3414,10 +3464,10 @@ static int rkisp_get_info(struct rkisp_device *dev, struct rkisp_isp_info *info)
return ret;
rd_mode = cfg.hdr_mode;
if (rd_mode == HDR_COMPR)
bit = cfg.compr.bit > 20 ? 20 : cfg.compr.bit;
bit = cfg.compr.src_bit > 20 ? 20 : cfg.compr.src_bit;
} else {
rd_mode = dev->rd_mode;
bit = dev->hdr.compr_bit;
bit = dev->hdr.src_bit;
}
switch (rd_mode) {
@@ -4135,6 +4185,8 @@ void rkisp_isp_isr(unsigned int isp_mis,
ISP2X_3A_RAWAWB;
bool sof_event_later = false;
if (dev->isp_ver > ISP_V20)
si3a_isr_mask = 0;
/*
* The last time that rx perform 'back read' don't clear done flag
* in advance, otherwise the statistics will be abnormal.
@@ -4383,6 +4435,10 @@ vs_skip:
rkisp_dvbm_event(dev, ISP3X_OUT_FRM_END);
}
if ((isp_mis & ISP39_LDCV_END) && (dev->isp_ver == ISP_V39)) {
writel(ISP39_LDCV_END, base + CIF_ISP_ICR);
rkisp_stream_ldc_end_v39(dev);
}
if (isp_mis & CIF_ISP_FRAME)
rkisp_check_idle(dev, ISP_FRAME_END);
}

4
drivers/media/platform/rockchip/isp/rkisp.h
View File

@@ -63,8 +63,10 @@
#define CIF_ISP_INPUT_H_MAX_V32_L 3136
#define CIF_ISP_INPUT_W_MAX_V32_L_UNITE 8192
#define CIF_ISP_INPUT_H_MAX_V32_L_UNITE 6144
#define CIF_ISP_INPUT_W_MAX_V39 4672
#define CIF_ISP_INPUT_H_MAX_V39 3504
#define CIF_ISP_INPUT_W_MIN 272
#define CIF_ISP_INPUT_H_MIN 256
#define CIF_ISP_INPUT_H_MIN 272
#define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX
#define CIF_ISP_OUTPUT_H_MAX CIF_ISP_INPUT_H_MAX
#define CIF_ISP_OUTPUT_W_MIN CIF_ISP_INPUT_W_MIN

22
include/uapi/linux/rk-camera-module.h
View File

@@ -414,29 +414,25 @@ enum rkmodule_hdr_mode {
HDR_COMPR,
};
enum rkmodule_hdr_compr_segment {
HDR_COMPR_SEGMENT_4 = 4,
HDR_COMPR_SEGMENT_12 = 12,
HDR_COMPR_SEGMENT_16 = 16,
};
#define HDR_COMPR_POINT_MAX 32
/* rkmodule_hdr_compr
* linearised and compressed data for hdr: data_src = K * data_compr + XX
*
* bit: bit of src data, max 20 bit.
* segment: linear segment, support 4, 6 or 16.
* src_bit: bit of src data, max 20 bit.
* point: linear point number, max 32 for rk3576.
* k_shift: left shift bit of slop amplification factor, 2^k_shift, [0 15].
* slope_k: K * 2^k_shift.
* data_src_shitf: left shift bit of source data, data_src = 2^data_src_shitf
* data_src: source data.
* data_compr: compressed data.
*/
struct rkmodule_hdr_compr {
enum rkmodule_hdr_compr_segment segment;
__u8 bit;
__u8 point;
__u8 src_bit;
__u8 k_shift;
__u8 data_src_shitf[HDR_COMPR_SEGMENT_16];
__u16 data_compr[HDR_COMPR_SEGMENT_16];
__u32 slope_k[HDR_COMPR_SEGMENT_16];
__u16 data_compr[HDR_COMPR_POINT_MAX];
__u32 data_src[HDR_COMPR_POINT_MAX];
__u32 slope_k[HDR_COMPR_POINT_MAX];
};
/**

4
include/uapi/linux/rk-isp2-config.h
View File

@@ -10,6 +10,7 @@
#include <linux/const.h>
#include <linux/types.h>
#include <linux/v4l2-controls.h>
#include <linux/rk-camera-module.h>
#define RKISP_API_VERSION KERNEL_VERSION(2, 5, 0)
@@ -104,6 +105,9 @@
#define RKISP_CMD_SET_IQTOOL_CONN_ID \
_IOW('V', BASE_VIDIOC_PRIVATE + 113, int)
#define RKISP_CMD_SET_EXPANDER \
_IOW('V', BASE_VIDIOC_PRIVATE + 114, struct rkmodule_hdr_cfg)
/*************************************************************/
#define ISP2X_ID_DPCC (0)

1602
include/uapi/linux/rk-isp39-config.h Normal file
View File

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