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add rknand

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This commit is contained in:
zhaoyifeng
2010-12-07 16:13:40 +08:00
parent d1e7f16f43
commit 4d463a643a
15 changed files with 2721 additions and 1 deletions
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5
arch/arm/mach-rk29/board-rk29sdk.c Normal file → Executable file
View File

@@ -906,6 +906,11 @@ static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_SDMMC1_RK29
&rk29_device_sdmmc1,
#endif
#ifdef CONFIG_MTD_NAND_RK29XX
&rk29xx_device_nand,
#endif
#ifdef CONFIG_MTD_NAND_RK29
&rk29_device_nand,
#endif

23
arch/arm/mach-rk29/devices.c
View File

@@ -434,6 +434,29 @@ struct platform_device rk29_device_fb = {
}
};
#endif
#if defined(CONFIG_MTD_NAND_RK29XX)
static struct resource rk29xxnand_resources[] = {
{
.start = RK29_NANDC_PHYS,
.end = RK29_NANDC_PHYS+RK29_NANDC_SIZE -1,
.flags = IORESOURCE_MEM,
}
};
struct platform_device rk29xx_device_nand = {
.name = "rk29xxnand",
.id = -1,
.resource = rk29xxnand_resources,
.num_resources= ARRAY_SIZE(rk29xxnand_resources),
.dev = {
.platform_data= &rk29_nand_data,
},
};
#endif
#if defined(CONFIG_MTD_NAND_RK29)
static struct resource nand_resources[] = {
{

1
arch/arm/mach-rk29/devices.h
View File

@@ -41,6 +41,7 @@ extern struct rk29xx_spi_platform_data rk29xx_spi0_platdata;
extern struct rk29xx_spi_platform_data rk29xx_spi1_platdata;
extern struct platform_device rk29_device_fb;
extern struct platform_device rk29_device_nand;
extern struct platform_device rk29xx_device_nand;
extern struct rk29_sdmmc_platform_data default_sdmmc0_data;
extern struct rk29_sdmmc_platform_data default_sdmmc1_data;
extern struct platform_device rk29_device_sdmmc0;

2
drivers/mtd/Kconfig
View File

@@ -323,6 +323,8 @@ source "drivers/mtd/devices/Kconfig"
source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/rknand/Kconfig"
source "drivers/mtd/onenand/Kconfig"
source "drivers/mtd/lpddr/Kconfig"

2
drivers/mtd/Makefile
View File

@@ -29,6 +29,6 @@ obj-$(CONFIG_MTD_OOPS) += mtdoops.o
nftl-objs := nftlcore.o nftlmount.o
inftl-objs := inftlcore.o inftlmount.o
obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ rknand/
obj-$(CONFIG_MTD_UBI) += ubi/

41
drivers/mtd/rknand/Kconfig Executable file
View File

@@ -0,0 +1,41 @@
#
# linux/drivers/mtd/rknand/Kconfig
#
config MTD_RKNAND
tristate "RK NAND Device Support"
depends on MTD
select MTD_RK_NAND_IDS
help
RK NAND Device Support
if MTD_RKNAND
config MTD_NAND_RK29XX
tristate "RK29 on-chip NAND Flash Controller driver with FTL"
depends on MTD_RKNAND
default y
help
This enables the RK28xx on-chip NAND flash controller and NFTL driver.
config RKFTL_PAGECACHE_SIZE
int "config page remap mtd part size(MB),MAX is 128MB,this mtd part will mount in /data/data"
depends on MTD_RKNAND
default "64"
help
default size is 64MB,and "swap" size is (128 - 64)MB.if you config this size up to 128MB,then "swap" funtion will disable.
config MTD_NAND_RK29XX_DEBUG
tristate "RK29 Nand driver debug enables"
depends on MTD_RKNAND
default n
help
config MTD_NAND_RK29XX_DEBUG_VERBOSE
int "Debugging verbosity (0 = quiet, 3 = noisy)"
depends on MTD_NAND_RK29XX_DEBUG
default "0"
help
Determines the verbosity level of the MTD NAND debugging messages.
endif # MTD_RKNAND

13
drivers/mtd/rknand/Makefile Executable file
View File

@@ -0,0 +1,13 @@
#
# linux/drivers/nand/Makefile
#
# $Id: Makefile,v 1.2.4.1 2010/07/14 02:28:12 Administrator Exp $
#
obj-$(CONFIG_MTD_NAND_RK29XX) += flash.o
obj-$(CONFIG_MTD_NAND_RK29XX) += ftl.o
obj-$(CONFIG_MTD_NAND_RK29XX) += rknand_base.o
#obj-$(CONFIG_MTD_UBI) += ubi/
$(obj)/flash.o: $(obj)/flash.uu
uudecode $(obj)/flash.uu -o $(obj)/flash.o
$(obj)/ftl.o: $(obj)/ftl.uu
uudecode $(obj)/ftl.uu -o $(obj)/ftl.o

191
drivers/mtd/rknand/api_flash.h Executable file
View File

@@ -0,0 +1,191 @@
/********************************************************************************
*********************************************************************************
COPYRIGHT (c) 2004 BY ROCK-CHIP FUZHOU
-- ALL RIGHTS RESERVED --
File Name: api_flash.h
Author: XUESHAN LIN
Created: 1st Dec 2008
Modified:
Revision: 1.00
Modify log:
1.01 <20><><EFBFBD><EFBFBD>FtlClose<73>ӿں<D3BF><DABA><EFBFBD> 2009.10.15 lxs
********************************************************************************
********************************************************************************/
#ifndef _API_FLASH_H
#define _API_FLASH_H
//1<><31><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:FTL<54><4C>FLASH<53><48>ʼ<EFBFBD><CABC>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
0=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1=ӳ<><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><>ǿ<EFBFBD>Ƶ͸<C6B5>
2=flash<73><68>ʼ<EFBFBD><CABC>ʧ<EFBFBD><CAA7>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>й̼<D0B9><CCBC><EFBFBD><EFBFBD><EFBFBD>
<20><><EFBFBD><EFBFBD>ֵ:<3A>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
˵ <20><>:<3A>ϵ<EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>γ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
***************************************************************************/
extern int FtlInit(unsigned int nandcBaseAddr,unsigned char pageRemapEn);
extern int FTLInit(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><>ȡFLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
DISK_NAND_CODE:<3A>̼<EFBFBD><CCBC><EFBFBD>
DISK_NAND_DATA:ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DISK_NAND_USER:<3A>û<EFBFBD><C3BB><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
˵ <20><>:
***************************************************************************/
extern unsigned int FtlGetCapacity(unsigned char LUN);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:LUN=<3D>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, Index=<3D><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ, buf=<3D><><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD>, nSec=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:0=<3D><>ȡ<EFBFBD><C8A1>ȷ; <20><>0=<3D><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>, <20><><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
˵ <20><>:
***************************************************************************/
extern int FtlRead(unsigned char LUN, unsigned int Index, unsigned int nSec, void *buf);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:д<><D0B4><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:LUN=<3D>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, Index=<3D><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ, buf=<3D><><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD>, nSec=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:0=<3D><>ȷд<C8B7><D0B4>; <20><>0=д<><D0B4><EFBFBD><EFBFBD>ʧ<EFBFBD><CAA7>, <20><><EFBFBD><EFBFBD>û<EFBFBD>б<EFBFBD><D0B1><EFBFBD>ȷд<C8B7><D0B4>
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
˵ <20><>:
***************************************************************************/
extern int FtlWrite(unsigned char LUN, unsigned int Index, unsigned int nSec, void *buf);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:MLC FLASH<53><48><EFBFBD><EFBFBD>ˢ<EFBFBD><CBA2>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
˵ <20><>:<3A><>ϵͳIDLE/<2F>ڱȽϼ<C8BD><CFBC>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>ʱ(<28><>A-B<><42><EFBFBD>š<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>)<29><><EFBFBD>øú<C3B8><C3BA><EFBFBD>,
<20>ܼ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ܽϳ<DCBD>(<28><><EFBFBD><EFBFBD>ms<6D><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD>s)
***************************************************************************/
extern void FlashRefreshHook(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:AHB<48><42>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ҫ<EFBFBD><D2AA><EFBFBD>ô˽ӿ<CBBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FLASHʱ<48><CAB1>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:AHBnKHz=<3D><>Ƶ(AHB)
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
extern void FlashTimingCfg(unsigned int AHBnKHz);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:FTL <20>رգ<D8B1><D5A3>ػ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><>
˵ <20><>:<3A>ػ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
***************************************************************************/
extern void FtlClose(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:FTL <20><>ʱ<EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ1S<31><53><EFBFBD>ҵ<EFBFBD><D2B5><EFBFBD>һ<EFBFBD><D2BB>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><>
˵ <20><>:FTL<54><4C>һЩCACHE<48>ڶ<EFBFBD>ʱ<EFBFBD>л<EFBFBD>дflash
***************************************************************************/
extern void FtlTimeHook(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><>ȡ flash page <20><>С<EFBFBD><D0A1><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD>濪<EFBFBD><E6BFAA><EFBFBD><EFBFBD>,
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:page<67><65>С<EFBFBD><D0A1>sector<6F><72>λ
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
˵<EFBFBD><EFBFBD>: <20><>Ҫ<EFBFBD><D2AA>FTLInit<69><74><EFBFBD>ſ<EFBFBD><C5BF><EFBFBD>
***************************************************************************/
extern int FlashGetPageSize(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:AHB<48><42>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ҫ<EFBFBD><D2AA><EFBFBD>ô˽ӿ<CBBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FLASHʱ<48><CAB1>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:AHBnMHz=<3D><>Ƶ(AHB)
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
extern void FlashTimingCfg(unsigned int AHBnKHz);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:ϵͳ<CFB5><CDB3>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
extern void FtlFlashSysProtSetOn(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:ϵͳ<CFB5><CDB3>д<EFBFBD><D0B4><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
extern void FtlFlashSysProtSetOff(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD>ϵͳ<CFB5>̣<EFBFBD><CCA3><EFBFBD><EFBFBD><EFBFBD>ʱʹ<CAB1><CAB9>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
extern void FtlLowFormatSysDisk(void);
extern int FtlWriteImage(unsigned int Index, unsigned int nSec, void *buf);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD>cache д<><D0B4>cache <20><>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
extern void FtlCacheDelayWriteALL(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:LBA<42><41>ַ<EFBFBD><D6B7>С<EFBFBD><D0A1>LBA<42>ĵ<EFBFBD>ַд<D6B7><D0B4><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
void FtlSetSysProtAddr(int LBA);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><>ȡFLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A>̷<EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>λ
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
int FtlGetPageZoneCapacity(void);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:Index=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, nSec=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڻ<EFBFBD><DABB><EFBFBD><EFBFBD><EFBFBD>buf<75><66>
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
int FtlPageWrite(int Index, int nSec, void *buf);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:Index=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, nSec=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڻ<EFBFBD><DABB><EFBFBD><EFBFBD><EFBFBD>buf<75><66>
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
***************************************************************************/
int FtlPageRead(int Index, int nSec, void *buf);
/***************************************************************************
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><>ȡ SN sector<6F><72>Ϣ
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:pbuf
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>:
<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>:
ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>FTLInit<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܵ<EFBFBD><EFBFBD>ã<EFBFBD>pbuf<EFBFBD><EFBFBD>С<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD><EFBFBD><EFBFBD>512 bytes<65><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϢΪ512
bytes<65><73>
***************************************************************************/
char GetSNSectorInfo(char * pbuf);
#endif

165
drivers/mtd/rknand/epphal.h Executable file
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@@ -0,0 +1,165 @@
/********************************************************************************
*********************************************************************************
COPYRIGHT (c) 2004 BY ROCK-CHIP FUZHOU
-- ALL RIGHTS RESERVED --
File Name: epphal.h
Author: XUESHAN LIN
Created: 1st Dec 2008
Modified:
Revision: 1.00
********************************************************************************
********************************************************************************/
#ifndef _EPPHAL_H
#define _EPPHAL_H
#define read_XDATA32(address) (*((uint32 volatile*)(address)))
#define write_XDATA32(address, value) (*((uint32 volatile*)(address)) = value)
#define USB_OTG_INT_CH (1<<8)
//1<>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD>
#ifndef DRIVERS_INTC
//INTC Registers
typedef volatile struct tagINTC_STRUCT
{
uint32 IRQ_INTEN_L;
uint32 IRQ_INTEN_H;
uint32 IRQ_INTMASK_L;
uint32 IRQ_INTMASK_H;
uint32 IRQ_INTFORCE_L;
uint32 IRQ_INTFORCE_H;
uint32 IRQ_RAWSTATUS_L;
uint32 IRQ_RAWSTATUS_H;
uint32 IRQ_STATUS_L;
uint32 IRQ_STATUS_H;
uint32 IRQ_MASKSTATUS_L;
uint32 IRQ_MASKSTATUS_H;
uint32 IRQ_FINALSTATUS_L;
uint32 IRQ_FINALSTATUS_H;
uint32 RESERVED1[(0xc0-0x38)/4];
uint32 FIQ_INTEN;
uint32 FIQ_INTMASK;
uint32 FIQ_INTFORCE;
uint32 FIQ_RAWSTATUS;
uint32 FIQ_STATUS;
uint32 FIQ_FINALSTATUS;
uint32 IRQ_PLEVEL;
uint32 RESERVED2[(0xe8-0xdc)/4];
uint32 IRQ_PN_OFFSET[40];
uint32 RESERVED3[(0x3f8-0x188)/4];
uint32 AHB_ICTL_COMP_VERSION;
uint32 ICTL_COMP_TYPE;
} INTC_REG, *pINTC_REG;
//SCU Registers
typedef volatile struct tagSCU_STRUCT
{
uint32 SCU_APLL_CON;
uint32 SCU_DPLL_CON;
uint32 SCU_CPLL_CON;
uint32 SCU_MODE_CON;
uint32 SCU_PMU_CON;
uint32 SCU_CLKSEL0_CON;
uint32 SCU_CLESEL1_CON;
uint32 SCU_CLKGATE0_CON;
uint32 SCU_CLKGATE1_CON;
uint32 SCU_CLKGATE2_CON;
uint32 SCU_SOFTRST_CON;
uint32 SCU_CHIPCFG_CON;
uint32 SCU_CPUPD;
} SCU_REG, *pSCU_REG;
//REG FILE registers
typedef volatile struct tagREG_FILE
{
uint32 CPU_APB_REG0;
uint32 CPU_APB_REG1;
uint32 CPU_APB_REG2;
uint32 CPU_APB_REG3;
uint32 CPU_APB_REG4;
uint32 CPU_APB_REG5;
uint32 CPU_APB_REG6;
uint32 CPU_APB_REG7;
uint32 IOMUX_A_CON;
uint32 IOMUX_B_CON;
uint32 GPIO0_AB_PU_CON;
uint32 GPIO0_CD_PU_CON;
uint32 GPIO1_AB_PU_CON;
uint32 GPIO1_CD_PU_CON;
uint32 OTGPHY_CON0;
uint32 OTGPHY_CON1;
} REG_FILE, *pREG_FILE;
/********************************************************************
** <20>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD> *
********************************************************************/
//GRF Registers
typedef volatile struct tagGRF_REG
{
uint32 CPU_APB_REG0;
uint32 CPU_APB_REG1;
uint32 CPU_APB_REG2;
uint32 CPU_APB_REG3;
uint32 CPU_APB_REG4;
uint32 CPU_APB_REG5;
uint32 CPU_APB_REG6;
uint32 CPU_APB_REG7;
uint32 IOMUX_A_CON;
uint32 IOMUX_B_CON;
uint32 GPIO0_AB_PU_CON;
uint32 GPIO0_CD_PU_CON;
uint32 GPIO1_AB_PU_CON;
uint32 GPIO1_CD_PU_CON;
uint32 OTGPHY_CON0;
uint32 OTGPHY_CON1;
}GRF_REG, *pGRF_REG,*pAPB_REG;
//GPIO Registers
typedef volatile struct tagGPIO_STRUCT
{
uint32 GPIO_SWPORTA_DR;
uint32 GPIO_SWPORTA_DDR;
uint32 RESERVED1;
uint32 GPIO_SWPORTB_DR;
uint32 GPIO_SWPORTB_DDR;
uint32 RESERVED2;
uint32 GPIO_SWPORTC_DR;
uint32 GPIO_SWPORTC_DDR;
uint32 RESERVED3;
uint32 GPIO_SWPORTD_DR;
uint32 GPIO_SWPORTD_DDR;
uint32 RESERVED4;
uint32 GPIO_INTEN;
uint32 GPIO_INTMASK;
uint32 GPIO_INTTYPE_LEVEL;
uint32 GPIO_INT_POLARITY;
uint32 GPIO_INT_STATUS;
uint32 GPIO_INT_RAWSTATUS;
uint32 GPIO_DEBOUNCE;
uint32 GPIO_PORTS_EOI;
uint32 GPIO_EXT_PORTA;
uint32 GPIO_EXT_PORTB;
uint32 GPIO_EXT_PORTC;
uint32 GPIO_EXT_PORTD;
uint32 GPIO_LS_SYNC;
}GPIO_REG,*pGPIO_REG;
#endif
//1ȫ<31>ֱ<EFBFBD><D6B1><EFBFBD>
#undef EXT
#ifdef IN_EPPHAL
#define EXT
#else
#define EXT extern
#endif
//1<><31><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
extern void EnableIRQ(void);
extern void DisableIRQ(void);
extern void EnableOtgIntr(void);
extern void DisableOtgIntr(void);
extern void InterruptInit(void);
#endif

591
drivers/mtd/rknand/flash.uu Executable file
View File

@@ -0,0 +1,591 @@
begin 644 flash.o
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end

58
drivers/mtd/rknand/nand_config.h Executable file
View File

@@ -0,0 +1,58 @@
/********************************************************************************
*********************************************************************************
COPYRIGHT (c) 2004 BY ROCK-CHIP FUZHOU
-- ALL RIGHTS RESERVED --
File Name: nand_config.h
Author: RK28XX Driver Develop Group
Created: 25th OCT 2008
Modified:
Revision: 1.00
********************************************************************************
********************************************************************************/
#ifndef _NAND_CONFIG_H
#define _NAND_CONFIG_H
#define DRIVERS_NAND
#define LINUX
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/delay.h>
//#include <asm/arch-rockchip/hardware.h>
#include "typedef.h"
#include <mach/rk29_iomap.h>
#include <mach/iomux.h>
//#include "epphal.h"
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL (void*)0
#endif
#include "FTL_OSDepend.h"
#include "flash.h"
#include "ftl.h"
#ifdef CONFIG_MTD_NAND_RK29XX_DEBUG
#undef RKNAND_DEBUG
#define RKNAND_DEBUG(format, arg...) \
printk(KERN_NOTICE format, ## arg);
#else
#undef RKNAND_DEBUG
#define RKNAND_DEBUG(n, arg...)
#endif
extern void rkNand_cond_resched(void);
#define COND_RESCHED() rkNand_cond_resched()//cond_resched()
#define PRINTF RKNAND_DEBUG
#endif

737
drivers/mtd/rknand/rknand_base.c Executable file
View File

@@ -0,0 +1,737 @@
/*
* linux/drivers/mtd/rknand/rknand_base.c
*
* Copyright (C) 2005-2009 Fuzhou Rockchip Electronics
* ZYF <zyf@rock-chips.com>
*
*
*/
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mutex.h>
#include <linux/kthread.h>
#include <linux/reboot.h>
#include <asm/io.h>
#include <asm/mach/flash.h>
#include "api_flash.h"
#define DRIVER_NAME "rk29xxnand"
#define NAND_DEBUG_LEVEL0 0
#define NAND_DEBUG_LEVEL1 1
#define NAND_DEBUG_LEVEL2 2
#define NAND_DEBUG_LEVEL3 3
long FTLWriteCount =0;
long FTLReadWriteTime =0;
long FTLSwapWriteCount =0;
long FTLPageWriteCount =0;
#ifndef CONFIG_RKFTL_PAGECACHE_SIZE
#define CONFIG_RKFTL_PAGECACHE_SIZE 64 //<2F><><EFBFBD><EFBFBD>pageӳ<65><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD>λΪMB,mount <20><>/data/data<74>¡<EFBFBD>
#endif
#define use_image
#ifdef use_image
unsigned long SysImageWriteEndAdd = 0;
int g_num_partitions = 0;
#endif
#ifdef CONFIG_MTD_NAND_RK29XX_DEBUG
static int s_debug = CONFIG_MTD_NAND_RK29XX_DEBUG_VERBOSE;
//module_param(s_debug, int, 0);
//MODULE_PARM_DESC(s_debug, "Set Debug Level 0=quiet, 5=noisy");
#undef NAND_DEBUG
/*#define NAND_DEBUG(n, format, arg...) \
if (n <= s_debug) { \
printk(KERN_NOTICE __FILE__ ":%s(): " format "\n", __FUNCTION__ , ## arg); \
}*/
#define NAND_DEBUG(n, format, arg...) \
if (n <= s_debug) { \
printk(format,##arg); \
}
#else
#undef NAND_DEBUG
#define NAND_DEBUG(n, arg...)
static const int s_debug = 0;
#endif
long RkFtlWriteCount;
/*
* RK28 LBA PARTITIONS,the size and offset value below is default value in this program,
* when RK28 LBA FLASH init,the value will be modify to the value in the nand flash.
*/
#define MAX_FLASH_PARTITION 2
#define ROOTFS_PART_SIZE 300
#define PARA_PART_SIZE 1
#define KERNEL_PART_SIZE 4
static struct mtd_partition rk28_partition_info[] = {
{
name: "misc",
offset: 0x2000*0x200,
size: 0x2000*0x200,//100MB
},
{
name: "kernel",
offset: 0x4000*0x200,
size: 0x4000*0x200,//200MB
},
{
name: "boot",
offset: 0x8000*0x200,
size: 0x2000*0x200,//200MB
},
{
name: "system",
offset: 0xE000*0x200,
size: 0x38000*0x200,//200MB
},
};
static struct mtd_partition rk28_page_part_info[] = {
{
name: "pagecache",
offset: 0,
size: CONFIG_RKFTL_PAGECACHE_SIZE * 0x800,//32MB
},
{
name: "swap",
offset: (CONFIG_RKFTL_PAGECACHE_SIZE) * 0x800,
size: 64 * 0x800,//64MB
},
};
/*
* onenand_state_t - chip states
* Enumeration for OneNAND flash chip state
*/
typedef enum {
FL_READY,
FL_READING,
FL_WRITING,
FL_ERASING,
FL_SYNCING,
FL_UNVALID,
} rknand_state_t;
struct rknand_chip {
wait_queue_head_t wq;
rknand_state_t state;
int rknand_schedule_enable;//1 enable ,0 disable
void (*pFlashCallBack)(void);//call back funtion
};
struct rknand_info {
struct mtd_info mtd;
struct mtd_info page_mtd;
struct mtd_partition *parts;
struct rknand_chip rknand;
struct task_struct *thread;
};
struct rknand_info * gpNandInfo;
static int rknand_get_device(int new_state)
{
struct rknand_chip *nand_info = &gpNandInfo->rknand;
DECLARE_WAITQUEUE(wait, current);
while (1) {
if (nand_info->state == FL_READY) {
nand_info->state = new_state;
break;
}
NAND_DEBUG(NAND_DEBUG_LEVEL1,"FLASH not ready\n");
set_current_state(TASK_UNINTERRUPTIBLE);
add_wait_queue(&nand_info->wq, &wait);
schedule();
remove_wait_queue(&nand_info->wq, &wait);
}
return 0;
}
static void rknand_release_device(void)
{
struct rknand_chip *nand_info = &gpNandInfo->rknand;
if(nand_info->pFlashCallBack)
nand_info->pFlashCallBack();//call back
nand_info->pFlashCallBack = NULL;
nand_info->state = FL_READY;
wake_up(&nand_info->wq);
}
void rkNand_cond_resched(void)
{
if(gpNandInfo->rknand.rknand_schedule_enable == 1)
{
//msleep(1);
//mdelay(1);
cond_resched();
}
}
static int rk28xxnand_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
int ret = 0;
int sector = len>>9;
int LBA = (int)(from>>9);
//printk(KERN_NOTICE "read: from=%x,len=%x,\n",(int)from,len);
NAND_DEBUG(NAND_DEBUG_LEVEL1,"-");
//FTLReadWriteTime++;
//if(len&511)
// printk("rk28xxnand_read: from=%x,len=%x,\n",(int)from,len);
rknand_get_device(FL_READING);
if(sector)
{
{
ret = FtlRead(2,LBA, sector, buf);
}
}
rknand_release_device();
*retlen = len;
return 0;//ret;
}
// cmy: before cache part use FtlWriteImage, after cache(include cache) use FtlWrite
static int write_Image(int LBA, int sector, u_char* buf)
{
int remain_sector = sector;
int write_sector = 0;
u_char* data = buf;
int index = LBA;
int ret = 0;
while(remain_sector > 0)
{
write_sector = remain_sector>32?32:remain_sector;
ret = FtlWriteImage(index, write_sector, data);
data += write_sector<<9;
index += write_sector;
remain_sector -= write_sector;
}
return ret;
}
static int rk28xxnand_write(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
int ret = 0;
int sector = len>>9;
int LBA = (int)(from>>9);
//NAND_DEBUG(NAND_DEBUG_LEVEL0,"+");
FTLWriteCount+=sector;
FTLReadWriteTime++;
//dump_stack();
//printk(KERN_NOTICE "write: from=%lx,len=%x\n",(int)from,len);
rknand_get_device(FL_WRITING);
if(sector)// cmy
{
#ifdef use_image
if(LBA < SysImageWriteEndAdd)//0x4E000)
{
printk(">>> FtlWriteImage: LBA=0x%08X sector=%d\n",LBA, sector);
ret = FtlWriteImage(LBA&0xFFFFFFE0, sector, buf);// LBA align to 32
}
#else
if(LBA<0x4E000)
ret = write_Image(LBA, sector, buf);
#endif
else
{
ret = FtlWrite(2,LBA, sector, buf);
}
}
rknand_release_device();
*retlen = len;
return 0;//ret;
}
static int rk28xxnand_page_write(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
int ret = 0;
int sector = len;
int LBA = (int)(from);
NAND_DEBUG(NAND_DEBUG_LEVEL1,"*");
FTLWriteCount+=sector;
//printk("+");
//printk(KERN_NOTICE "pagewrite: from=%lx,len=%x\n",(int)from,len);
rknand_get_device(FL_WRITING);
if(sector)// cmy
{
ret = FtlPageWrite(LBA, sector, buf);
}
rknand_release_device();
*retlen = len;
return 0;//ret;
}
static int rk28xxnand_page_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
int ret = 0;
int sector = len;
int LBA = (int)(from);
//printk(KERN_NOTICE "read: from=%x,len=%x,\n",(int)from,len);
NAND_DEBUG(NAND_DEBUG_LEVEL2,"-");
//printk("-");
//if(len&511)
// printk("rk28xxnand_read: from=%x,len=%x,\n",(int)from,len);
rknand_get_device(FL_READING);
if(sector)
{
ret = FtlPageRead(LBA, sector, buf);
}
rknand_release_device();
*retlen = len;
return 0;//ret;
}
static int rk28xxnand_erase(struct mtd_info *mtd, struct erase_info *instr)
{
int ret = 0;
if (instr->callback)
instr->callback(instr);
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_erase,add:%x,len:%x\n",instr->addr,instr->len);
return ret;
}
static int rk28xxnand_read_oob(struct mtd_info *mtd, loff_t from,
struct mtd_oob_ops *ops)
{
int ret = 0;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_read_oob\n");
return ret;
}
static int rk28xxnand_write_oob(struct mtd_info *mtd, loff_t to,
struct mtd_oob_ops *ops)
{
int ret=0;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_write_oob\n");
return ret;
}
static int rk28xxnand_suspend(struct platform_device *dev, pm_message_t pm)
{
gpNandInfo->rknand.rknand_schedule_enable = 0;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xx_nand_suspend: \n");
return 0;
}
static int rk28xxnand_resume(struct platform_device *dev)
{
gpNandInfo->rknand.rknand_schedule_enable = 1;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xx_nand_resume: \n");
return 0;
}
static int rk28xxnand_block_isbad(struct mtd_info *mtd, loff_t ofs)
{
//printk("rk28xxnand_block_isbad: \n");
return 0;
}
static int rk28xxnand_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_block_markbad: \n");
return 0;
}
static void rk28xxnand_sync(struct mtd_info *mtd)
{
/* Grab the lock and see if the device is available */
rknand_get_device(FL_SYNCING);
/* Release it and go back */
rknand_release_device();
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_sync: \n");
}
static int rk28xxnand_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
{
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_lock: \n");
return 0;
}
static int rk28xxnand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
{
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_unlock: \n");
return 0;
}
static int rk28xxnand_init(struct rknand_info *nand_info)
{
struct mtd_info *mtd = &nand_info->mtd;
struct mtd_info *page_mtd = &nand_info->page_mtd;
struct rknand_chip *rknand = &nand_info->rknand;
rknand->state = FL_READY;
rknand->rknand_schedule_enable = 1;
rknand->pFlashCallBack = NULL;
init_waitqueue_head(&rknand->wq);
NAND_DEBUG(NAND_DEBUG_LEVEL0,"FTLInit ...: \n");
if(FTLInit())
{
NAND_DEBUG(NAND_DEBUG_LEVEL0,"FTLInit Error: \n");
return -ENXIO;
}
NAND_DEBUG(NAND_DEBUG_LEVEL0,"FTLInit OK: \n");
mtd->size = (uint64_t)FtlGetCapacity(0xFF)*0x200;
//readflash modify rk28_partition_info
NAND_DEBUG(NAND_DEBUG_LEVEL0,"mtd->size: 0x%012llx\n",mtd->size);
mtd->oobsize = 0;
mtd->oobavail = 0;
mtd->ecclayout = 0;
mtd->erasesize = FlashGetPageSize()*0x200; //sector
mtd->writesize = FlashGetPageSize()*0x200;
// Fill in remaining MTD driver data
mtd->type = MTD_NANDFLASH;//MTD_RAM;//
mtd->flags = (MTD_WRITEABLE|MTD_NO_ERASE);//
mtd->erase = rk28xxnand_erase;
mtd->point = NULL;
mtd->unpoint = NULL;
mtd->read = rk28xxnand_read;
mtd->write = rk28xxnand_write;
mtd->read_oob = rk28xxnand_read_oob;
mtd->write_oob = rk28xxnand_write_oob;
mtd->panic_write = NULL;
mtd->sync = rk28xxnand_sync;
mtd->lock = rk28xxnand_lock;
mtd->unlock = rk28xxnand_unlock;
mtd->suspend = rk28xxnand_suspend;
mtd->resume = rk28xxnand_resume;
mtd->block_isbad = rk28xxnand_block_isbad;
mtd->block_markbad = rk28xxnand_block_markbad;
mtd->owner = THIS_MODULE;
page_mtd->size = FtlGetPageZoneCapacity();
//readflash modify rk28_partition_info
NAND_DEBUG(NAND_DEBUG_LEVEL0,"page_mtd->size: %x\n",page_mtd->size);
page_mtd->oobsize = 0;
page_mtd->oobavail = 0;
page_mtd->ecclayout = 0;
page_mtd->erasesize = FlashGetPageSize(); //sector
page_mtd->writesize = FlashGetPageSize();
// Fill in remaining MTD driver data
page_mtd->type = MTD_NANDFLASH;//MTD_RAM;//
page_mtd->flags = (MTD_WRITEABLE|MTD_NO_ERASE);//
page_mtd->erase = rk28xxnand_erase;
page_mtd->point = NULL;
page_mtd->unpoint = NULL;
page_mtd->read = rk28xxnand_page_read;
page_mtd->write = rk28xxnand_page_write;
page_mtd->read_oob = rk28xxnand_read_oob;
page_mtd->write_oob = rk28xxnand_write_oob;
page_mtd->panic_write = NULL;
page_mtd->sync = rk28xxnand_sync;
page_mtd->lock = rk28xxnand_lock;
page_mtd->unlock = rk28xxnand_unlock;
page_mtd->suspend = rk28xxnand_suspend;
page_mtd->resume = rk28xxnand_resume;
page_mtd->block_isbad = rk28xxnand_block_isbad;
page_mtd->block_markbad = rk28xxnand_block_markbad;
page_mtd->owner = THIS_MODULE;
return 0;
}
/*
* CMY: <20><><EFBFBD><EFBFBD><EFBFBD>˶<EFBFBD><CBB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>֧<EFBFBD><D6A7>
* <09><>cmdline<6E><65><EFBFBD>ṩ<EFBFBD><E1B9A9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>cmdline<6E>ķ<EFBFBD><C4B7><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD>з<EFBFBD><D0B7><EFBFBD>
* <09><>cmdlineû<65><C3BB><EFBFBD>ṩ<EFBFBD><E1B9A9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>Ĭ<EFBFBD>ϵķ<CFB5><C4B7><EFBFBD><EFBFBD><EFBFBD>Ϣ(rk28_partition_info)<29><><EFBFBD>з<EFBFBD><D0B7><EFBFBD>
*/
#ifdef CONFIG_MTD_CMDLINE_PARTS
const char *part_probes[] = { "cmdlinepart", NULL };
#endif
static int rk28xxnand_add_partitions(struct rknand_info *nand_info)
{
NAND_DEBUG(NAND_DEBUG_LEVEL0,"Enter rk28xxnand_add_partitions\n");
#ifdef CONFIG_MTD_CMDLINE_PARTS
int num_partitions = 0;
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>н<EFBFBD><D0BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
num_partitions = parse_mtd_partitions(&(nand_info->mtd), part_probes, &nand_info->parts, 0);
printk("num_partitions = %d\n",num_partitions);
if(num_partitions > 0) {
int i;
for (i = 0; i < num_partitions; i++)
{
//printk(KERN_ERR"111 offset 0x%012llx size :0x%012llx\n",nand_info->parts[i].offset, nand_info->parts[i].size);
nand_info->parts[i].offset *= 0x200;
nand_info->parts[i].size *=0x200;
//printk(KERN_ERR"offset 0x%012llx size :0x%012llx\n",nand_info->parts[i].offset, nand_info->parts[i].size);
}
nand_info->parts[num_partitions - 1].size = nand_info->mtd.size - nand_info->parts[num_partitions - 1].offset;
#ifdef use_image
g_num_partitions = num_partitions;
#endif
return add_mtd_partitions(&nand_info->mtd, nand_info->parts, num_partitions);
}
#endif
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><C3BB><EFBFBD>ṩ<EFBFBD><E1B9A9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>Ĭ<EFBFBD>ϵķ<CFB5><C4B7><EFBFBD><EFBFBD><EFBFBD>Ϣ
printk("parse_mtd_partitions\n");
// rk28_partition_info[1].size = nand_info->mtd.size - ((ROOTFS_PART_SIZE + PARA_PART_SIZE + KERNEL_PART_SIZE)*0x100000);
// rk28_partition_info[2].offset = rk28_partition_info[1].size + rk28_partition_info[1].offset;
#ifdef use_image
g_num_partitions = sizeof(rk28_partition_info)/sizeof(struct mtd_partition);
#endif
return add_mtd_partitions(&nand_info->mtd, rk28_partition_info, sizeof(rk28_partition_info)/sizeof(struct mtd_partition));//MAX_FLASH_PARTITION);
}
static int __devinit rk28xxnand_probe(struct platform_device *pdev)
{
struct rknand_info *nand_info;
struct mtd_partition *parts;
int i;
struct resource *res = pdev->resource;
int err = 0;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_probe: \n");
gpNandInfo = kzalloc(sizeof(struct rknand_info), GFP_KERNEL);
if (!gpNandInfo)
return -ENOMEM;
nand_info = gpNandInfo;
nand_info->mtd.name = dev_name(&pdev->dev);//pdev->dev.bus_id
nand_info->mtd.priv = &nand_info->rknand;
nand_info->mtd.owner = THIS_MODULE;
nand_info->page_mtd.name = dev_name(&pdev->dev);//pdev->dev.bus_id
nand_info->page_mtd.priv = &nand_info->rknand;
nand_info->page_mtd.owner = THIS_MODULE;
if(rk28xxnand_init(nand_info))
{
err = -ENXIO;
goto exit_free;
}
/*{
char pbuf[512];
GetSNSectorInfo(pbuf);
printk("SN: %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x",pbuf[2],pbuf[3],pbuf[4],pbuf[5],pbuf[6],pbuf[7],pbuf[8],pbuf[9],
pbuf[10],pbuf[11],pbuf[12],pbuf[13],pbuf[14],pbuf[15],pbuf[16],pbuf[17]);
} */
rk28xxnand_add_partitions(nand_info);
return 0;
#if 0
nand_info->page_mtd.name = "pagecache";
add_mtd_device(&nand_info->page_mtd);
#else
//rk28_page_part_info[1].size = nand_info->page_mtd.size - rk28_page_part_info[0].size;
//add_mtd_partitions(&nand_info->page_mtd, rk28_page_part_info, 2);
#endif
#ifdef use_image
parts = nand_info->parts;
for(i=0;i<g_num_partitions;i++)
{
printk(">>> part[%d]: name=%s offset=0x%X\n", i, parts[i].name, parts[i].offset);
if(strcmp(parts[i].name,"cache") == 0)
{
SysImageWriteEndAdd = parts[i].offset;
printk(">>> SysImageWriteEndAdd=0x%X\n", SysImageWriteEndAdd);
break;
}
}
#endif
FtlSetSysProtAddr(SysImageWriteEndAdd);
dev_set_drvdata(&pdev->dev, nand_info);
return 0;
exit_free:
if(nand_info)
kfree(nand_info);
return err;
}
static int __devexit rknand_remove(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct rknand_info *nand_info = dev_get_drvdata(&pdev->dev);
struct resource *res = pdev->resource;
unsigned long size = res->end - res->start + 1;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xx_rknand_remove: \n");
dev_set_drvdata(&pdev->dev, NULL);
if (nand_info) {
if (nand_info->parts)
del_mtd_partitions(&nand_info->mtd);
else
del_mtd_device(&nand_info->mtd);
//rknand_release(&nand_info->mtd);
release_mem_region(res->start, size);
kfree(nand_info);
}
return 0;
}
void rk28xxnand_shutdown(struct platform_device *pdev)
{
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rk28xxnand_shutdown\n");
//rknand_get_device(FL_UNVALID);
//FtlClose();
//rknand_release_device();
}
static struct platform_driver rknand_driver = {
.probe = rk28xxnand_probe,
.remove = rknand_remove,
.suspend = rk28xxnand_suspend,
.resume = rk28xxnand_resume,
.shutdown = rk28xxnand_shutdown,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
//.bus = &platform_bus_type,
},
};
MODULE_ALIAS(DRIVER_NAME);
static int __init rknand_init(void)
{
int ret;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_init: \n");
ret = platform_driver_register(&rknand_driver);
NAND_DEBUG(NAND_DEBUG_LEVEL0,"platform_driver_register:ret = %x \n",ret);
return ret;
}
static void __exit rknand_exit(void)
{
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_exit: \n");
rknand_get_device(FL_UNVALID);
FtlClose();
rknand_release_device();
platform_driver_unregister(&rknand_driver);
}
module_init(rknand_init);
module_exit(rknand_exit);
#if 0//def CONFIG_rknand
/*
ע<EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD>sys dev <20><><EFBFBD>ڹػ<DAB9><D8BB>͸<EFBFBD>λʱ<CEBB>ص<EFBFBD><D8B5><EFBFBD><EFBFBD><EFBFBD>flash<73>ؼ<EFBFBD><D8BC><EFBFBD>Ϣд<CFA2><D0B4>nand flash<73>У<EFBFBD><D0A3>´ο<C2B4><CEBF><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>Կ<EFBFBD><D4BF>ٿ<EFBFBD><D9BF><EFBFBD><EFBFBD><EFBFBD>
*/
#include <linux/sysdev.h>
#include <linux/timer.h>
static int rknand_sys_suspend(struct sys_device *dev, pm_message_t state)
{
struct rknand_chip *nand_info = &gpNandInfo->rknand;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"...rknand_sys_suspend...\n");
extern void FtlCacheWriteBack(void);
nand_info->rknand_schedule_enable = 0;
if (nand_info->state == FL_READY)
{
nand_info->state = FL_WRITING;
FtlCacheWriteBack();
rknand_release_device();
}
else
{
nand_info->pFlashCallBack = FtlCacheWriteBack;
}
NAND_DEBUG(NAND_DEBUG_LEVEL0,"...rknand_sys_suspend done...\n");
return 0;
}
static int rknand_sys_resume(struct sys_device *dev)
{
struct rknand_chip *nand_info = &gpNandInfo->rknand;
nand_info->rknand_schedule_enable = 1;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"...rknand_sys_resume...\n");
return 0;
}
static int rknand_sys_shutdown(struct sys_device *dev)
{
struct rknand_chip *nand_info = &gpNandInfo->rknand;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"...rknand_sys_shutdown...\n");
nand_info->rknand_schedule_enable = 0;
if (nand_info->state == FL_READY)
{
//rknand_get_device(FL_UNVALID);
nand_info->state = FL_UNVALID;
FtlClose();
rknand_release_device();
}
else
{//flash not ready,use call back
nand_info->pFlashCallBack = FtlClose;
}
return 0;
}
static struct sysdev_class rknand_sysclass = {
.name = "rknand_sysdev",
.shutdown = rknand_sys_shutdown,
.suspend = rknand_sys_suspend,
.resume = rknand_sys_resume,
};
static struct sys_device rknand_sysdevice = {
.id = 0,
.cls = &rknand_sysclass,
};
static int __init rknand_sys_init(void)
{
int ret;
NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_sys_init!!!!!!!!!!!!!!\n");
ret = sysdev_class_register(&rknand_sysclass);
if (ret == 0)
ret = sysdev_register(&rknand_sysdevice);
return ret;
}
device_initcall(rknand_sys_init);
#endif
MODULE_LICENSE("");
MODULE_AUTHOR("ZYF <zyf@rock-chips.com>");
MODULE_DESCRIPTION("FTL layer for SLC and MlC nand flash on RK28xx SDK boards");

56
drivers/mtd/rknand/typedef.h Executable file
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@@ -0,0 +1,56 @@
#ifndef __TYPEDEF_H
#define __TYPEDEF_H
typedef volatile unsigned int REG32;
typedef volatile unsigned short REG16;
typedef volatile unsigned char REG8;
typedef int BOOLEAN;
typedef BOOLEAN BOOL;
#define FALSE 0
#define TRUE (!FALSE)
#define NULL 0
#define OK 0
#define ERROR !0
//typedef char * va_list;
typedef unsigned int uint32;
typedef unsigned int UINT32;
typedef unsigned short UINT16;
typedef unsigned char UINT8;
typedef int INT32;
typedef short INT16;
typedef char INT8;
typedef unsigned char INT8U;
typedef signed char INT8S;
typedef unsigned short INT16U;
typedef signed short INT16S;
typedef int INT32S;
typedef unsigned int INT32U;
typedef unsigned long L32U;
typedef signed long L32S;
typedef unsigned char BYTE;
//typedef volatile unsigned int data_t;
//typedef volatile unsigned int* addr_t;
typedef void (*pFunc)(void); //<2F><><EFBFBD>庯<EFBFBD><E5BAAF>ָ<EFBFBD><D6B8>, <20><><EFBFBD>ڵ<EFBFBD><DAB5>þ<EFBFBD><C3BE>Ե<EFBFBD>ַ
typedef unsigned char uint8;
typedef signed char int8;
typedef unsigned short uint16;
typedef signed short int16;
typedef signed long int32;
typedef unsigned long long uint64;
typedef signed long long int64;
//typedef unsigned char bool;
typedef unsigned short WCHAR;
#endif /*__TYPEDEF_H */

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mkkrnlimg Executable file
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