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vdin: vdin write register fail sometimes due to gate clk is off [1/1]

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PD#SWPL-9372

Problem:
write register after clk off

Solution:
write register after clk on

Verify:
verified by t962x2_x301

Change-Id: Id9639d98a5434a8be22f0de9bf4ed778b9cbeb9f
Signed-off-by: zhiwei.yuan <zhiwei.yuan@amlogic.com>
This commit is contained in:
zhiwei.yuan
2019-06-05 19:48:42 +08:00
committed by Chris KIM
parent 6f24015c1c
commit 4df4b85fdf
2 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
View File

@@ -2950,6 +2950,9 @@ void vdin_hw_enable(unsigned int offset)
void vdin_hw_disable(unsigned int offset)
{
unsigned int def_canvas;
def_canvas = offset ? vdin_canvas_ids[1][0] : vdin_canvas_ids[0][0];
/* disable cm2 */
wr_bits(offset, VDIN_CM_BRI_CON_CTRL, 0, CM_TOP_EN_BIT, CM_TOP_EN_WID);
/* disable video data input */
@@ -2963,10 +2966,9 @@ void vdin_hw_disable(unsigned int offset)
wr(offset, VDIN_COM_CTRL0, 0x00000910);
vdin_delay_line(delay_line_num, offset);
if (enable_reset)
wr(offset, VDIN_WR_CTRL, 0x0b401000);
wr(offset, VDIN_WR_CTRL, 0x0b401000 | def_canvas);
else
wr(offset, VDIN_WR_CTRL, 0x0bc01000);
wr(offset, VDIN_WR_CTRL, 0x0bc01000 | def_canvas);
/* disable clock of blackbar, histogram, histogram, line fifo1, matrix,
* hscaler, pre hscaler, clock0
*/

16
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
View File

@@ -210,7 +210,7 @@ int vdin_open_fe(enum tvin_port_e port, int index, struct vdin_dev_s *devp)
}
devp->frontend = fe;
devp->parm.port = port;
devp->parm.port = port;
/* for atv snow function */
if ((port == TVIN_PORT_CVBS3) &&
(devp->parm.info.fmt == TVIN_SIG_FMT_NULL))
@@ -223,13 +223,6 @@ int vdin_open_fe(enum tvin_port_e port, int index, struct vdin_dev_s *devp)
/* clear color para*/
memset(&devp->prop, 0, sizeof(devp->prop));
/*enable clk*/
vdin_clk_onoff(devp, true);
vdin_set_default_regmap(devp->addr_offset);
/*only for vdin0*/
if (devp->urgent_en && (devp->index == 0))
vdin_urgent_patch_resume(devp->addr_offset);
/* vdin msr clock gate enable */
if (devp->msr_clk != NULL)
clk_prepare_enable(devp->msr_clk);
@@ -269,7 +262,6 @@ void vdin_close_fe(struct vdin_dev_s *devp)
if (devp->msr_clk != NULL)
clk_disable_unprepare(devp->msr_clk);
vdin_hw_disable(devp->addr_offset);
del_timer_sync(&devp->timer);
if (devp->frontend && devp->frontend->dec_ops->close) {
devp->frontend->dec_ops->close(devp->frontend);
@@ -515,6 +507,12 @@ void vdin_start_dec(struct vdin_dev_s *devp)
is_meson_txhd_cpu())
switch_vpu_clk_gate_vmod(VPU_VPU_CLKB, VPU_CLK_GATE_ON);
/*enable clk*/
vdin_clk_onoff(devp, true);
vdin_set_default_regmap(devp->addr_offset);
if (devp->urgent_en && (devp->index == 0))
vdin_urgent_patch_resume(devp->addr_offset);
vdin_get_format_convert(devp);
devp->curr_wr_vfe = NULL;
devp->vfp->skip_vf_num = devp->prop.skip_vf_num;