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clk: rockchip: rk3288: remove ROCKCHIP_PLL_SYNC_RATE flag for CPLL and GPLL

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Change-Id: I698437b21c94684af0a7dfbe643794de62edc962
Signed-off-by: Jerry Xu <xbl@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Jerry Xu
2017-06-29 10:27:55 +08:00
committed by Tao Huang
parent 8b51cc2a32
commit 4df60ffbd1
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3288.c
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@@ -210,9 +210,9 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
RK3288_MODE_CON, 4, 5, 0, NULL),
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates),
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
};