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ARM64: dts: pd: add power domains node for rk3368

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add pd parameters in the dtsi.
support pd for rk3368.

Change-Id: If04704fabbdcf03815d81be5520077b081479af0
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
This commit is contained in:
zhangqing
2016-01-08 06:20:24 -08:00
parent e123c536d5
commit 4e58e53cc2
1 changed files with 89 additions and 1 deletions
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90
arch/arm64/boot/dts/rockchip/rk3368.dtsi
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@@ -46,6 +46,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/display/rk_fb.h>
#include <dt-bindings/power/rk3368-power.h>
/ {
compatible = "rockchip,rk3368";
@@ -561,8 +562,95 @@
};
pmu: power-management@ff730000 {
compatible = "rockchip,rk3368-pmu", "syscon";
compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff730000 0x0 0x1000>;
power: power-controller {
status = "disabled";
compatible = "rockchip,rk3368-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
/*
* Note: Although SCLK_* are the working clocks
* of device without including on the NOC, needed for
* synchronous reset.
*
* The clocks on the which NOC:
* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
* ACLK_RGA is on ACLK_RGA_NIU.
* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
*
* Which clock are device clocks:
* clocks devices
* *_IEP IEP:Image Enhancement Processor
* *_ISP ISP:Image Signal Processing
* *_VIP VIP:Video Input Processor
* *_VOP* VOP:Visual Output Processor
* *_RGA RGA
* *_EDP* EDP
* *_DPHY* LVDS
* *_HDMI HDMI
* *_MIPI_* MIPI
*/
pd_vio {
reg = <RK3368_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
<&cru ACLK_VIP>,
<&cru ACLK_RGA>,
<&cru ACLK_VOP>,
<&cru ACLK_VOP_IEP>,
<&cru DCLK_VOP>,
<&cru HCLK_IEP>,
<&cru HCLK_ISP>,
<&cru HCLK_RGA>,
<&cru HCLK_VIP>,
<&cru HCLK_VOP>,
<&cru HCLK_VIO_HDCPMMU>,
<&cru PCLK_EDP_CTRL>,
<&cru PCLK_HDMI_CTRL>,
<&cru PCLK_HDCP>,
<&cru PCLK_ISP>,
<&cru PCLK_VIP>,
<&cru PCLK_DPHYRX>,
<&cru PCLK_DPHYTX0>,
<&cru PCLK_MIPI_CSI>,
<&cru PCLK_MIPI_DSI0>,
<&cru SCLK_VOP0_PWM>,
<&cru SCLK_EDP_24M>,
<&cru SCLK_EDP>,
<&cru SCLK_HDCP>,
<&cru SCLK_ISP>,
<&cru SCLK_RGA>,
<&cru SCLK_HDMI_CEC>,
<&cru SCLK_HDMI_HDCP>;
};
/*
* Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
pd_video {
reg = <RK3368_PD_VIDEO>;
clocks = <&cru ACLK_VIDEO>,
<&cru HCLK_VIDEO>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
};
/*
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
pd_gpu_1 {
reg = <RK3368_PD_GPU_1>;
clocks = <&cru ACLK_GPU_CFG>,
<&cru ACLK_GPU_MEM>,
<&cru SCLK_GPU_CORE>;
};
};
};
pmugrf: syscon@ff738000 {