di: add di for sm1 bringup [1/1]

PD#SWPL-5865

Problem:
SM1 bring up

Solution:
add the chipid

Verify:
sm

Change-Id: I9b738efea210b4fb3deb2dab9de6a443aabadb53
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>

Conflicts:
	drivers/amlogic/media/deinterlace/deinterlace.c
	drivers/amlogic/media/deinterlace/deinterlace_dbg.c
	drivers/amlogic/media/deinterlace/deinterlace_hw.c
	drivers/amlogic/media/deinterlace/nr_drv.c
This commit is contained in:
Yong Qin
2019-03-22 20:41:15 +08:00
committed by Luan Yuan
parent dfb4226f14
commit 4e5bb4795a
4 changed files with 44 additions and 19 deletions

View File

@@ -129,7 +129,7 @@ static di_dev_t *de_devp;
static dev_t di_devno;
static struct class *di_clsp;
static const char version_s[] = "2019-03-14a";
static const char version_s[] = "2019-02-26a sm1 buring up test";
static int bypass_state = 1;
static int bypass_all;
@@ -5099,7 +5099,8 @@ de_post_process(void *arg, unsigned int zoom_start_x_lines,
is_meson_gxlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu() ||
is_meson_g12b_cpu()) {
is_meson_g12b_cpu() ||
is_meson_sm1_cpu()) {
di_post_read_reverse_irq(overturn, mc_pre_flag,
post_blend_en ? mcpre_en : false);
/* disable mc for first 2 fieldes mv unreliable */
@@ -5880,7 +5881,8 @@ static void di_unreg_process_irq(void)
afbc_reg_sw(false);
di_hw_uninit();
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()
|| is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
|| is_meson_g12a_cpu() || is_meson_g12b_cpu()
|| is_meson_tl1_cpu() || is_meson_sm1_cpu()) {
di_pre_gate_control(false, mcpre_en);
nr_gate_control(false);
} else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) {
@@ -5892,7 +5894,8 @@ static void di_unreg_process_irq(void)
if (mirror_disable) {
di_hw_disable(mcpre_en);
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()
|| is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
|| is_meson_g12a_cpu() || is_meson_g12b_cpu()
|| is_meson_tl1_cpu() || is_meson_sm1_cpu()) {
enable_di_post_mif(GATE_OFF);
di_post_gate_control(false);
di_top_gate_control(false, false);
@@ -6004,7 +6007,9 @@ static void di_pre_size_change(unsigned short width,
is_meson_gxlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu() ||
is_meson_g12b_cpu())
is_meson_g12b_cpu() ||
is_meson_tl1_cpu() ||
is_meson_sm1_cpu())
film_mode_win_config(width, height);
}
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL))
@@ -6436,7 +6441,9 @@ static int di_task_handle(void *data)
#endif
}
}
if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
if (is_meson_g12a_cpu() || is_meson_g12b_cpu()
|| is_meson_tl1_cpu() ||
is_meson_sm1_cpu()) {
#ifdef CLK_TREE_SUPPORT
clk_set_rate(de_devp->vpu_clkb,
de_devp->clkb_max_rate);
@@ -7383,7 +7390,9 @@ static void set_di_flag(void)
is_meson_gxlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu() ||
is_meson_g12b_cpu()) {
is_meson_g12b_cpu() ||
is_meson_tl1_cpu() ||
is_meson_sm1_cpu()) {
mcpre_en = true;
mc_mem_alloc = true;
pulldown_enable = false;
@@ -7400,7 +7409,9 @@ static void set_di_flag(void)
is_meson_gxlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu() ||
is_meson_g12b_cpu()) {
is_meson_g12b_cpu() ||
is_meson_tl1_cpu() ||
is_meson_sm1_cpu()) {
full_422_pack = true;
}
@@ -7411,7 +7422,9 @@ static void set_di_flag(void)
full_422_pack = false;
}
post_hold_line =
(is_meson_g12a_cpu() || is_meson_g12b_cpu())?10:17;
(is_meson_g12a_cpu() || is_meson_g12b_cpu()
|| is_meson_tl1_cpu() ||
is_meson_sm1_cpu())?10:17;
} else {
post_hold_line = 8; /*2019-01-10: from VLSI feijun*/
mcpre_en = false;

View File

@@ -253,7 +253,9 @@ void dump_di_reg_g12(void)
if (is_meson_txlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu() ||
is_meson_g12b_cpu())
is_meson_g12b_cpu() ||
is_meson_tl1_cpu() ||
is_meson_sm1_cpu())
base_addr = 0xff900000;
else
base_addr = 0xd0100000;

View File

@@ -466,7 +466,8 @@ void di_hw_init(bool pd_enable, bool mc_enable)
unsigned short fifo_size_di = 0xc0;
switch_vpu_clk_gate_vmod(VPU_VPU_CLKB, VPU_CLK_GATE_ON);
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()
|| is_meson_g12a_cpu() || is_meson_g12b_cpu())
|| is_meson_g12a_cpu() || is_meson_g12b_cpu()
|| is_meson_tl1_cpu() || is_meson_sm1_cpu())
di_top_gate_control(true, true);
else if (is_meson_gxl_cpu() || is_meson_gxm_cpu()
|| is_meson_gxlx_cpu())
@@ -479,7 +480,8 @@ void di_hw_init(bool pd_enable, bool mc_enable)
is_meson_gxlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu() ||
is_meson_g12b_cpu()) {
is_meson_g12b_cpu() || is_meson_sm1_cpu() ||
is_meson_tl1_cpu()) {
/* vpp fifo max size on txl :128*3=384[0x180] */
/* di fifo max size on txl :96*3=288[0x120] */
fifo_size_vpp = 0x180;
@@ -510,7 +512,8 @@ void di_hw_init(bool pd_enable, bool mc_enable)
if (is_meson_txlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu() ||
is_meson_g12b_cpu()) {
is_meson_g12b_cpu() || is_meson_sm1_cpu() ||
is_meson_tl1_cpu()) {
di_pre_gate_control(true, true);
di_post_gate_control(true);
}
@@ -527,8 +530,9 @@ void di_hw_init(bool pd_enable, bool mc_enable)
mc_di_param_init();
if (is_meson_txlx_cpu() ||
is_meson_txhd_cpu() ||
is_meson_g12a_cpu() ||
is_meson_g12b_cpu()) {
is_meson_g12a_cpu() || is_meson_sm1_cpu() ||
is_meson_g12b_cpu() ||
is_meson_tl1_cpu()) {
di_pre_gate_control(false, true);
di_post_gate_control(false);
di_top_gate_control(false, false);
@@ -1000,7 +1004,9 @@ bool afbc_is_supported(void)
}
#define AFBC_DEC_SEL (eAFBC_DEC1)
void enable_afbc_input(struct vframe_s *vf)
{
unsigned int r, u, v, w_aligned, h_aligned;
unsigned int out_height = 0;

View File

@@ -353,7 +353,8 @@ static void linebuffer_config(unsigned short width)
static void nr2_config(unsigned short width, unsigned short height)
{
if (is_meson_txlx_cpu() || is_meson_g12a_cpu() ||
is_meson_g12b_cpu()) {
is_meson_g12b_cpu() || is_meson_tl1_cpu() ||
is_meson_sm1_cpu()) {
DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 2, 1);
DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 15, 1);
DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 17, 1);
@@ -402,7 +403,8 @@ void nr_all_config(unsigned short width, unsigned short height,
if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXLX))
cue_config(nr_param.pcue_parm, field_type);
if (is_meson_txlx_cpu() || is_meson_g12a_cpu() ||
is_meson_g12b_cpu()) {
is_meson_g12b_cpu() || is_meson_tl1_cpu() ||
is_meson_sm1_cpu()) {
linebuffer_config(width);
nr4_config(nr_param.pnr4_parm, width, height);
}
@@ -782,7 +784,8 @@ void nr_process_in_irq(void)
if (dnr_en)
dnr_process(&dnr_param);
if (is_meson_txlx_cpu() || is_meson_g12a_cpu()
|| is_meson_g12a_cpu()) {
|| is_meson_g12a_cpu() || is_meson_tl1_cpu() ||
is_meson_sm1_cpu()) {
noise_meter_process(nr_param.pnr4_parm, nr_param.frame_count);
luma_enhancement_process(nr_param.pnr4_parm,
nr_param.frame_count);
@@ -1130,7 +1133,8 @@ void nr_hw_init(void)
void nr_gate_control(bool gate)
{
if (!is_meson_txlx_cpu() && !is_meson_g12a_cpu()
&& !is_meson_g12b_cpu())
&& !is_meson_g12b_cpu() && !is_meson_sm1_cpu()
&& !is_meson_tl1_cpu())
return;
if (gate) {
/* enable nr auto gate */