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media: rockchip: ispp: safe to enable shp/fec output
Change-Id: I7a05c561a909718125edc972b88f1de73d5f014d Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
@@ -996,6 +996,7 @@ static int start_ii(struct rkispp_stream *stream)
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static int config_ii(struct rkispp_stream *stream)
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{
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stream->is_cfg = true;
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return config_modules(stream->isppdev);
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}
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@@ -1005,10 +1006,41 @@ static int is_stopped_ii(struct rkispp_stream *stream)
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return true;
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}
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static void secure_config_mb(struct rkispp_stream *stream)
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{
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struct rkispp_device *dev = stream->isppdev;
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u32 limit_range;
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/* enable dma immediately, config in idle state */
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switch (stream->last_module) {
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case ISPP_MODULE_NR:
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case ISPP_MODULE_SHP:
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limit_range = (stream->out_fmt.quantization != V4L2_QUANTIZATION_LIM_RANGE) ?
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0 : SW_SHP_WR_YUV_LIMIT;
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rkispp_set_bits(dev, RKISPP_SHARP_CTRL,
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SW_SHP_WR_YUV_LIMIT | SW_SHP_WR_FORMAT_MASK,
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limit_range | stream->out_cap_fmt.wr_fmt);
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rkispp_clear_bits(dev, RKISPP_SHARP_CORE_CTRL, SW_SHP_DMA_DIS);
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break;
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case ISPP_MODULE_FEC:
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limit_range = (stream->out_fmt.quantization != V4L2_QUANTIZATION_LIM_RANGE) ?
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0 : SW_FEC_WR_YUV_LIMIT;
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rkispp_set_bits(dev, RKISPP_FEC_CTRL, SW_FEC_WR_YUV_LIMIT | FMT_WR_MASK,
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limit_range | stream->out_cap_fmt.wr_fmt << 4);
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rkispp_write(dev, RKISPP_FEC_PIC_SIZE,
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stream->out_fmt.height << 16 | stream->out_fmt.width);
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rkispp_clear_bits(dev, RKISPP_FEC_CORE_CTRL, SW_FEC2DDR_DIS);
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break;
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default:
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break;
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}
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stream->is_cfg = true;
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}
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static int config_mb(struct rkispp_stream *stream)
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{
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struct rkispp_device *dev = stream->isppdev;
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u32 i, limit_range, mult = 1;
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u32 i, mult = 1;
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for (i = ISPP_MODULE_FEC; i > 0; i = i >> 1) {
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if (dev->stream_vdev.module_ens & i)
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@@ -1037,12 +1069,6 @@ static int config_mb(struct rkispp_stream *stream)
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stream->config->reg.cur_vir_stride = RKISPP_SHARP_WR_VIR_STRIDE;
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stream->config->reg.cur_y_base_shd = RKISPP_SHARP_WR_Y_BASE_SHD;
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stream->config->reg.cur_uv_base_shd = RKISPP_SHARP_WR_UV_BASE_SHD;
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limit_range = (stream->out_fmt.quantization != V4L2_QUANTIZATION_LIM_RANGE) ?
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0 : SW_SHP_WR_YUV_LIMIT;
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rkispp_set_bits(dev, RKISPP_SHARP_CTRL,
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SW_SHP_WR_YUV_LIMIT | SW_SHP_WR_FORMAT_MASK,
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limit_range | stream->out_cap_fmt.wr_fmt);
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rkispp_clear_bits(dev, RKISPP_SHARP_CORE_CTRL, SW_SHP_DMA_DIS);
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break;
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default:
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stream->config->frame_end_id = FEC_INT;
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@@ -1051,19 +1077,15 @@ static int config_mb(struct rkispp_stream *stream)
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stream->config->reg.cur_vir_stride = RKISPP_FEC_WR_VIR_STRIDE;
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stream->config->reg.cur_y_base_shd = RKISPP_FEC_WR_Y_BASE_SHD;
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stream->config->reg.cur_uv_base_shd = RKISPP_FEC_WR_UV_BASE_SHD;
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limit_range = (stream->out_fmt.quantization != V4L2_QUANTIZATION_LIM_RANGE) ?
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0 : SW_FEC_WR_YUV_LIMIT;
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rkispp_set_bits(dev, RKISPP_FEC_CTRL, SW_FEC_WR_YUV_LIMIT | FMT_WR_MASK,
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limit_range | stream->out_cap_fmt.wr_fmt << 4);
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rkispp_write(dev, RKISPP_FEC_PIC_SIZE,
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stream->out_fmt.height << 16 | stream->out_fmt.width);
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rkispp_clear_bits(dev, RKISPP_FEC_CORE_CTRL, SW_FEC2DDR_DIS);
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}
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if (stream->out_cap_fmt.wr_fmt & FMT_YUYV)
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mult = 2;
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else if (stream->out_cap_fmt.wr_fmt & FMT_FBC)
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mult = 0;
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set_vir_stride(stream, ALIGN(stream->out_fmt.width * mult, 16) >> 2);
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if (dev->ispp_sdev.state == ISPP_STOP)
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secure_config_mb(stream);
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v4l2_dbg(1, rkispp_debug, &dev->v4l2_dev,
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"%s last module:%d\n", __func__, i);
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return 0;
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@@ -1150,6 +1172,7 @@ static int config_scl(struct rkispp_stream *stream)
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((stream->out_fmt.quantization != V4L2_QUANTIZATION_LIM_RANGE) ?
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0 : SW_SCL_WR_YUV_LIMIT);
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rkispp_set_bits(dev, stream->config->reg.ctrl, mask, val);
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stream->is_cfg = true;
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v4l2_dbg(1, rkispp_debug, &dev->v4l2_dev,
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"scl%d ctrl:0x%x stride:0x%x factor:0x%x\n",
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@@ -1520,6 +1543,7 @@ static int rkispp_start_streaming(struct vb2_queue *queue,
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return -EBUSY;
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stream->is_upd = false;
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stream->is_cfg = false;
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atomic_inc(&dev->stream_vdev.refcnt);
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if (!dev->inp || !stream->linked) {
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v4l2_err(&dev->v4l2_dev,
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@@ -1961,6 +1985,11 @@ static void fec_work_event(struct rkispp_device *dev,
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vdev->fec.cur_rd->timestamp;
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atomic_set(&dev->ispp_sdev.frm_sync_seq, seq);
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}
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stream = &vdev->stream[STREAM_MB];
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if (stream->streaming && !stream->is_cfg)
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secure_config_mb(stream);
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if (!dev->hw_dev->is_single)
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rkispp_update_regs(dev, RKISPP_FEC, RKISPP_FEC_CROP);
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writel(FEC_FORCE_UPD, base + RKISPP_CTRL_UPDATE);
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@@ -2124,6 +2153,10 @@ static void nr_work_event(struct rkispp_device *dev,
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}
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}
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stream = &vdev->stream[STREAM_MB];
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if (!is_fec_en && stream->streaming && !stream->is_cfg)
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secure_config_mb(stream);
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if (!dev->hw_dev->is_single)
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rkispp_update_regs(dev, RKISPP_NR, RKISPP_ORB_MAX_FEATURE);
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writel(OTHER_FORCE_UPD, base + RKISPP_CTRL_UPDATE);
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@@ -2379,7 +2412,7 @@ void rkispp_isr(u32 mis_val, struct rkispp_device *dev)
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for (i = 0; i < STREAM_MAX; i++) {
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stream = &vdev->stream[i];
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if (!stream->streaming ||
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if (!stream->streaming || !stream->is_cfg ||
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!(mis_val & INT_FRAME(stream)))
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continue;
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if (stream->stopping &&
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@@ -163,6 +163,7 @@ struct rkispp_stream {
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bool stopping;
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bool linked;
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bool is_upd;
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bool is_cfg;
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};
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/* rkispp stream device */
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