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PCI: rockchip: dw: fix UDMA logic

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Clear UDMA interrupt first before starting a new transfer. Otherwise,
the new interrupt corresponding to new transfer may be cleared
when clear the last interrupt which finally cause transfer timeout.

Change-Id: I4d232e41cdfaa68178cdd99942aefa717032c1b9
Signed-off-by: Simon Xue <xxm@rock-chips.com>
This commit is contained in:
Simon Xue
2020-12-17 11:15:48 +08:00
committed by Tao Huang
parent e1b9ba4215
commit 4eb691cb07
1 changed files with 5 additions and 2 deletions
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7
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -984,18 +984,21 @@ rk_pcie_handle_dma_interrupt(struct rk_pcie *rk_pcie)
static irqreturn_t rk_pcie_sys_irq_handler(int irq, void *arg)
{
struct rk_pcie *rk_pcie = arg;
u32 chn = rk_pcie->dma_obj->cur->chn;
u32 chn = 0;
union int_status status;
union int_clear clears;
status.asdword = dw_pcie_readl_dbi(rk_pcie->pci, PCIE_DMA_OFFSET +
PCIE_DMA_WR_INT_STATUS);
if (rk_pcie->dma_obj && rk_pcie->dma_obj->cur)
chn = rk_pcie->dma_obj->cur->chn;
if (status.donesta & BIT(0)) {
rk_pcie_handle_dma_interrupt(rk_pcie);
clears.doneclr = 0x1 << chn;
dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET +
PCIE_DMA_WR_INT_CLEAR, clears.asdword);
rk_pcie_handle_dma_interrupt(rk_pcie);
}
if (status.abortsta & BIT(0)) {