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Merge tag 'v5.16-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
mt8183: - add Acer Chromebook 314 - evb: add node to read thermisor from AUXIN0 - add several sku's for Lenovo IdeaPad Flex 3 Chromebook and ASUS Chromebook Detachable CM3 - update sensor mapping of the board temperature sensor - add some coresight nodes for CPU debugging - USB Type C connector description to all Chromebooks mt8192, mt8516: - smaller i2c related fixes mt8173: - enable backlight enable pin to all Chromebooks mt7986[a,b]: - add basic support * tag 'v5.16-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (21 commits) arm64: dts: mediatek: add pinctrl support for mt7986b arm64: dts: mediatek: add pinctrl support for mt7986a arm64: dts: mt8183: kukui: Add Type C node arm64: dts: mediatek: add basic mt7986 support dt-bindings: arm64: dts: mediatek: Add mt7986 series arm64: dts: mt8183: support coresight-cpu-debug for mt8183 arm64: dts: mediatek: mt8173-elm: Add backlight enable pin config arm64: dts: mediatek: mt8173-elm: Move pwm pinctrl to pwm0 node arm64: dts: mt8183-kukui: Update Tboard sensor mapping table arm64: dts: mediatek: mt8173: Add gce-client-reg to display od/ufo dt-bindings: arm64: dts: mediatek: Add sku22 for mt8183 kakadu board dt-bindings: arm64: dts: mediatek: Add more SKUs for mt8183 fennel board dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-cozmo arm64: dts: mt8183: Add kakadu sku22 arm64: dts: mt8183: Add more fennel SKUs arm64: dts: mt8183: Add kukui-jacuzzi-cozmo board arm64: dts: mt8183: jacuzzi: remove unused ddc-i2c-bus arm64: dts: mediatek: mt8183-evb: Add node for thermistor arm64: dts: mediatek: mt8516: remove 2 invalid i2c clocks arm64: dts: mediatek: mt8192: fix i2c node names ... Link: https://lore.kernel.org/r/0d05e8b6-c56f-bad7-00c1-44682cedb38f@suse.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -77,6 +77,14 @@ properties:
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- enum:
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- mediatek,mt7629-rfb
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- const: mediatek,mt7629
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- items:
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- enum:
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- mediatek,mt7986a-rfb
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- const: mediatek,mt7986a
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- items:
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- enum:
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- mediatek,mt7986b-rfb
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- const: mediatek,mt7986b
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- items:
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- enum:
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- mediatek,mt8127-moose
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@@ -134,6 +142,10 @@ properties:
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- google,krane-sku176
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- const: google,krane
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- const: mediatek,mt8183
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- description: Google Cozmo (Acer Chromebook 314)
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items:
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- const: google,cozmo
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- const: mediatek,mt8183
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- description: Google Damu (ASUS Chromebook Flip CM3)
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items:
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- const: google,damu
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@@ -143,7 +155,9 @@ properties:
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- enum:
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- google,fennel-sku0
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- google,fennel-sku1
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- google,fennel-sku2
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- google,fennel-sku6
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- google,fennel-sku7
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- const: google,fennel
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- const: mediatek,mt8183
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- description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
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@@ -159,6 +173,12 @@ properties:
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- const: google,kakadu-rev2
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- const: google,kakadu
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- const: mediatek,mt8183
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- description: Google Kakadu (ASUS Chromebook Detachable CM3)
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items:
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- const: google,kakadu-rev3-sku22
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- const: google,kakadu-rev2-sku22
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- const: google,kakadu
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- const: mediatek,mt8183
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- description: Google Kappa (HP Chromebook 11a)
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items:
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- const: google,kappa
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@@ -7,6 +7,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
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@@ -14,16 +16,20 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
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57
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
Normal file
57
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
Normal file
@@ -0,0 +1,57 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7986a.dtsi"
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/ {
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model = "MediaTek MT7986a RFB";
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compatible = "mediatek,mt7986a-rfb";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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reg = <0 0x40000000 0 0x40000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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&pio {
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uart1_pins: uart1-pins {
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mux {
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function = "uart";
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groups = "uart1";
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};
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};
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uart2_pins: uart2-pins {
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mux {
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function = "uart";
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groups = "uart2";
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};
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};
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};
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169
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
Normal file
169
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
Normal file
@@ -0,0 +1,169 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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system_clk: dummy40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x0>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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#cooling-cells = <2>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x30000>;
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no-map;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x10000>, /* GICD */
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<0 0x0c080000 0 0x80000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7986-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x1001c000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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status = "disabled";
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};
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pio: pinctrl@1001f000 {
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compatible = "mediatek,mt7986a-pinctrl";
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reg = <0 0x1001f000 0 0x1000>,
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<0 0x11c30000 0 0x1000>,
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<0 0x11c40000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11e30000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x11f10000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
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"iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 100>;
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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};
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trng: trng@1020f000 {
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compatible = "mediatek,mt7986-rng",
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"mediatek,mt7623-rng";
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reg = <0 0x1020f000 0 0x100>;
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clocks = <&system_clk>;
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clock-names = "rng";
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
|
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&system_clk>;
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status = "disabled";
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};
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uart1: serial@11003000 {
|
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compatible = "mediatek,mt7986-uart",
|
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
|
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&system_clk>;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
|
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reg = <0 0x11004000 0 0x400>;
|
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&system_clk>;
|
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status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
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29
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
Normal file
29
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
Normal file
@@ -0,0 +1,29 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2021 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
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/dts-v1/;
|
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#include "mt7986b.dtsi"
|
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|
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/ {
|
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model = "MediaTek MT7986b RFB";
|
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compatible = "mediatek,mt7986b-rfb";
|
||||
|
||||
aliases {
|
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serial0 = &uart0;
|
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};
|
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|
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chosen {
|
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stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
12
arch/arm64/boot/dts/mediatek/mt7986b.dtsi
Normal file
12
arch/arm64/boot/dts/mediatek/mt7986b.dtsi
Normal file
@@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2021 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#include "mt7986a.dtsi"
|
||||
|
||||
&pio {
|
||||
compatible = "mediatek,mt7986b-pinctrl";
|
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gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
|
||||
};
|
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@@ -28,7 +28,7 @@
|
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enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
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pinctrl-0 = <&disp_pwm0_pins>;
|
||||
pinctrl-0 = <&panel_backlight_en_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -827,6 +827,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
panel_backlight_en_pins: panel_backlight_en_pins {
|
||||
pins1 {
|
||||
pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>;
|
||||
};
|
||||
};
|
||||
|
||||
panel_fixed_pins: panel_fixed_pins {
|
||||
pins1 {
|
||||
pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
|
||||
@@ -901,6 +907,8 @@
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&disp_pwm0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -1212,6 +1212,7 @@
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
@@ -1316,6 +1317,7 @@
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
|
||||
};
|
||||
|
||||
hdmi0: hdmi@14025000 {
|
||||
|
||||
@@ -36,6 +36,14 @@
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
ntc@0 {
|
||||
compatible = "murata,ncp03wf104";
|
||||
pullup-uv = <1800000>;
|
||||
pullup-ohm = <390000>;
|
||||
pulldown-ohm = <0>;
|
||||
io-channels = <&auxadc 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&auxadc {
|
||||
|
||||
36
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
Normal file
36
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
Normal file
@@ -0,0 +1,36 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8183-kukui-jacuzzi.dtsi"
|
||||
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google cozmo board";
|
||||
compatible = "google,cozmo", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
&i2c_tunnel {
|
||||
google,remote-bus = <0>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
trackpad@2c {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x2c>;
|
||||
hid-descr-addr = <0x20>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&trackpad_pins>;
|
||||
|
||||
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&qca_wifi {
|
||||
qcom,ath10k-calibration-variant = "GO_COZMO";
|
||||
};
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
|
||||
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google fennel sku1 board";
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
|
||||
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google fennel sku6 board";
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
|
||||
#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google fennel sku7 board";
|
||||
compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
status = "okay";
|
||||
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x10>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&touchscreen_pins>;
|
||||
|
||||
post-power-on-delay-ms = <10>;
|
||||
hid-descr-addr = <0x0001>;
|
||||
};
|
||||
|
||||
|
||||
&qca_wifi {
|
||||
qcom,ath10k-calibration-variant = "GO_FENNEL";
|
||||
};
|
||||
|
||||
@@ -5,7 +5,6 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8183-kukui-jacuzzi.dtsi"
|
||||
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
|
||||
|
||||
&mt6358codec {
|
||||
mediatek,dmic-mode = <1>; /* one-wire */
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
|
||||
#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google fennel14 sku2 board";
|
||||
compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
&qca_wifi {
|
||||
qcom,ath10k-calibration-variant = "GO_FENNEL14";
|
||||
};
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
|
||||
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google fennel14 sku0 board";
|
||||
|
||||
@@ -9,7 +9,6 @@
|
||||
panel: panel {
|
||||
compatible = "auo,b116xw03";
|
||||
power-supply = <&pp3300_panel>;
|
||||
ddc-i2c-bus = <&i2c4>;
|
||||
backlight = <&backlight_lcd0>;
|
||||
|
||||
port {
|
||||
|
||||
19
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
Normal file
19
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
Normal file
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright 2021 Google LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8183-kukui-kakadu.dtsi"
|
||||
#include "mt8183-kukui-audio-rt1015p.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MediaTek kakadu board sku22";
|
||||
compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
|
||||
"google,kakadu", "mediatek,mt8183";
|
||||
};
|
||||
|
||||
&sound {
|
||||
compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
|
||||
};
|
||||
|
||||
@@ -157,33 +157,33 @@
|
||||
#thermal-sensor-cells = <0>;
|
||||
io-channels = <&auxadc 0>;
|
||||
io-channel-names = "sensor-channel";
|
||||
temperature-lookup-table = < (-5000) 4241
|
||||
0 4063
|
||||
5000 3856
|
||||
10000 3621
|
||||
15000 3364
|
||||
20000 3091
|
||||
25000 2810
|
||||
30000 2526
|
||||
35000 2247
|
||||
40000 1982
|
||||
45000 1734
|
||||
50000 1507
|
||||
55000 1305
|
||||
60000 1122
|
||||
65000 964
|
||||
70000 827
|
||||
75000 710
|
||||
80000 606
|
||||
85000 519
|
||||
90000 445
|
||||
95000 382
|
||||
100000 330
|
||||
105000 284
|
||||
110000 245
|
||||
115000 213
|
||||
120000 183
|
||||
125000 161>;
|
||||
temperature-lookup-table = < (-5000) 1553
|
||||
0 1488
|
||||
5000 1412
|
||||
10000 1326
|
||||
15000 1232
|
||||
20000 1132
|
||||
25000 1029
|
||||
30000 925
|
||||
35000 823
|
||||
40000 726
|
||||
45000 635
|
||||
50000 552
|
||||
55000 478
|
||||
60000 411
|
||||
65000 353
|
||||
70000 303
|
||||
75000 260
|
||||
80000 222
|
||||
85000 190
|
||||
90000 163
|
||||
95000 140
|
||||
100000 121
|
||||
105000 104
|
||||
110000 90
|
||||
115000 78
|
||||
120000 67
|
||||
125000 59>;
|
||||
};
|
||||
|
||||
tboard_thermistor2: thermal-sensor2 {
|
||||
@@ -191,33 +191,33 @@
|
||||
#thermal-sensor-cells = <0>;
|
||||
io-channels = <&auxadc 1>;
|
||||
io-channel-names = "sensor-channel";
|
||||
temperature-lookup-table = < (-5000) 4241
|
||||
0 4063
|
||||
5000 3856
|
||||
10000 3621
|
||||
15000 3364
|
||||
20000 3091
|
||||
25000 2810
|
||||
30000 2526
|
||||
35000 2247
|
||||
40000 1982
|
||||
45000 1734
|
||||
50000 1507
|
||||
55000 1305
|
||||
60000 1122
|
||||
65000 964
|
||||
70000 827
|
||||
75000 710
|
||||
80000 606
|
||||
85000 519
|
||||
90000 445
|
||||
95000 382
|
||||
100000 330
|
||||
105000 284
|
||||
110000 245
|
||||
115000 213
|
||||
120000 183
|
||||
125000 161>;
|
||||
temperature-lookup-table = < (-5000) 1553
|
||||
0 1488
|
||||
5000 1412
|
||||
10000 1326
|
||||
15000 1232
|
||||
20000 1132
|
||||
25000 1029
|
||||
30000 925
|
||||
35000 823
|
||||
40000 726
|
||||
45000 635
|
||||
50000 552
|
||||
55000 478
|
||||
60000 411
|
||||
65000 353
|
||||
70000 303
|
||||
75000 260
|
||||
80000 222
|
||||
85000 190
|
||||
90000 163
|
||||
95000 140
|
||||
100000 121
|
||||
105000 104
|
||||
110000 90
|
||||
115000 78
|
||||
120000 67
|
||||
125000 59>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -813,7 +813,7 @@
|
||||
|
||||
cros_ec {
|
||||
compatible = "google,cros-ec-rpmsg";
|
||||
mtk,rpmsg-name = "cros-ec-rpmsg";
|
||||
mediatek,rpmsg-name = "cros-ec-rpmsg";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -886,6 +886,20 @@
|
||||
cbas {
|
||||
compatible = "google,cros-cbas";
|
||||
};
|
||||
|
||||
typec {
|
||||
compatible = "google,cros-ec-typec";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb_c0: connector@0 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <0>;
|
||||
power-role = "dual";
|
||||
data-role = "host";
|
||||
try-power-role = "sink";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -367,6 +367,70 @@
|
||||
reg = <0 0x0c530a80 0 0x50>;
|
||||
};
|
||||
|
||||
cpu_debug0: cpu-debug@d410000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0xd410000 0x0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
cpu_debug1: cpu-debug@d510000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0xd510000 0x0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
cpu_debug2: cpu-debug@d610000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0xd610000 0x0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
cpu_debug3: cpu-debug@d710000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0xd710000 0x0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
|
||||
cpu_debug4: cpu-debug@d810000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0xd810000 0x0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
|
||||
cpu_debug5: cpu-debug@d910000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0xd910000 0x0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
|
||||
cpu_debug6: cpu-debug@da10000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0xda10000 0x0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
|
||||
cpu_debug7: cpu-debug@db10000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0xdb10000 0x0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
|
||||
clock-names = "apb_pclk";
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8183-topckgen", "syscon";
|
||||
reg = <0 0x10000000 0 0x1000>;
|
||||
|
||||
@@ -479,7 +479,7 @@
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c3: i2c3@11cb0000 {
|
||||
i2c3: i2c@11cb0000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11cb0000 0 0x1000>,
|
||||
<0 0x10217300 0 0x80>;
|
||||
@@ -498,7 +498,7 @@
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c7: i2c7@11d00000 {
|
||||
i2c7: i2c@11d00000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11d00000 0 0x1000>,
|
||||
<0 0x10217600 0 0x180>;
|
||||
@@ -511,7 +511,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c8@11d01000 {
|
||||
i2c8: i2c@11d01000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11d01000 0 0x1000>,
|
||||
<0 0x10217780 0 0x180>;
|
||||
@@ -524,7 +524,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c9: i2c9@11d02000 {
|
||||
i2c9: i2c@11d02000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11d02000 0 0x1000>,
|
||||
<0 0x10217900 0 0x180>;
|
||||
@@ -543,7 +543,7 @@
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c1: i2c1@11d20000 {
|
||||
i2c1: i2c@11d20000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11d20000 0 0x1000>,
|
||||
<0 0x10217100 0 0x80>;
|
||||
@@ -556,7 +556,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c2@11d21000 {
|
||||
i2c2: i2c@11d21000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11d21000 0 0x1000>,
|
||||
<0 0x10217180 0 0x180>;
|
||||
@@ -569,7 +569,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c4@11d22000 {
|
||||
i2c4: i2c@11d22000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11d22000 0 0x1000>,
|
||||
<0 0x10217380 0 0x180>;
|
||||
@@ -588,7 +588,7 @@
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c5: i2c5@11e00000 {
|
||||
i2c5: i2c@11e00000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11e00000 0 0x1000>,
|
||||
<0 0x10217500 0 0x80>;
|
||||
@@ -607,7 +607,7 @@
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c0@11f00000 {
|
||||
i2c0: i2c@11f00000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11f00000 0 0x1000>,
|
||||
<0 0x10217080 0 0x80>;
|
||||
@@ -620,7 +620,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c6@11f01000 {
|
||||
i2c6: i2c@11f01000 {
|
||||
compatible = "mediatek,mt8192-i2c";
|
||||
reg = <0 0x11f01000 0 0x1000>,
|
||||
<0 0x10217580 0 0x80>;
|
||||
|
||||
@@ -345,14 +345,9 @@
|
||||
reg = <0 0x11009000 0 0x90>,
|
||||
<0 0x11000180 0 0x80>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
|
||||
<&infracfg CLK_IFR_I2C0_SEL>,
|
||||
<&topckgen CLK_TOP_I2C0>,
|
||||
clocks = <&topckgen CLK_TOP_I2C0>,
|
||||
<&topckgen CLK_TOP_APDMA>;
|
||||
clock-names = "main-source",
|
||||
"main-sel",
|
||||
"main",
|
||||
"dma";
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@@ -364,14 +359,9 @@
|
||||
reg = <0 0x1100a000 0 0x90>,
|
||||
<0 0x11000200 0 0x80>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
|
||||
<&infracfg CLK_IFR_I2C1_SEL>,
|
||||
<&topckgen CLK_TOP_I2C1>,
|
||||
clocks = <&topckgen CLK_TOP_I2C1>,
|
||||
<&topckgen CLK_TOP_APDMA>;
|
||||
clock-names = "main-source",
|
||||
"main-sel",
|
||||
"main",
|
||||
"dma";
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
@@ -383,14 +373,9 @@
|
||||
reg = <0 0x1100b000 0 0x90>,
|
||||
<0 0x11000280 0 0x80>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
|
||||
<&infracfg CLK_IFR_I2C2_SEL>,
|
||||
<&topckgen CLK_TOP_I2C2>,
|
||||
clocks = <&topckgen CLK_TOP_I2C2>,
|
||||
<&topckgen CLK_TOP_APDMA>;
|
||||
clock-names = "main-source",
|
||||
"main-sel",
|
||||
"main",
|
||||
"dma";
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
Reference in New Issue
Block a user