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pcie: fix check linkup timeout bug when pcie resume.
PD#169779: pcie: fix check linkup timeout bug when pcie resume. Change-Id: Ia648c63447f101b71ae84dd960c0f414b80cbd32 Signed-off-by: Yue Wang <yue.wang@amlogic.com>
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@@ -554,8 +554,16 @@ static int amlogic_pcie_link_up(struct pcie_port *pp)
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u32 speed_okay = 0;
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u32 current_data_rate;
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int cnt = 0;
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u32 val = 0;
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u32 linkup = 0;
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struct amlogic_pcie *amlogic_pcie = to_amlogic_pcie(pp);
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val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
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linkup = ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
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(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
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if (linkup)
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return linkup;
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while (smlh_up == 0 || rdlh_up == 0
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|| ltssm_up == 0 || speed_okay == 0) {
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udelay(20);
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@@ -514,8 +514,16 @@ int amlogic_pcie_link_up(struct pcie_port *pp)
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u32 speed_okay = 0;
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u32 current_data_rate;
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int cnt = 0;
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u32 val = 0;
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u32 linkup = 0;
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struct amlogic_pcie *amlogic_pcie = to_amlogic_pcie(pp);
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val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
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linkup = ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
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(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
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if (linkup)
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return linkup;
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while (smlh_up == 0 || rdlh_up == 0
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|| ltssm_up == 0 || speed_okay == 0) {
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udelay(20);
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@@ -33,6 +33,12 @@
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#define PCIE_CFG_STATUS12 0x30
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#define PCIE_CFG_STATUS17 0x44
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/* PCIe Port Logic registers */
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#define PLR_OFFSET 0x700
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#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
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#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
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#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
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#define WAIT_LINKUP_TIMEOUT 2000
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enum pcie_data_rate {
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