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rockchip:midgard:1,update version to r4p1-02dev0 2,disable ve configuration when CONFIG_MALI_DEBUG enabled 3,device driver version to 2

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This commit is contained in:
xxm
2014-06-12 14:44:51 +08:00
parent a05c3a3973
commit 511fc892af
26 changed files with 191 additions and 139 deletions
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8
drivers/gpu/arm/midgard/Kbuild
View File

@@ -15,7 +15,7 @@
# Driver version string which is returned to userspace via an ioctl
MALI_RELEASE_NAME ?= "r4p1-01dev0"
MALI_RELEASE_NAME ?= "r4p1-02dev0"
# Paths required for build
KBASE_PATH = $(src)
@@ -66,9 +66,11 @@ else
DEFINES +=-DMALI_KBASE_THIRDPARTY_PATH=$(src)/platform/$(CONFIG_MALI_PLATFORM_THIRDPARTY_NAME)
endif
DEFINES += -I$(srctree)/drivers/staging/android
# Use our defines when compiling
ccflags-y += $(DEFINES) -I$(KBASE_PATH) -I$(KBASE_PLATFORM_PATH) -I$(UMP_PATH) -I$(srctree)/drivers/staging/android
subdir-ccflags-y += $(DEFINES) -I$(KBASE_PATH) -I$(KBASE_PLATFORM_PATH) -I$(OSK_PATH) -I$(UMP_PATH)
ccflags-y += $(DEFINES) -I$(KBASE_PATH) -I$(KBASE_PLATFORM_PATH) -I$(UMP_PATH) -I$(srctree)/include/linux
subdir-ccflags-y += $(DEFINES) -I$(KBASE_PATH) -I$(KBASE_PLATFORM_PATH) -I$(OSK_PATH) -I$(UMP_PATH) -I$(srctree)/include/linux
SRC := \
mali_kbase_device.c \

62
drivers/gpu/arm/midgard/mali_base_hwconfig.h
View File

@@ -235,7 +235,7 @@ typedef enum base_hw_issue {
/* sometimes HW doesn't invalidate cached VPDs when it has to */
BASE_HW_ISSUE_10684,
/* Chicken bit on (t67x_r1p0 and t72x) to work for a HW workaround in compiler */
/* Chicken bit on t72x to work for a HW workaround in compiler */
BASE_HW_ISSUE_10797,
/* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */
@@ -281,30 +281,9 @@ typedef enum base_hw_issue {
/* Partial 16xMSAA support */
BASE_HW_ISSUE_T76X_26,
/* Forward pixel kill doesn't work with MRT */
BASE_HW_ISSUE_T76X_2121,
/* CRC not working with MFBD and more than one render target */
BASE_HW_ISSUE_T76X_2315,
/* Some indexed formats not supported for MFBD preload. */
BASE_HW_ISSUE_T76X_2686,
/* Must disable CRC if the tile output size is 8 bytes or less. */
BASE_HW_ISSUE_T76X_2712,
/* DBD clean pixel enable bit is reserved */
BASE_HW_ISSUE_T76X_2772,
/* AFBC is not supported for T76X beta. */
BASE_HW_ISSUE_T76X_2906,
/* RTD doesn't specify the row stride for AFBC surfaces. */
BASE_HW_ISSUE_T76X_3086,
/* Prevent MMU deadlock for T76X beta. */
BASE_HW_ISSUE_T76X_3285,
/* Clear encoder state for a hard stopped fragment job which is AFBC
* encoded by soft resetting the GPU. Only for T76X r0p0, r0p1 and r0p1_50rel0
*/
@@ -318,9 +297,6 @@ typedef enum base_hw_issue {
/* T76X cannot disable uses_discard even if depth and stencil are read-only. */
BASE_HW_ISSUE_T76X_3700,
/* ST_TILEBUFFER is not supported on T76X-r0p0-beta */
BASE_HW_ISSUE_T76X_3759,
/* Preload ignores any size or bounding box restrictions of the output image. */
BASE_HW_ISSUE_T76X_3793,
@@ -515,8 +491,9 @@ static const base_hw_issue base_hw_issues_t62x_r1p0[] = {
BASE_HW_ISSUE_END
};
/* Mali T67x r1p0 */
static const base_hw_issue base_hw_issues_t67x_r1p0[] = {
/* Mali T62x r1p1 */
static const base_hw_issue base_hw_issues_t62x_r1p1[] =
{
BASE_HW_ISSUE_6402,
BASE_HW_ISSUE_8803,
BASE_HW_ISSUE_9435,
@@ -524,41 +501,12 @@ static const base_hw_issue base_hw_issues_t67x_r1p0[] = {
BASE_HW_ISSUE_10472,
BASE_HW_ISSUE_10649,
BASE_HW_ISSUE_10684,
BASE_HW_ISSUE_10797,
BASE_HW_ISSUE_10821,
BASE_HW_ISSUE_10883,
BASE_HW_ISSUE_10931,
BASE_HW_ISSUE_10946,
BASE_HW_ISSUE_10959,
BASE_HW_ISSUE_11012,
BASE_HW_ISSUE_11020,
BASE_HW_ISSUE_11024,
/* List of hardware issues must end with BASE_HW_ISSUE_END */
BASE_HW_ISSUE_END
};
/* Mali T76x r0p0 beta */
static const base_hw_issue base_hw_issues_t76x_r0p0_beta[] = {
BASE_HW_ISSUE_8803,
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_10649,
BASE_HW_ISSUE_10821,
BASE_HW_ISSUE_10883,
BASE_HW_ISSUE_10946,
BASE_HW_ISSUE_10959,
BASE_HW_ISSUE_11020,
BASE_HW_ISSUE_11024,
BASE_HW_ISSUE_T76X_26,
BASE_HW_ISSUE_T76X_2121,
BASE_HW_ISSUE_T76X_2315,
BASE_HW_ISSUE_T76X_2686,
BASE_HW_ISSUE_T76X_2712,
BASE_HW_ISSUE_T76X_2772,
BASE_HW_ISSUE_T76X_2906,
BASE_HW_ISSUE_T76X_3285,
BASE_HW_ISSUE_T76X_3700,
BASE_HW_ISSUE_T76X_3759,
BASE_HW_ISSUE_T76X_3793,
/* List of hardware issues must end with BASE_HW_ISSUE_END */
BASE_HW_ISSUE_END
};
@@ -612,6 +560,7 @@ static const base_hw_issue base_hw_issues_t76x_r0p1_50rel0[] = {
BASE_HW_ISSUE_10883,
BASE_HW_ISSUE_10946,
BASE_HW_ISSUE_T76X_26,
BASE_HW_ISSUE_T76X_3086,
BASE_HW_ISSUE_T76X_3542,
BASE_HW_ISSUE_T76X_3556,
BASE_HW_ISSUE_T76X_3700,
@@ -649,6 +598,7 @@ static const base_hw_issue base_hw_issues_t76x_r0p3[] = {
BASE_HW_ISSUE_10883,
BASE_HW_ISSUE_10946,
BASE_HW_ISSUE_T76X_26,
BASE_HW_ISSUE_T76X_3086,
BASE_HW_ISSUE_T76X_3542,
BASE_HW_ISSUE_T76X_3556,
BASE_HW_ISSUE_T76X_3700,

3
drivers/gpu/arm/midgard/mali_kbase_context.c
View File

@@ -27,6 +27,7 @@
#define MEMPOOL_PAGES 16384
/**
* @brief Create a kernel base context.
*
@@ -125,7 +126,7 @@ free_jd:
free_allocator:
kbase_mem_allocator_term(&kctx->osalloc);
free_kctx:
vfree(kctx);
vfree(kctx);
out:
return NULL;

7
drivers/gpu/arm/midgard/mali_kbase_core_linux.c
View File

@@ -85,7 +85,7 @@ EXPORT_SYMBOL(shared_kernel_test_data);
#endif /* MALI_UNIT_TEST */
#define KBASE_DRV_NAME "mali"
#define ROCKCHIP_VERSION 1
#define ROCKCHIP_VERSION 2
static const char kbase_drv_name[] = KBASE_DRV_NAME;
static int kbase_dev_nr;
@@ -3020,11 +3020,6 @@ module_exit(kbase_driver_exit);
MODULE_LICENSE("GPL");
MODULE_VERSION(MALI_RELEASE_NAME);
/* Module parameter to control log level */
int mali_debug_level = 0;
module_param(mali_debug_level, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH); /* rw-rw-r-- */
MODULE_PARM_DESC(mali_debug_level, "Higher number, more dmesg output");
#ifdef CONFIG_MALI_GATOR_SUPPORT
/* Create the trace points (otherwise we just get code to call a tracepoint) */
#define CREATE_TRACE_POINTS

24
drivers/gpu/arm/midgard/mali_kbase_debug.h
View File

@@ -22,30 +22,6 @@
#include <linux/bug.h>
extern int mali_debug_level;
/**
* @def KBASEP_LOG(level, ...)
* @brief Logs a debug message using dev_dbg().
*
* Logs a debug message using dev_dbg if the debug level specified for the
* message is lower or equal than the current debug level. Use higher
* numbers to log messages with increasing verbosity.
*
* The current debug level is controlled by the module parameter
* 'mali_debug_level' which is 0 by default.
*
* No special meaning is assigned to debug levels but the recommendation is
* 0 = driver init/exit messages
* 1 = function entry/exit messages
* 2 = function detailed messages
* 3 = irq/callback messages
* 4 = register read/write messages
*
* @param level debug level for the message
* @param ... Arguments you would normally pass to dev_dbg()
*/
#define KBASE_LOG(level, ...) if ((level) <= mali_debug_level) dev_dbg(__VA_ARGS__)
/** @brief If equals to 0, a trace containing the file, line, and function will be displayed before each message. */
#define KBASE_DEBUG_SKIP_TRACE 0

1
drivers/gpu/arm/midgard/mali_kbase_defs.h
View File

@@ -42,7 +42,6 @@
#endif /* CONFIG_KDS */
#ifdef CONFIG_SYNC
//#include <linux/sync.h>
#include "sync.h"
#endif /* CONFIG_SYNC */

9
drivers/gpu/arm/midgard/mali_kbase_hw.c
View File

@@ -79,13 +79,9 @@ mali_error kbase_hw_set_issues_mask(kbase_device *kbdev)
case GPU_ID_MAKE(GPU_ID_PI_T62X, 1, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T62X, 1, 0, 1):
issues = base_hw_issues_t62x_r1p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T67X, 1, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T67X, 1, 0, 1):
issues = base_hw_issues_t67x_r1p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T76X, 0, 0, 0):
issues = base_hw_issues_t76x_r0p0_beta;
case GPU_ID_MAKE(GPU_ID_PI_T62X, 1, 1, 0):
issues = base_hw_issues_t62x_r1p1;
break;
case GPU_ID_MAKE(GPU_ID_PI_T76X, 0, 0, 1):
issues = base_hw_issues_t76x_r0p0;
@@ -122,7 +118,6 @@ mali_error kbase_hw_set_issues_mask(kbase_device *kbdev)
switch (gpu_id >> GPU_ID_VERSION_PRODUCT_ID_SHIFT) {
case GPU_ID_PI_T60X:
case GPU_ID_PI_T62X:
case GPU_ID_PI_T67X:
issues = base_hw_issues_model_t6xx;
break;
case GPU_ID_PI_T72X:

13
drivers/gpu/arm/midgard/mali_kbase_jd.c
View File

@@ -834,6 +834,7 @@ mali_bool jd_submit_atom(kbase_context *kctx,
katom->nr_extres = user_atom->nr_extres;
katom->extres = NULL;
katom->device_nr = user_atom->device_nr;
katom->affinity = 0;
katom->jc = user_atom->jc;
katom->coreref_state = KBASE_ATOM_COREREF_STATE_NO_CORES_REQUESTED;
@@ -897,14 +898,22 @@ mali_bool jd_submit_atom(kbase_context *kctx,
katom->status = KBASE_JD_ATOM_STATE_QUEUED;
/* Reject atoms with job chain = NULL, as these cause issues with soft-stop */
if (0 == katom->jc && (katom->core_req & BASEP_JD_REQ_ATOM_TYPE) != BASE_JD_REQ_DEP)
{
if (0 == katom->jc && (katom->core_req & BASEP_JD_REQ_ATOM_TYPE) != BASE_JD_REQ_DEP) {
dev_warn(kctx->kbdev->dev, "Rejecting atom with jc = NULL");
katom->event_code = BASE_JD_EVENT_JOB_INVALID;
ret = jd_done_nolock(katom);
goto out;
}
/* Reject atoms with an invalid device_nr */
if ((katom->core_req & BASE_JD_REQ_SPECIFIC_COHERENT_GROUP) &&
(katom->device_nr >= kctx->kbdev->gpu_props.num_core_groups)) {
dev_warn(kctx->kbdev->dev, "Rejecting atom with invalid device_nr %d", katom->device_nr);
katom->event_code = BASE_JD_EVENT_JOB_INVALID;
ret = jd_done_nolock(katom);
goto out;
}
/*
* If the priority is increased we need to check the caller has security caps to do this, if
* priority is decreased then this is ok as the result will have no negative impact on other

20
drivers/gpu/arm/midgard/mali_kbase_jm.c
View File

@@ -146,11 +146,31 @@ static void kbase_job_hw_submit(kbase_device *kbdev, kbase_jd_atom *katom, int j
void kbase_job_submit_nolock(kbase_device *kbdev, kbase_jd_atom *katom, int js)
{
kbase_jm_slot *jm_slots;
base_jd_core_req core_req;
KBASE_DEBUG_ASSERT(kbdev);
KBASE_DEBUG_ASSERT(katom);
jm_slots = kbdev->jm_slots;
core_req = katom->core_req;
if (core_req & BASE_JD_REQ_ONLY_COMPUTE) {
unsigned long flags;
int device_nr = (core_req & BASE_JD_REQ_SPECIFIC_COHERENT_GROUP) ? katom->device_nr : 0;
KBASE_DEBUG_ASSERT(device_nr < 2);
spin_lock_irqsave(&kbdev->pm.metrics.lock, flags);
kbasep_pm_record_job_status(kbdev);
kbdev->pm.metrics.active_cl_ctx[device_nr]++;
spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags);
} else {
unsigned long flags;
spin_lock_irqsave(&kbdev->pm.metrics.lock, flags);
kbasep_pm_record_job_status(kbdev);
kbdev->pm.metrics.active_gl_ctx++;
spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags);
}
/*
* We can have:
* - one job already done (pending interrupt),

1
drivers/gpu/arm/midgard/mali_kbase_js.h
View File

@@ -752,6 +752,7 @@ static INLINE void kbasep_js_atom_retained_state_copy(kbasep_js_atom_retained_st
retained_state->event_code = katom->event_code;
retained_state->core_req = katom->core_req;
retained_state->retry_submit_on_slot = katom->retry_submit_on_slot;
retained_state->device_nr = katom->device_nr;
}
/**

21
drivers/gpu/arm/midgard/mali_kbase_js_ctx_attr.c
View File

@@ -295,10 +295,27 @@ mali_bool kbasep_js_ctx_attr_ctx_release_atom(kbase_device *kbdev, kbase_context
if (kbasep_js_atom_retained_state_is_valid(katom_retained_state) == MALI_FALSE)
return MALI_FALSE;
if (core_req & BASE_JD_REQ_ONLY_COMPUTE)
if (core_req & BASE_JD_REQ_ONLY_COMPUTE) {
unsigned long flags;
int device_nr = (core_req & BASE_JD_REQ_SPECIFIC_COHERENT_GROUP) ? katom_retained_state->device_nr : 0;
KBASE_DEBUG_ASSERT(device_nr < 2);
spin_lock_irqsave(&kbdev->pm.metrics.lock, flags);
kbasep_pm_record_job_status(kbdev);
kbdev->pm.metrics.active_cl_ctx[device_nr]--;
spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags);
runpool_state_changed |= kbasep_js_ctx_attr_ctx_release_attr(kbdev, kctx, KBASEP_JS_CTX_ATTR_COMPUTE);
else
} else {
unsigned long flags;
spin_lock_irqsave(&kbdev->pm.metrics.lock, flags);
kbasep_pm_record_job_status(kbdev);
kbdev->pm.metrics.active_gl_ctx--;
spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags);
runpool_state_changed |= kbasep_js_ctx_attr_ctx_release_attr(kbdev, kctx, KBASEP_JS_CTX_ATTR_NON_COMPUTE);
}
if ((core_req & (BASE_JD_REQ_CS | BASE_JD_REQ_ONLY_COMPUTE | BASE_JD_REQ_T)) != 0 && (core_req & (BASE_JD_REQ_COHERENT_GROUP | BASE_JD_REQ_SPECIFIC_COHERENT_GROUP)) == 0) {
/* Atom that can run on slot1 or slot2, and can use all cores */

2
drivers/gpu/arm/midgard/mali_kbase_js_defs.h
View File

@@ -448,6 +448,8 @@ typedef struct kbasep_js_atom_retained_state {
base_jd_core_req core_req;
/** Job Slot to retry submitting to if submission from IRQ handler failed */
int retry_submit_on_slot;
/* Core group atom was executed on */
u32 device_nr;
} kbasep_js_atom_retained_state;

2
drivers/gpu/arm/midgard/mali_kbase_mem_linux.c
View File

@@ -1404,7 +1404,7 @@ int kbase_mmap(struct file *file, struct vm_area_struct *vma)
!(reg->flags & KBASE_REG_CPU_WR))) {
/* VM flags inconsistent with region flags */
err = -EPERM;
printk(KERN_ERR "%s:%d inconsistent VM flags\n",
dev_err(dev, "%s:%d inconsistent VM flags\n",
__FILE__, __LINE__);
goto out_unlock;
}

4
drivers/gpu/arm/midgard/mali_kbase_mmu.c
View File

@@ -207,10 +207,6 @@ static void page_fault_worker(struct work_struct *data)
kbase_reg_write(kbdev, MMU_AS_REG(as_no, ASn_LOCKADDR_LO), lock_addr & 0xFFFFFFFFUL, kctx);
kbase_reg_write(kbdev, MMU_AS_REG(as_no, ASn_LOCKADDR_HI), lock_addr >> 32, kctx);
kbase_reg_write(kbdev, MMU_AS_REG(as_no, ASn_COMMAND), ASn_COMMAND_LOCK, kctx);
if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_T76X_3285)) {
kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), (1UL << as_no), NULL);
kbase_reg_write(kbdev, MMU_AS_REG(as_no, ASn_COMMAND), ASn_COMMAND_LOCK, kctx);
}
/* set up the new pages */
err = kbase_mmu_insert_pages(kctx, region->start_pfn + kbase_reg_current_backed_size(region) - new_pages, &kbase_get_phy_pages(region)[kbase_reg_current_backed_size(region) - new_pages], new_pages, region->flags);

27
drivers/gpu/arm/midgard/mali_kbase_pm.h
View File

@@ -110,10 +110,16 @@ void kbase_pm_term(struct kbase_device *kbdev);
typedef struct kbasep_pm_metrics_data {
int vsync_hit;
int utilisation;
int util_gl_share;
int util_cl_share[2]; /* 2 is a max number of core groups we can have */
ktime_t time_period_start;
u32 time_busy;
u32 time_idle;
mali_bool gpu_active;
u32 busy_cl[2];
u32 busy_gl;
u32 active_cl_ctx[2];
u32 active_gl_ctx;
spinlock_t lock;
@@ -660,6 +666,16 @@ mali_error kbasep_pm_metrics_init(struct kbase_device *kbdev);
*/
void kbasep_pm_metrics_term(struct kbase_device *kbdev);
/** Record state of jobs currently active on GPU.
*
* This function record time spent executing jobs split per GL and CL
* contexts, per core group (only CL jobs).
*
* @param kbdev The kbase device structure for the device
* (must be a valid pointer)
*/
void kbasep_pm_record_job_status(struct kbase_device *kbdev);
/** Record that the GPU is active.
*
* This records that the GPU is now active. The previous GPU state must have been idle, the function will assert if
@@ -839,11 +855,14 @@ void kbase_pm_do_poweroff(struct kbase_device *kbdev, mali_bool is_suspend);
* Function provided by platform specific code when DVFS is enabled to allow
* the power management metrics system to report utilisation.
*
* @param kbdev The kbase device structure for the device (must be a valid pointer)
* @param utilisation The current calculated utilisation by the metrics system.
* @return Returns 0 on failure and non zero on success.
* @param kbdev The kbase device structure for the device (must be a valid pointer)
* @param utilisation The current calculated utilisation by the metrics system.
* @param util_gl_share The current calculated gl share of utilisation.
* @param util_cl_share The current calculated cl share of utilisation per core group.
* @return Returns 0 on failure and non zero on success.
*/
int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation);
int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation,
u32 util_gl_share, u32 util_cl_share[2]);
#endif
#endif /* _KBASE_PM_H_ */

4
drivers/gpu/arm/midgard/mali_kbase_pm_driver.c
View File

@@ -762,10 +762,6 @@ static void kbase_pm_hw_issues(kbase_device *kbdev)
if (DEFAULT_ALTERNATIVE_HWC)
value |= SC_ALT_COUNTERS;
/* Use software control of forward pixel kill when needed. See MIDEUR-174. */
if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_T76X_2121))
value |= SC_OVERRIDE_FWD_PIXEL_KILL;
/* Needed due to MIDBASE-2795. ENABLE_TEXGRD_FLAGS. See PRLAM-10797. */
if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_10797))
value |= SC_ENABLE_TEXGRD_FLAGS;

106
drivers/gpu/arm/midgard/mali_kbase_pm_metrics.c
View File

@@ -69,12 +69,21 @@ mali_error kbasep_pm_metrics_init(kbase_device *kbdev)
kbdev->pm.metrics.kbdev = kbdev;
kbdev->pm.metrics.vsync_hit = 0;
kbdev->pm.metrics.utilisation = 0;
kbdev->pm.metrics.util_cl_share[0] = 0;
kbdev->pm.metrics.util_cl_share[1] = 0;
kbdev->pm.metrics.util_gl_share = 0;
kbdev->pm.metrics.time_period_start = ktime_get();
kbdev->pm.metrics.time_busy = 0;
kbdev->pm.metrics.time_idle = 0;
kbdev->pm.metrics.gpu_active = MALI_TRUE;
kbdev->pm.metrics.timer_active = MALI_TRUE;
kbdev->pm.metrics.active_cl_ctx[0] = 0;
kbdev->pm.metrics.active_cl_ctx[1] = 0;
kbdev->pm.metrics.active_gl_ctx = 0;
kbdev->pm.metrics.busy_cl[0] = 0;
kbdev->pm.metrics.busy_cl[1] = 0;
kbdev->pm.metrics.busy_gl = 0;
spin_lock_init(&kbdev->pm.metrics.lock);
@@ -109,11 +118,31 @@ void kbasep_pm_metrics_term(kbase_device *kbdev)
KBASE_EXPORT_TEST_API(kbasep_pm_metrics_term)
/*caller needs to hold kbdev->pm.metrics.lock before calling this function*/
void kbasep_pm_record_job_status(kbase_device *kbdev)
{
ktime_t now;
ktime_t diff;
u32 ns_time;
KBASE_DEBUG_ASSERT(kbdev != NULL);
now = ktime_get();
diff = ktime_sub(now, kbdev->pm.metrics.time_period_start);
ns_time = (u32) (ktime_to_ns(diff) >> KBASE_PM_TIME_SHIFT);
kbdev->pm.metrics.time_busy += ns_time;
kbdev->pm.metrics.busy_gl += ns_time * kbdev->pm.metrics.active_gl_ctx;
kbdev->pm.metrics.busy_cl[0] += ns_time * kbdev->pm.metrics.active_cl_ctx[0];
kbdev->pm.metrics.busy_cl[1] += ns_time * kbdev->pm.metrics.active_cl_ctx[1];
kbdev->pm.metrics.time_period_start = now;
}
KBASE_EXPORT_TEST_API(kbasep_pm_record_job_status)
void kbasep_pm_record_gpu_idle(kbase_device *kbdev)
{
unsigned long flags;
ktime_t now;
ktime_t diff;
KBASE_DEBUG_ASSERT(kbdev != NULL);
@@ -123,11 +152,7 @@ void kbasep_pm_record_gpu_idle(kbase_device *kbdev)
kbdev->pm.metrics.gpu_active = MALI_FALSE;
now = ktime_get();
diff = ktime_sub(now, kbdev->pm.metrics.time_period_start);
kbdev->pm.metrics.time_busy += (u32) (ktime_to_ns(diff) >> KBASE_PM_TIME_SHIFT);
kbdev->pm.metrics.time_period_start = now;
kbasep_pm_record_job_status(kbdev);
spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags);
}
@@ -172,9 +197,10 @@ void kbase_pm_report_vsync(kbase_device *kbdev, int buffer_updated)
KBASE_EXPORT_TEST_API(kbase_pm_report_vsync)
/*caller needs to hold kbdev->pm.metrics.lock before calling this function*/
int kbase_pm_get_dvfs_utilisation(kbase_device *kbdev)
int kbase_pm_get_dvfs_utilisation(kbase_device *kbdev, int *util_gl_share, int util_cl_share[2])
{
int utilisation = 0;
int busy;
ktime_t now = ktime_get();
ktime_t diff;
@@ -183,7 +209,11 @@ int kbase_pm_get_dvfs_utilisation(kbase_device *kbdev)
diff = ktime_sub(now, kbdev->pm.metrics.time_period_start);
if (kbdev->pm.metrics.gpu_active) {
kbdev->pm.metrics.time_busy += (u32) (ktime_to_ns(diff) >> KBASE_PM_TIME_SHIFT);
u32 ns_time = (u32) (ktime_to_ns(diff) >> KBASE_PM_TIME_SHIFT);
kbdev->pm.metrics.time_busy += ns_time;
kbdev->pm.metrics.busy_cl[0] += ns_time * kbdev->pm.metrics.active_cl_ctx[0];
kbdev->pm.metrics.busy_cl[1] += ns_time * kbdev->pm.metrics.active_cl_ctx[1];
kbdev->pm.metrics.busy_gl += ns_time * kbdev->pm.metrics.active_gl_ctx;
kbdev->pm.metrics.time_period_start = now;
} else {
kbdev->pm.metrics.time_idle += (u32) (ktime_to_ns(diff) >> KBASE_PM_TIME_SHIFT);
@@ -193,15 +223,49 @@ int kbase_pm_get_dvfs_utilisation(kbase_device *kbdev)
if (kbdev->pm.metrics.time_idle + kbdev->pm.metrics.time_busy == 0) {
/* No data - so we return NOP */
utilisation = -1;
if (util_gl_share)
*util_gl_share = -1;
if (util_cl_share) {
util_cl_share[0] = -1;
util_cl_share[1] = -1;
}
goto out;
}
utilisation = (100 * kbdev->pm.metrics.time_busy) / (kbdev->pm.metrics.time_idle + kbdev->pm.metrics.time_busy);
utilisation = (100 * kbdev->pm.metrics.time_busy) /
(kbdev->pm.metrics.time_idle +
kbdev->pm.metrics.time_busy);
out:
busy = kbdev->pm.metrics.busy_gl +
kbdev->pm.metrics.busy_cl[0] +
kbdev->pm.metrics.busy_cl[1];
if (busy != 0) {
if (util_gl_share)
*util_gl_share =
(100 * kbdev->pm.metrics.busy_gl) / busy;
if (util_cl_share) {
util_cl_share[0] =
(100 * kbdev->pm.metrics.busy_cl[0]) / busy;
util_cl_share[1] =
(100 * kbdev->pm.metrics.busy_cl[1]) / busy;
}
} else {
if (util_gl_share)
*util_gl_share = -1;
if (util_cl_share) {
util_cl_share[0] = -1;
util_cl_share[1] = -1;
}
}
out:
kbdev->pm.metrics.time_idle = 0;
kbdev->pm.metrics.time_busy = 0;
kbdev->pm.metrics.busy_cl[0] = 0;
kbdev->pm.metrics.busy_cl[1] = 0;
kbdev->pm.metrics.busy_gl = 0;
return utilisation;
}
@@ -209,18 +273,22 @@ int kbase_pm_get_dvfs_utilisation(kbase_device *kbdev)
kbase_pm_dvfs_action kbase_pm_get_dvfs_action(kbase_device *kbdev)
{
unsigned long flags;
int utilisation;
int utilisation, util_gl_share;
int util_cl_share[2];
kbase_pm_dvfs_action action;
KBASE_DEBUG_ASSERT(kbdev != NULL);
spin_lock_irqsave(&kbdev->pm.metrics.lock, flags);
utilisation = kbase_pm_get_dvfs_utilisation(kbdev);
utilisation = kbase_pm_get_dvfs_utilisation(kbdev, &util_gl_share, util_cl_share);
if (utilisation < 0) {
if (utilisation < 0 || util_gl_share < 0 || util_cl_share < 0) {
action = KBASE_PM_DVFS_NOP;
utilisation = 0;
util_gl_share = 0;
util_cl_share[0] = 0;
util_cl_share[1] = 0;
goto out;
}
@@ -243,12 +311,18 @@ kbase_pm_dvfs_action kbase_pm_get_dvfs_action(kbase_device *kbdev)
}
kbdev->pm.metrics.utilisation = utilisation;
out:
kbdev->pm.metrics.util_cl_share[0] = util_cl_share[0];
kbdev->pm.metrics.util_cl_share[1] = util_cl_share[1];
kbdev->pm.metrics.util_gl_share = util_gl_share;
out:
#ifdef CONFIG_MALI_MIDGARD_DVFS
kbase_platform_dvfs_event(kbdev, utilisation);
kbase_platform_dvfs_event(kbdev, utilisation, util_gl_share, util_cl_share);
#endif /*CONFIG_MALI_MIDGARD_DVFS */
kbdev->pm.metrics.time_idle = 0;
kbdev->pm.metrics.time_busy = 0;
kbdev->pm.metrics.busy_cl[0] = 0;
kbdev->pm.metrics.busy_cl[1] = 0;
kbdev->pm.metrics.busy_gl = 0;
spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags);
return action;

1
drivers/gpu/arm/midgard/mali_kbase_softjobs.c
View File

@@ -20,7 +20,6 @@
#include <mali_kbase.h>
#ifdef CONFIG_SYNC
//#include <linux/sync.h>
#include "sync.h"
#include <linux/syscalls.h>
#include "mali_kbase_sync.h"

1
drivers/gpu/arm/midgard/mali_kbase_sync.c
View File

@@ -24,7 +24,6 @@
#ifdef CONFIG_SYNC
//#include <linux/sync.h>
#include "sync.h"
#include <mali_kbase.h>

1
drivers/gpu/arm/midgard/mali_midg_regmap.h
View File

@@ -438,7 +438,6 @@
/* Values for GPU_ID_VERSION_PRODUCT_ID bitfield */
#define GPU_ID_PI_T60X 0x6956
#define GPU_ID_PI_T62X 0x0620
#define GPU_ID_PI_T67X 0x0670
#define GPU_ID_PI_T76X 0x0750
#define GPU_ID_PI_T72X 0x0720

2
drivers/gpu/arm/midgard/platform/rk/mali_kbase_config_rk.c
View File

@@ -312,6 +312,7 @@ static kbase_attribute config_attributes[] = {
#ifdef CONFIG_MALI_DEBUG
/* Use more aggressive scheduling timeouts in debug builds for testing purposes */
#if 0
{
KBASE_CONFIG_ATTR_JS_SCHEDULING_TICK_NS,
KBASE_VE_JS_SCHEDULING_TICK_NS_DEBUG},
@@ -335,6 +336,7 @@ static kbase_attribute config_attributes[] = {
{
KBASE_CONFIG_ATTR_JS_RESET_TICKS_NSS,
KBASE_VE_JS_RESET_TICKS_NSS_DEBUG},
#endif
#else /* CONFIG_MALI_DEBUG */
/* In release builds same as the defaults but scaled for 5MHz FPGA */
#if 0

2
drivers/gpu/arm/midgard/platform/rk/mali_kbase_dvfs.c
View File

@@ -222,7 +222,7 @@ static void mali_dvfs_event_proc(struct work_struct *w)
static DECLARE_WORK(mali_dvfs_work, mali_dvfs_event_proc);
int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation)
int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation,u32 util_gl_share_no_use,u32 util_cl_share_no_use[2])
{
unsigned long flags;
struct rk_context *platform;

3
drivers/gpu/arm/midgard/platform/rk/mali_kbase_dvfs.h
View File

@@ -48,7 +48,8 @@ int kbase_platform_dvfs_get_level(int freq);
#ifdef CONFIG_MALI_MIDGARD_DVFS
int kbase_platform_dvfs_init(struct kbase_device *dev);
void kbase_platform_dvfs_term(void);
int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation);
/*int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation);*/
/*int kbase_platform_dvfs_event(struct kbase_device *kbdev, u32 utilisation,u32 util_gl_share, u32 util_cl_share[2]);*/
int kbase_platform_dvfs_get_enable_status(void);
int kbase_platform_dvfs_enable(bool enable, int freq);
int kbase_platform_dvfs_get_utilisation(void);

2
drivers/gpu/arm/midgard/sconscript
View File

@@ -1,5 +1,5 @@
#
# (C) COPYRIGHT 2010-2013 ARM Limited. All rights reserved.
# (C) COPYRIGHT 2010-2014 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software

2
drivers/gpu/arm/midgard/tests/customer/sconscript
View File

@@ -1,6 +1,6 @@
# This confidential and proprietary software may be used only as
# authorised by a licensing agreement from ARM Limited
# (C) COPYRIGHT 2010-2011 ARM Limited
# (C) COPYRIGHT 2010-2011, 2013 ARM Limited
# ALL RIGHTS RESERVED
# The entire notice above must be reproduced on all authorised
# copies and copies may only be made to the extent permitted

2
drivers/gpu/arm/midgard/tests/sconscript
View File

@@ -1,6 +1,6 @@
# This confidential and proprietary software may be used only as
# authorised by a licensing agreement from ARM Limited
# (C) COPYRIGHT 2010-2011 ARM Limited
# (C) COPYRIGHT 2010-2011, 2013 ARM Limited
# ALL RIGHTS RESERVED
# The entire notice above must be reproduced on all authorised
# copies and copies may only be made to the extent permitted