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drm/bridge: analogix_dp: Add HBR2 support for RK3399

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Change-Id: I3999e4fa0b83ede5719f341d1e9a9a8797c7576b
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2017-08-28 09:33:59 +08:00
committed by Tao Huang
parent ae45df9576
commit 515b6b6055
4 changed files with 33 additions and 8 deletions
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29
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
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@@ -465,11 +465,25 @@ static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
}
}
static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp)
{
bool source_tps3_supported, sink_tps3_supported;
u8 dpcd = 0;
source_tps3_supported =
dp->video_info.max_link_rate == DP_LINK_BW_5_4;
drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd);
sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED;
return source_tps3_supported && sink_tps3_supported;
}
static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
{
int lane, lane_count, retval;
u8 voltage_swing, pre_emphasis, training_lane;
u8 link_status[2], adjust_request[2];
u8 training_pattern = TRAINING_PTN2;
usleep_range(100, 101);
@@ -485,12 +499,16 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
return retval;
if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
/* set training pattern 2 for EQ */
analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
if (analogix_dp_tps3_supported(dp))
training_pattern = TRAINING_PTN3;
/* set training pattern for EQ */
analogix_dp_set_training_pattern(dp, training_pattern);
retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
DP_LINK_SCRAMBLING_DISABLE |
DP_TRAINING_PATTERN_2);
(training_pattern == TRAINING_PTN3 ?
DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2));
if (retval < 0)
return retval;
@@ -1583,7 +1601,6 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
switch (dp->plat_data->dev_type) {
case RK3288_DP:
case RK3399_EDP:
case RK3568_EDP:
/*
* Like Rk3288 DisplayPort TRM indicate that "Main link
@@ -1592,6 +1609,10 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
video_info->max_link_rate = 0x0A;
video_info->max_lane_count = 0x04;
break;
case RK3399_EDP:
video_info->max_link_rate = 0x14;
video_info->max_lane_count = 0x04;
break;
case EXYNOS_DP:
/*
* NOTE: those property parseing code is used for

1
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
View File

@@ -69,6 +69,7 @@ enum pattern_set {
D10_2,
TRAINING_PTN1,
TRAINING_PTN2,
TRAINING_PTN3,
DP_NONE
};

10
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
View File

@@ -559,12 +559,10 @@ bool analogix_dp_ssc_supported(struct analogix_dp_device *dp)
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
{
u32 reg, status;
u32 status;
int ret;
reg = bwtype;
if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg);
analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, bwtype);
if (dp->phy) {
union phy_configure_opts phy_cfg = {0};
@@ -720,6 +718,10 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
break;
case TRAINING_PTN3:
reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN3;
analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
break;
case DP_NONE:
reg = SCRAMBLING_ENABLE |
LINK_QUAL_PATTERN_SET_DISABLE |

1
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
View File

@@ -402,6 +402,7 @@
#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
#define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0)
#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)