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mt76: unify sta_rate_tbl_update and related helpers
Use common sta_rate_tbl_update on mt76x0 and mt76x2. mt76x0 do not have support TPC (transmision power control) implmented, msta->wcid.max_txpwr_adj is only set for mt76x2. Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
committed by
Felix Fietkau
parent
212926eb44
commit
5327b5ea13
@@ -247,6 +247,8 @@ struct mt76_driver_ops {
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void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
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bool ps);
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s8 (*get_max_txpwr_adj)(struct mt76_dev *dev,
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const struct ieee80211_tx_rate *rate);
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};
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struct mt76_channel_state {
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@@ -493,6 +493,7 @@ struct mt76x0_dev *mt76x0_alloc_device(struct device *pdev)
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dev = hw->priv;
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dev->mt76.dev = pdev;
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dev->mt76.hw = hw;
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dev->mt76.drv = NULL;
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mutex_init(&dev->usb_ctrl_mtx);
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mutex_init(&dev->reg_atomic_mutex);
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mutex_init(&dev->hw_atomic_mutex);
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@@ -116,67 +116,6 @@ mt76_mac_fill_tx_status(struct mt76x0_dev *dev, struct ieee80211_tx_info *info,
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info->flags |= IEEE80211_TX_STAT_ACK;
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}
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u16 mt76x0_mac_tx_rate_val(struct mt76x0_dev *dev,
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const struct ieee80211_tx_rate *rate, u8 *nss_val)
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{
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u16 rateval;
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u8 phy, rate_idx;
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u8 nss = 1;
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u8 bw = 0;
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if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
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rate_idx = rate->idx;
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nss = 1 + (rate->idx >> 4);
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phy = MT_PHY_TYPE_VHT;
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if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
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bw = 2;
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else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
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bw = 1;
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} else if (rate->flags & IEEE80211_TX_RC_MCS) {
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rate_idx = rate->idx;
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nss = 1 + (rate->idx >> 3);
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phy = MT_PHY_TYPE_HT;
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if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
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phy = MT_PHY_TYPE_HT_GF;
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if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
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bw = 1;
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} else {
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const struct ieee80211_rate *r;
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int band = dev->mt76.chandef.chan->band;
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u16 val;
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r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx];
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if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
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val = r->hw_value_short;
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else
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val = r->hw_value;
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phy = val >> 8;
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rate_idx = val & 0xff;
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bw = 0;
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}
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rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx);
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rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy);
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rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);
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if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
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rateval |= MT_RXWI_RATE_SGI;
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*nss_val = nss;
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return cpu_to_le16(rateval);
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}
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void mt76x0_mac_wcid_set_rate(struct mt76x0_dev *dev, struct mt76_wcid *wcid,
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const struct ieee80211_tx_rate *rate)
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{
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unsigned long flags;
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spin_lock_irqsave(&dev->mt76.lock, flags);
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wcid->tx_rate = mt76x0_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss);
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wcid->tx_rate_set = true;
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spin_unlock_irqrestore(&dev->mt76.lock, flags);
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}
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struct mt76x02_tx_status mt76x0_mac_fetch_tx_status(struct mt76x0_dev *dev)
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{
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struct mt76x02_tx_status stat = {};
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@@ -537,7 +476,7 @@ u32 mt76x0_mac_process_rx(struct mt76x0_dev *dev, struct sk_buff *skb,
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spin_lock_bh(&dev->con_mon_lock);
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if (mt76x0_rx_is_our_beacon(dev, data)) {
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mt76x0_rx_monitor_beacon(dev, rxwi, rate, rssi);
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} else if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_U2M)) {
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} else if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST)) {
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if (dev->avg_rssi == 0)
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dev->avg_rssi = rssi;
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else
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@@ -32,60 +32,6 @@ struct mt76x0_rxwi {
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__le32 bbp_rxinfo[4];
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} __packed __aligned(4);
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#define MT_RXINFO_BA BIT(0)
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#define MT_RXINFO_DATA BIT(1)
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#define MT_RXINFO_NULL BIT(2)
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#define MT_RXINFO_FRAG BIT(3)
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#define MT_RXINFO_U2M BIT(4)
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#define MT_RXINFO_MULTICAST BIT(5)
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#define MT_RXINFO_BROADCAST BIT(6)
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#define MT_RXINFO_MYBSS BIT(7)
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#define MT_RXINFO_CRCERR BIT(8)
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#define MT_RXINFO_ICVERR BIT(9)
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#define MT_RXINFO_MICERR BIT(10)
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#define MT_RXINFO_AMSDU BIT(11)
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#define MT_RXINFO_HTC BIT(12)
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#define MT_RXINFO_RSSI BIT(13)
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#define MT_RXINFO_L2PAD BIT(14)
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#define MT_RXINFO_AMPDU BIT(15)
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#define MT_RXINFO_DECRYPT BIT(16)
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#define MT_RXINFO_BSSIDX3 BIT(17)
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#define MT_RXINFO_WAPI_KEY BIT(18)
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#define MT_RXINFO_PN_LEN GENMASK(21, 19)
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#define MT_RXINFO_SW_PKT_80211 BIT(22)
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#define MT_RXINFO_TCP_SUM_BYPASS BIT(28)
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#define MT_RXINFO_IP_SUM_BYPASS BIT(29)
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#define MT_RXINFO_TCP_SUM_ERR BIT(30)
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#define MT_RXINFO_IP_SUM_ERR BIT(31)
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#define MT_RXWI_CTL_WCID GENMASK(7, 0)
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#define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
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#define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
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#define MT_RXWI_CTL_UDF GENMASK(15, 13)
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#define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16)
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#define MT_RXWI_CTL_TID GENMASK(31, 28)
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#define MT_RXWI_FRAG GENMASK(3, 0)
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#define MT_RXWI_SN GENMASK(15, 4)
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#define MT_RXWI_RATE_INDEX GENMASK(5, 0)
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#define MT_RXWI_RATE_LDPC BIT(6)
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#define MT_RXWI_RATE_BW GENMASK(8, 7)
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#define MT_RXWI_RATE_SGI BIT(9)
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#define MT_RXWI_RATE_STBC BIT(10)
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#define MT_RXWI_RATE_LDPC_ETXBF BIT(11)
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#define MT_RXWI_RATE_SND BIT(12)
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#define MT_RXWI_RATE_PHY GENMASK(15, 13)
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#define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0)
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#define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4)
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#define MT_RXWI_GAIN_RSSI_VAL GENMASK(5, 0)
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#define MT_RXWI_GAIN_RSSI_LNA_ID GENMASK(7, 6)
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#define MT_RXWI_ANT_AUX_LNA BIT(7)
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#define MT_RXWI_EANT_ENC_ANT_ID GENMASK(7, 0)
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enum mt76_phy_bandwidth {
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MT_PHY_BW_20,
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MT_PHY_BW_40,
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@@ -138,11 +84,6 @@ struct mt76_txwi {
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u32 mt76x0_mac_process_rx(struct mt76x0_dev *dev, struct sk_buff *skb,
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u8 *data, void *rxi);
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void mt76x0_mac_wcid_set_rate(struct mt76x0_dev *dev, struct mt76_wcid *wcid,
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const struct ieee80211_tx_rate *rate);
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u16 mt76x0_mac_tx_rate_val(struct mt76x0_dev *dev,
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const struct ieee80211_tx_rate *rate, u8 *nss_val);
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struct mt76x02_tx_status
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mt76x0_mac_fetch_tx_status(struct mt76x0_dev *dev);
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void mt76x0_send_tx_status(struct mt76x0_dev *dev, struct mt76x02_tx_status *stat, u8 *update);
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@@ -156,29 +156,6 @@ static int mt76x0_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
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return 0;
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}
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static void
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mt76_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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struct ieee80211_sta *sta)
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{
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struct mt76x0_dev *dev = hw->priv;
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struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv;
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struct ieee80211_sta_rates *rates;
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struct ieee80211_tx_rate rate = {};
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rcu_read_lock();
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rates = rcu_dereference(sta->rates);
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if (!rates)
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goto out;
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rate.idx = rates->rate[0].idx;
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rate.flags = rates->rate[0].flags;
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mt76x0_mac_wcid_set_rate(dev, &msta->wcid, &rate);
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out:
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rcu_read_unlock();
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}
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const struct ieee80211_ops mt76x0_ops = {
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.tx = mt76x0_tx,
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.start = mt76x0_start,
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@@ -195,6 +172,6 @@ const struct ieee80211_ops mt76x0_ops = {
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.sw_scan_start = mt76x0_sw_scan,
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.sw_scan_complete = mt76x0_sw_scan_complete,
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.ampdu_action = mt76x02_ampdu_action,
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.sta_rate_tbl_update = mt76_sta_rate_tbl_update,
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.sta_rate_tbl_update = mt76x02_sta_rate_tbl_update,
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.set_rts_threshold = mt76x0_set_rts_threshold,
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};
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@@ -93,7 +93,7 @@ mt76x0_push_txwi(struct mt76x0_dev *dev, struct sk_buff *skb,
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rate_ctl = wcid->tx_rate;
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nss = wcid->tx_rate_nss;
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} else {
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rate_ctl = mt76x0_mac_tx_rate_val(dev, rate, &nss);
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rate_ctl = mt76x02_mac_tx_rate_val(&dev->mt76, rate, &nss);
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}
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spin_unlock_irqrestore(&dev->mt76.lock, flags);
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@@ -155,3 +155,64 @@ void mt76x02_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq)
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mt76_txq_init(dev, txq);
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}
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EXPORT_SYMBOL_GPL(mt76x02_txq_init);
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__le16
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mt76x02_mac_tx_rate_val(struct mt76_dev *dev,
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const struct ieee80211_tx_rate *rate, u8 *nss_val)
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{
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u16 rateval;
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u8 phy, rate_idx;
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u8 nss = 1;
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u8 bw = 0;
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if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
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rate_idx = rate->idx;
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nss = 1 + (rate->idx >> 4);
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phy = MT_PHY_TYPE_VHT;
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if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
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bw = 2;
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else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
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bw = 1;
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} else if (rate->flags & IEEE80211_TX_RC_MCS) {
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rate_idx = rate->idx;
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nss = 1 + (rate->idx >> 3);
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phy = MT_PHY_TYPE_HT;
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if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
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phy = MT_PHY_TYPE_HT_GF;
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if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
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bw = 1;
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} else {
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const struct ieee80211_rate *r;
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int band = dev->chandef.chan->band;
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u16 val;
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r = &dev->hw->wiphy->bands[band]->bitrates[rate->idx];
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if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
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val = r->hw_value_short;
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else
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val = r->hw_value;
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phy = val >> 8;
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rate_idx = val & 0xff;
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bw = 0;
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}
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rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx);
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rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy);
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rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);
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if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
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rateval |= MT_RXWI_RATE_SGI;
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*nss_val = nss;
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return cpu_to_le16(rateval);
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}
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EXPORT_SYMBOL_GPL(mt76x02_mac_tx_rate_val);
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void mt76x02_mac_wcid_set_rate(struct mt76_dev *dev, struct mt76_wcid *wcid,
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const struct ieee80211_tx_rate *rate)
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{
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spin_lock_bh(&dev->lock);
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wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss);
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wcid->tx_rate_set = true;
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spin_unlock_bh(&dev->lock);
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}
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@@ -53,6 +53,57 @@ struct mt76x02_sta {
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int inactive_count;
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};
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#define MT_RXINFO_BA BIT(0)
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#define MT_RXINFO_DATA BIT(1)
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#define MT_RXINFO_NULL BIT(2)
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#define MT_RXINFO_FRAG BIT(3)
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#define MT_RXINFO_UNICAST BIT(4)
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#define MT_RXINFO_MULTICAST BIT(5)
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#define MT_RXINFO_BROADCAST BIT(6)
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#define MT_RXINFO_MYBSS BIT(7)
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#define MT_RXINFO_CRCERR BIT(8)
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#define MT_RXINFO_ICVERR BIT(9)
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#define MT_RXINFO_MICERR BIT(10)
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#define MT_RXINFO_AMSDU BIT(11)
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#define MT_RXINFO_HTC BIT(12)
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#define MT_RXINFO_RSSI BIT(13)
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#define MT_RXINFO_L2PAD BIT(14)
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#define MT_RXINFO_AMPDU BIT(15)
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#define MT_RXINFO_DECRYPT BIT(16)
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#define MT_RXINFO_BSSIDX3 BIT(17)
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#define MT_RXINFO_WAPI_KEY BIT(18)
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#define MT_RXINFO_PN_LEN GENMASK(21, 19)
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#define MT_RXINFO_SW_FTYPE0 BIT(22)
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#define MT_RXINFO_SW_FTYPE1 BIT(23)
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#define MT_RXINFO_PROBE_RESP BIT(24)
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#define MT_RXINFO_BEACON BIT(25)
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#define MT_RXINFO_DISASSOC BIT(26)
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#define MT_RXINFO_DEAUTH BIT(27)
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#define MT_RXINFO_ACTION BIT(28)
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#define MT_RXINFO_TCP_SUM_ERR BIT(30)
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#define MT_RXINFO_IP_SUM_ERR BIT(31)
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#define MT_RXWI_CTL_WCID GENMASK(7, 0)
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#define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
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#define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
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#define MT_RXWI_CTL_UDF GENMASK(15, 13)
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#define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16)
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#define MT_RXWI_CTL_EOF BIT(31)
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#define MT_RXWI_TID GENMASK(3, 0)
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#define MT_RXWI_SN GENMASK(15, 4)
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#define MT_RXWI_RATE_INDEX GENMASK(5, 0)
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#define MT_RXWI_RATE_LDPC BIT(6)
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#define MT_RXWI_RATE_BW GENMASK(8, 7)
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#define MT_RXWI_RATE_SGI BIT(9)
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#define MT_RXWI_RATE_STBC BIT(10)
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#define MT_RXWI_RATE_LDPC_EXSYM BIT(11)
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#define MT_RXWI_RATE_PHY GENMASK(15, 13)
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#define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0)
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#define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4)
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static inline bool mt76x02_wait_for_mac(struct mt76_dev *dev)
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{
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const u32 MAC_CSR0 = 0x1000;
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@@ -85,4 +136,9 @@ int mt76x02_mac_wcid_set_key(struct mt76_dev *dev, u8 idx,
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struct ieee80211_key_conf *key);
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void mt76x02_mac_wcid_setup(struct mt76_dev *dev, u8 idx, u8 vif_idx, u8 *mac);
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void mt76x02_mac_wcid_set_drop(struct mt76_dev *dev, u8 idx, bool drop);
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void mt76x02_mac_wcid_set_rate(struct mt76_dev *dev, struct mt76_wcid *wcid,
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const struct ieee80211_tx_rate *rate);
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__le16
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mt76x02_mac_tx_rate_val(struct mt76_dev *dev,
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const struct ieee80211_tx_rate *rate, u8 *nss_val);
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#endif
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@@ -327,4 +327,25 @@ int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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}
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EXPORT_SYMBOL_GPL(mt76x02_conf_tx);
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void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
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struct ieee80211_vif *vif,
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struct ieee80211_sta *sta)
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{
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struct mt76_dev *dev = hw->priv;
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struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv;
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struct ieee80211_sta_rates *rates = rcu_dereference(sta->rates);
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struct ieee80211_tx_rate rate = {};
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if (!rates)
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return;
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rate.idx = rates->rate[0].idx;
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rate.flags = rates->rate[0].flags;
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mt76x02_mac_wcid_set_rate(dev, &msta->wcid, &rate);
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if (dev->drv && dev->drv->get_max_txpwr_adj)
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msta->wcid.max_txpwr_adj = dev->drv->get_max_txpwr_adj(dev, &rate);
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}
|
||||
EXPORT_SYMBOL_GPL(mt76x02_sta_rate_tbl_update);
|
||||
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
||||
@@ -40,4 +40,7 @@ int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
|
||||
struct ieee80211_key_conf *key);
|
||||
int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
u16 queue, const struct ieee80211_tx_queue_params *params);
|
||||
void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta);
|
||||
#endif
|
||||
|
||||
@@ -234,7 +234,7 @@ void mt76x2_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps);
|
||||
|
||||
void mt76x2_update_channel(struct mt76_dev *mdev);
|
||||
|
||||
s8 mt76x2_tx_get_max_txpwr_adj(struct mt76x2_dev *dev,
|
||||
s8 mt76x2_tx_get_max_txpwr_adj(struct mt76_dev *dev,
|
||||
const struct ieee80211_tx_rate *rate);
|
||||
s8 mt76x2_tx_get_txpwr_adj(struct mt76x2_dev *dev, s8 txpwr, s8 max_txpwr_adj);
|
||||
void mt76x2_tx_set_txpwr_auto(struct mt76x2_dev *dev, s8 txpwr);
|
||||
@@ -259,9 +259,6 @@ void mt76x2_remove_interface(struct ieee80211_hw *hw,
|
||||
int mt76x2_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
u16 queue, const struct ieee80211_tx_queue_params *params);
|
||||
void mt76x2_txq_init(struct mt76x2_dev *dev, struct ieee80211_txq *txq);
|
||||
void mt76x2_sta_rate_tbl_update(struct ieee80211_hw *hw,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta);
|
||||
|
||||
void mt76x2_phy_set_txpower_regs(struct mt76x2_dev *dev,
|
||||
enum nl80211_band band);
|
||||
|
||||
@@ -18,25 +18,6 @@
|
||||
#include "mt76x2.h"
|
||||
#include "mt76x02_mac.h"
|
||||
|
||||
void mt76x2_sta_rate_tbl_update(struct ieee80211_hw *hw,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct mt76x2_dev *dev = hw->priv;
|
||||
struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv;
|
||||
struct ieee80211_sta_rates *rates = rcu_dereference(sta->rates);
|
||||
struct ieee80211_tx_rate rate = {};
|
||||
|
||||
if (!rates)
|
||||
return;
|
||||
|
||||
rate.idx = rates->rate[0].idx;
|
||||
rate.flags = rates->rate[0].flags;
|
||||
mt76x2_mac_wcid_set_rate(dev, &msta->wcid, &rate);
|
||||
msta->wcid.max_txpwr_adj = mt76x2_tx_get_max_txpwr_adj(dev, &rate);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mt76x2_sta_rate_tbl_update);
|
||||
|
||||
void mt76x2_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
|
||||
@@ -424,6 +424,7 @@ struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev)
|
||||
.rx_skb = mt76x2_queue_rx_skb,
|
||||
.rx_poll_complete = mt76x2_rx_poll_complete,
|
||||
.sta_ps = mt76x2_sta_ps,
|
||||
.get_max_txpwr_adj = mt76x2_tx_get_max_txpwr_adj,
|
||||
};
|
||||
struct mt76x2_dev *dev;
|
||||
struct mt76_dev *mdev;
|
||||
|
||||
@@ -47,57 +47,6 @@ struct mt76x2_rxwi {
|
||||
__le32 bbp_rxinfo[4];
|
||||
};
|
||||
|
||||
#define MT_RXINFO_BA BIT(0)
|
||||
#define MT_RXINFO_DATA BIT(1)
|
||||
#define MT_RXINFO_NULL BIT(2)
|
||||
#define MT_RXINFO_FRAG BIT(3)
|
||||
#define MT_RXINFO_UNICAST BIT(4)
|
||||
#define MT_RXINFO_MULTICAST BIT(5)
|
||||
#define MT_RXINFO_BROADCAST BIT(6)
|
||||
#define MT_RXINFO_MYBSS BIT(7)
|
||||
#define MT_RXINFO_CRCERR BIT(8)
|
||||
#define MT_RXINFO_ICVERR BIT(9)
|
||||
#define MT_RXINFO_MICERR BIT(10)
|
||||
#define MT_RXINFO_AMSDU BIT(11)
|
||||
#define MT_RXINFO_HTC BIT(12)
|
||||
#define MT_RXINFO_RSSI BIT(13)
|
||||
#define MT_RXINFO_L2PAD BIT(14)
|
||||
#define MT_RXINFO_AMPDU BIT(15)
|
||||
#define MT_RXINFO_DECRYPT BIT(16)
|
||||
#define MT_RXINFO_BSSIDX3 BIT(17)
|
||||
#define MT_RXINFO_WAPI_KEY BIT(18)
|
||||
#define MT_RXINFO_PN_LEN GENMASK(21, 19)
|
||||
#define MT_RXINFO_SW_FTYPE0 BIT(22)
|
||||
#define MT_RXINFO_SW_FTYPE1 BIT(23)
|
||||
#define MT_RXINFO_PROBE_RESP BIT(24)
|
||||
#define MT_RXINFO_BEACON BIT(25)
|
||||
#define MT_RXINFO_DISASSOC BIT(26)
|
||||
#define MT_RXINFO_DEAUTH BIT(27)
|
||||
#define MT_RXINFO_ACTION BIT(28)
|
||||
#define MT_RXINFO_TCP_SUM_ERR BIT(30)
|
||||
#define MT_RXINFO_IP_SUM_ERR BIT(31)
|
||||
|
||||
#define MT_RXWI_CTL_WCID GENMASK(7, 0)
|
||||
#define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
|
||||
#define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
|
||||
#define MT_RXWI_CTL_UDF GENMASK(15, 13)
|
||||
#define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16)
|
||||
#define MT_RXWI_CTL_EOF BIT(31)
|
||||
|
||||
#define MT_RXWI_TID GENMASK(3, 0)
|
||||
#define MT_RXWI_SN GENMASK(15, 4)
|
||||
|
||||
#define MT_RXWI_RATE_INDEX GENMASK(5, 0)
|
||||
#define MT_RXWI_RATE_LDPC BIT(6)
|
||||
#define MT_RXWI_RATE_BW GENMASK(8, 7)
|
||||
#define MT_RXWI_RATE_SGI BIT(9)
|
||||
#define MT_RXWI_RATE_STBC BIT(10)
|
||||
#define MT_RXWI_RATE_LDPC_EXSYM BIT(11)
|
||||
#define MT_RXWI_RATE_PHY GENMASK(15, 13)
|
||||
|
||||
#define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0)
|
||||
#define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4)
|
||||
|
||||
#define MT_TX_PWR_ADJ GENMASK(3, 0)
|
||||
|
||||
enum mt76x2_phy_bandwidth {
|
||||
@@ -157,8 +106,6 @@ int mt76x2_mac_process_rx(struct mt76x2_dev *dev, struct sk_buff *skb,
|
||||
void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
|
||||
struct sk_buff *skb, struct mt76_wcid *wcid,
|
||||
struct ieee80211_sta *sta, int len);
|
||||
void mt76x2_mac_wcid_set_rate(struct mt76x2_dev *dev, struct mt76_wcid *wcid,
|
||||
const struct ieee80211_tx_rate *rate);
|
||||
|
||||
int mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 vif_idx,
|
||||
struct sk_buff *skb);
|
||||
|
||||
@@ -229,67 +229,6 @@ out:
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mt76x2_send_tx_status);
|
||||
|
||||
static __le16
|
||||
mt76x2_mac_tx_rate_val(struct mt76x2_dev *dev,
|
||||
const struct ieee80211_tx_rate *rate, u8 *nss_val)
|
||||
{
|
||||
u16 rateval;
|
||||
u8 phy, rate_idx;
|
||||
u8 nss = 1;
|
||||
u8 bw = 0;
|
||||
|
||||
if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
|
||||
rate_idx = rate->idx;
|
||||
nss = 1 + (rate->idx >> 4);
|
||||
phy = MT_PHY_TYPE_VHT;
|
||||
if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
|
||||
bw = 2;
|
||||
else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
|
||||
bw = 1;
|
||||
} else if (rate->flags & IEEE80211_TX_RC_MCS) {
|
||||
rate_idx = rate->idx;
|
||||
nss = 1 + (rate->idx >> 3);
|
||||
phy = MT_PHY_TYPE_HT;
|
||||
if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
|
||||
phy = MT_PHY_TYPE_HT_GF;
|
||||
if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
|
||||
bw = 1;
|
||||
} else {
|
||||
const struct ieee80211_rate *r;
|
||||
int band = dev->mt76.chandef.chan->band;
|
||||
u16 val;
|
||||
|
||||
r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
|
||||
if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
|
||||
val = r->hw_value_short;
|
||||
else
|
||||
val = r->hw_value;
|
||||
|
||||
phy = val >> 8;
|
||||
rate_idx = val & 0xff;
|
||||
bw = 0;
|
||||
}
|
||||
|
||||
rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx);
|
||||
rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy);
|
||||
rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);
|
||||
if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
|
||||
rateval |= MT_RXWI_RATE_SGI;
|
||||
|
||||
*nss_val = nss;
|
||||
return cpu_to_le16(rateval);
|
||||
}
|
||||
|
||||
void mt76x2_mac_wcid_set_rate(struct mt76x2_dev *dev, struct mt76_wcid *wcid,
|
||||
const struct ieee80211_tx_rate *rate)
|
||||
{
|
||||
spin_lock_bh(&dev->mt76.lock);
|
||||
wcid->tx_rate = mt76x2_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss);
|
||||
wcid->tx_rate_set = true;
|
||||
spin_unlock_bh(&dev->mt76.lock);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mt76x2_mac_wcid_set_rate);
|
||||
|
||||
void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
|
||||
struct sk_buff *skb, struct mt76_wcid *wcid,
|
||||
struct ieee80211_sta *sta, int len)
|
||||
@@ -333,8 +272,8 @@ void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
|
||||
max_txpwr_adj = wcid->max_txpwr_adj;
|
||||
nss = wcid->tx_rate_nss;
|
||||
} else {
|
||||
txwi->rate = mt76x2_mac_tx_rate_val(dev, rate, &nss);
|
||||
max_txpwr_adj = mt76x2_tx_get_max_txpwr_adj(dev, rate);
|
||||
txwi->rate = mt76x02_mac_tx_rate_val(&dev->mt76, rate, &nss);
|
||||
max_txpwr_adj = mt76x2_tx_get_max_txpwr_adj(&dev->mt76, rate);
|
||||
}
|
||||
spin_unlock_bh(&dev->mt76.lock);
|
||||
|
||||
|
||||
@@ -299,7 +299,7 @@ const struct ieee80211_ops mt76x2_ops = {
|
||||
.ampdu_action = mt76x02_ampdu_action,
|
||||
.get_txpower = mt76x2_get_txpower,
|
||||
.wake_tx_queue = mt76_wake_tx_queue,
|
||||
.sta_rate_tbl_update = mt76x2_sta_rate_tbl_update,
|
||||
.sta_rate_tbl_update = mt76x02_sta_rate_tbl_update,
|
||||
.release_buffered_frames = mt76_release_buffered_frames,
|
||||
.set_coverage_class = mt76x2_set_coverage_class,
|
||||
.get_survey = mt76_get_survey,
|
||||
|
||||
@@ -63,9 +63,10 @@ int mt76x2_insert_hdr_pad(struct sk_buff *skb)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mt76x2_insert_hdr_pad);
|
||||
|
||||
s8 mt76x2_tx_get_max_txpwr_adj(struct mt76x2_dev *dev,
|
||||
s8 mt76x2_tx_get_max_txpwr_adj(struct mt76_dev *mdev,
|
||||
const struct ieee80211_tx_rate *rate)
|
||||
{
|
||||
struct mt76x2_dev *dev = (struct mt76x2_dev *) mdev;
|
||||
s8 max_txpwr;
|
||||
|
||||
if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
|
||||
|
||||
@@ -176,5 +176,5 @@ const struct ieee80211_ops mt76x2u_ops = {
|
||||
.conf_tx = mt76x02_conf_tx,
|
||||
.sw_scan_start = mt76x2u_sw_scan,
|
||||
.sw_scan_complete = mt76x2u_sw_scan_complete,
|
||||
.sta_rate_tbl_update = mt76x2_sta_rate_tbl_update,
|
||||
.sta_rate_tbl_update = mt76x02_sta_rate_tbl_update,
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user