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PCI: rockchip: dw: Add dbi_base2 for both RC and EP mode

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In order to use dw_pcie_writel_dbi2() and standard macro
to disable unused BARs.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ibe26abfb319f3f75899dd2f8c4f7b0a9a733bfa7
This commit is contained in:
Shawn Lin
2023-10-11 16:17:41 +08:00
committed by Tao Huang
parent e0d85e33a3
commit 5351f974aa
1 changed files with 3 additions and 3 deletions
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6
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -1111,8 +1111,8 @@ static int rk_pcie_host_init(struct pcie_port *pp)
dw_pcie_setup_rc(pp);
/* Disable BAR0 BAR1 */
dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_0 * 4, 0);
dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_1 * 4, 0);
dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);
dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0);
ret = rk_pcie_establish_link(pci);
@@ -1185,7 +1185,6 @@ static int rk_pcie_add_ep(struct rk_pcie *rk_pcie)
return ret;
}
rk_pcie->pci->dbi_base2 = rk_pcie->pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET;
rk_pcie->pci->atu_base = rk_pcie->pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
rk_pcie->pci->iatu_unroll_enabled = rk_pcie_iatu_unroll_enabled(rk_pcie->pci);
@@ -1245,6 +1244,7 @@ static int rk_pcie_resource_get(struct platform_device *pdev,
return PTR_ERR(rk_pcie->dbi_base);
rk_pcie->pci->dbi_base = rk_pcie->dbi_base;
rk_pcie->pci->dbi_base2 = rk_pcie->pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET;
apb_base = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"pcie-apb");