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[ARM] tegra: driver for spdif audio
Creates /dev/spdif_out and /dev/spdif_out_ctl for playback and control settings. Playback is working. Signed-off-by: Iliyan Malchev <malchev@google.com>
This commit is contained in:
Ravindra Lokhande
committed by
Iliyan Malchev
Iliyan Malchev
parent
624287cd63
commit
53bb435d8d
@@ -12,6 +12,7 @@ obj-y += powergate.o
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obj-y += suspend.o
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obj-y += fuse.o
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obj-y += tegra_i2s_audio.o
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obj-y += tegra_spdif_audio.o
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obj-y += mc.o
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obj-$(CONFIG_USB_SUPPORT) += usb_phy.o
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obj-$(CONFIG_FIQ) += fiq.o
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392
arch/arm/mach-tegra/include/mach/spdif.h
Normal file
392
arch/arm/mach-tegra/include/mach/spdif.h
Normal file
@@ -0,0 +1,392 @@
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/*
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* arch/arm/mach-tegra/include/mach/spdif.h
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*
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*
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* Copyright (c) 2008-2009, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ARCH_ARM_MACH_TEGRA_SPDIF_H
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#define __ARCH_ARM_MACH_TEGRA_SPDIF_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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/* Offsets from TEGRA_SPDIF_BASE */
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#define SPDIF_CTRL_0 0x0
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#define SPDIF_STATUS_0 0x4
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#define SPDIF_STROBE_CTRL_0 0x8
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#define SPDIF_DATA_FIFO_CSR_0 0x0C
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#define SPDIF_DATA_OUT_0 0x40
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#define SPDIF_DATA_IN_0 0x80
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#define SPDIF_CH_STA_RX_A_0 0x100
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#define SPDIF_CH_STA_RX_B_0 0x104
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#define SPDIF_CH_STA_RX_C_0 0x108
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#define SPDIF_CH_STA_RX_D_0 0x10C
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#define SPDIF_CH_STA_RX_E_0 0x110
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#define SPDIF_CH_STA_RX_F_0 0x114
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#define SPDIF_CH_STA_TX_A_0 0x140
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#define SPDIF_CH_STA_TX_B_0 0x144
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#define SPDIF_CH_STA_TX_C_0 0x148
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#define SPDIF_CH_STA_TX_D_0 0x14C
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#define SPDIF_CH_STA_TX_E_0 0x150
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#define SPDIF_CH_STA_TX_F_0 0x154
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#define SPDIF_USR_STA_RX_A_0 0x180
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#define SPDIF_USR_DAT_TX_A_0 0x1C0
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/*
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* Register SPDIF_CTRL_0
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*/
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/*
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* 1=start capturing from left channel,0=start
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* capturing from right channel.
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*/
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#define SPDIF_CTRL_0_CAP_LC (1<<30)
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/* SPDIF receiver(RX): 1=enable, 0=disable. */
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#define SPDIF_CTRL_0_RX_EN (1<<29)
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/* SPDIF Transmitter(TX): 1=enable, 0=disable. */
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#define SPDIF_CTRL_0_TX_EN (1<<28)
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/* Transmit Channel status: 1=enable, 0=disable. */
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#define SPDIF_CTRL_0_TC_EN (1<<27)
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/* Transmit user Data: 1=enable, 0=disable. */
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#define SPDIF_CTRL_0_TU_EN (1<<26)
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/* Interrupt on transmit error: 1=enable, 0=disable. */
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#define SPDIF_CTRL_0_IE_TXE (1<<25)
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/* Interrupt on receive error: 1=enable, 0=disable. */
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#define SPDIF_CTRL_0_IE_RXE (1<<24)
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/* Interrupt on invalid preamble: 1=enable, 0=disable. */
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#define SPDIF_CTRL_0_IE_P (1<<23)
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/* Interrupt on "B" preamble: 1=enable, 0=disable. */
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#define SPDIF_CTRL_0_IE_B (1<<22)
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/*
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* Interrupt when block of channel status received:
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* 1=enable, 0=disable.
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*/
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#define SPDIF_CTRL_0_IE_C (1<<21)
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/*
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* Interrupt when a valid information unit (IU) recieve:
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* 1=enable, 0=disable.
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*/
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#define SPDIF_CTRL_0_IE_U (1<<20)
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/*
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* Interrupt when RX user FIFO attn. level is reached:
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* 1=enable, 0=disable.
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*/
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#define SPDIF_CTRL_0_QE_RU (1<<19)
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/*
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* Interrupt when TX user FIFO attn. level is reached:
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* 1=enable, 0=disable.
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*/
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#define SPDIF_CTRL_0_QE_TU (1<<18)
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/*
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* Interrupt when RX data FIFO attn. level is reached:
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* 1=enable, 0=disable.
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*/
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#define SPDIF_CTRL_0_QE_RX (1<<17)
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/*
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* Interrupt when TX data FIFO attn. level is reached:
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* 1=enable, 0=disable.
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*/
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#define SPDIF_CTRL_0_QE_TX (1<<16)
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/* Loopback test mode: 1=enable internal loopback, 0=Normal mode. */
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#define SPDIF_CTRL_0_LBK_EN (1<<15)
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/*
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* Pack data mode:
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* 1=Packeted left/right channel data into a single word,
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* 0=Single data (16 bit needs to be padded to match the
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* interface data bit size)
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*/
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#define SPDIF_CTRL_0_PACK (1<<14)
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/*
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* 00=16bit data
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* 01=20bit data
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* 10=24bit data
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* 11=raw data
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*/
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#define SPDIF_BIT_MODE_MODE16BIT (0)
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#define SPDIF_BIT_MODE_MODE20BIT (1)
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#define SPDIF_BIT_MODE_MODE24BIT (2)
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#define SPDIF_BIT_MODE_MODERAW (3)
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#define SPDIF_CTRL_0_BIT_MODE_SHIFT (12)
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#define SPDIF_CTRL_0_BIT_MODE_MASK \
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((0x3) << SPDIF_CTRL_0_BIT_MODE_SHIFT)
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#define SPDIF_CTRL_0_BIT_MODE_MODE16BIT \
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(SPDIF_BIT_MODE_MODE16BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
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#define SPDIF_CTRL_0_BIT_MODE_MODE20BIT \
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(SPDIF_BIT_MODE_MODE20BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
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#define SPDIF_CTRL_0_BIT_MODE_MODE24BIT \
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(SPDIF_BIT_MODE_MODE24BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
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#define SPDIF_CTRL_0_BIT_MODE_MODERAW \
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(SPDIF_BIT_MODE_MODERAW << SPDIF_CTRL_0_BIT_MODE_SHIFT)
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/*
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* SPDIF Status Register
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* -------------------------
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* Note: IS_P, IS_B, IS_C, and IS_U are sticky bits.
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* Software must write a 1 to the corresponding bit location
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* to clear the status.
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*/
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/* Register SPDIF_STATUS_0 */
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/*
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* Receiver(RX) shifter is busy receiving data. 1=busy, 0=not busy.
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* This bit is asserted when the receiver first locked onto the
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* preamble of the data stream after RX_EN is asserted. This bit is
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* deasserted when either,
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* (a) the end of a frame is reached after RX_EN is deeasserted, or
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* (b) the SPDIF data stream becomes inactive.
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*/
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#define SPDIF_STATUS_0_RX_BSY (1<<29)
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/*
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* Transmitter(TX) shifter is busy transmitting data.
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* 1=busy, 0=not busy.
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* This bit is asserted when TX_EN is asserted.
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* This bit is deasserted when the end of a frame is reached after
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* TX_EN is deasserted.
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*/
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#define SPDIF_STATUS_0_TX_BSY (1<<28)
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/*
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* TX is busy shifting out channel status. 1=busy, 0=not busy.
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* This bit is asserted when both TX_EN and TC_EN are asserted and
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* data from CH_STA_TX_A register is loaded into the internal shifter.
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* This bit is deasserted when either,
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* (a) the end of a frame is reached after TX_EN is deasserted, or
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* (b) CH_STA_TX_F register is loaded into the internal shifter.
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*/
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#define SPDIF_STATUS_0_TC_BSY (1<<27)
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/*
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* TX User data FIFO busy. 1=busy, 0=not busy.
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* This bit is asserted when TX_EN and TXU_EN are asserted and
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* there's data in the TX user FIFO. This bit is deassert when either,
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* (a) the end of a frame is reached after TX_EN is deasserted, or
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* (b) there's no data left in the TX user FIFO.
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*/
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#define SPDIF_STATUS_0_TU_BSY (1<<26)
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/* Tx FIFO Underrun error status: 1=error, 0=no error */
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#define SPDIF_STATUS_0_TX_ERR (1<<25)
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/* Rx FIFO Overrun error status: 1=error, 0=no error */
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#define SPDIF_STATUS_0_RX_ERR (1<<24)
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/* Preamble status: 1=bad/missing preamble, 0=Preamble ok */
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#define SPDIF_STATUS_0_IS_P (1<<23)
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/* B-preamble detection status: 0=not detected, 1=B-preamble detected */
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#define SPDIF_STATUS_0_IS_B (1<<22)
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/*
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* RX channel block data receive status:
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* 1=received entire block of channel status,
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* 0=entire block not recieved yet.
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*/
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#define SPDIF_STATUS_0_IS_C (1<<21)
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/* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
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#define SPDIF_STATUS_0_IS_U (1<<20)
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/*
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* RX User FIFO Status:
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* 1=attention level reached, 0=attention level not reached.
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*/
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#define SPDIF_STATUS_0_QS_RU (1<<19)
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/*
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* TX User FIFO Status:
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* 1=attention level reached, 0=attention level not reached.
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*/
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#define SPDIF_STATUS_0_QS_TU (1<<18)
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/*
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* RX Data FIFO Status:
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* 1=attention level reached, 0=attention level not reached.
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*/
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#define SPDIF_STATUS_0_QS_RX (1<<17)
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/*
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* TX Data FIFO Status:
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* 1=attention level reached, 0=attention level not reached.
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*/
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#define SPDIF_STATUS_0_QS_TX (1<<16)
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/* SPDIF FIFO Configuration and Status Register */
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/* Register SPDIF_DATA_FIFO_CSR_0 */
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#define SPDIF_FIFO_ATN_LVL_ONE_SLOT 0
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#define SPDIF_FIFO_ATN_LVL_FOUR_SLOTS 1
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#define SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS 2
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#define SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS 3
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/* Clear Receiver User FIFO (RX USR.FIFO) */
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#define SPDIF_DATA_FIFO_CSR_0_RU_CLR (1<<31)
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/*
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* RX USR.FIFO Attention Level:
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* 00=1-slot-full, 01=2-slots-full, 10=3-slots-full, 11=4-slots-full.
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*/
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1 (0)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2 (1)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3 (2)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4 (3)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIFT (29)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_MASK \
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(0x3 << SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1_WORD_FULL \
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(SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1 << \
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SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2_WORD_FULL \
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(SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2 << \
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SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3_WORD_FULL \
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(SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3 << \
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SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
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#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4_WORD_FULL \
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(SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4 << \
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SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
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/* Number of RX USR.FIFO levels with valid data. */
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#define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT (24)
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#define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_MASK \
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(0x1f << SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT)
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/* Clear Transmitter User FIFO (TX USR.FIFO) */
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#define SPDIF_DATA_FIFO_CSR_0_TU_CLR (1<<23)
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/*
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* TxUSR.FIFO Attention Level:
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* 11=4-slots-empty, 10=3-slots-empty, 01=2-slots-empty, 00=1-slot-empty.
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*/
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1 (0)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2 (1)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3 (2)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4 (3)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT (21)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_MASK \
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(0x3 << SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1_WORD_EMPTY \
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(SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1 << \
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SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2_WORD_EMPTY \
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(SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2 << \
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SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3_WORD_EMPTY \
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(SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3 << \
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SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4_WORD_EMPTY \
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(SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4 << \
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SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
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/* Number of Tx USR.FIFO levels that could be filled. */
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#define SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT (16)
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#define SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_FIELD \
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((0x1f) << SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT)
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/* Clear Receiver Data FIFO (RX DATA.FIFO). */
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#define SPDIF_DATA_FIFO_CSR_0_RX_CLR (1<<15)
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/*
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* Rx FIFO Attention Level:
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* 11=12-slots-full, 10=8-slots-full, 01=4-slots-full, 00=1-slot-full.
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*/
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#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT (13)
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#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_MASK \
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(0x3 << SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX1_WORD_FULL \
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(SPDIF_FIFO_ATN_LVL_ONE_SLOT << \
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SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX4_WORD_FULL \
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(SPDIF_FIFO_ATN_LVL_FOUR_SLOTS << \
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SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX8_WORD_FULL \
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(SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS << \
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SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
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#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX12_WORD_FULL \
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(SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS << \
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SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
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/* Number of RX DATA.FIFO levels with valid data */
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#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT (8)
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#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_FIELD \
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((0x1f) << SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT)
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/* Clear Transmitter Data FIFO (TX DATA.FIFO) */
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#define SPDIF_DATA_FIFO_CSR_0_TX_CLR (1<<7)
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/*
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* Tx FIFO Attention Level:
|
||||
* 11=12-slots-empty, 10=8-slots-empty, 01=4-slots-empty, 00=1-slot-empty
|
||||
*/
|
||||
#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT (5)
|
||||
#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_MASK \
|
||||
(0x3 << SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
|
||||
#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX1_WORD_FULL \
|
||||
(SPDIF_FIFO_ATN_LVL_ONE_SLOT << \
|
||||
SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
|
||||
#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX4_WORD_FULL \
|
||||
(SPDIF_FIFO_ATN_LVL_FOUR_SLOTS << \
|
||||
SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
|
||||
#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX8_WORD_FULL \
|
||||
(SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS << \
|
||||
SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
|
||||
#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX12_WORD_FULL \
|
||||
(SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS << \
|
||||
SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
|
||||
|
||||
|
||||
/* Number of Tx DATA.FIFO levels that could be filled. */
|
||||
#define SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_SHIFT (0)
|
||||
#define SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_MASK \
|
||||
((0x1f) << SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_SHIFT)
|
||||
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_TEGRA_SPDIF_H */
|
||||
1396
arch/arm/mach-tegra/tegra_spdif_audio.c
Normal file
1396
arch/arm/mach-tegra/tegra_spdif_audio.c
Normal file
File diff suppressed because it is too large
Load Diff
56
include/linux/tegra_spdif.h
Normal file
56
include/linux/tegra_spdif.h
Normal file
@@ -0,0 +1,56 @@
|
||||
/* include/linux/tegra_spdif.h
|
||||
*
|
||||
* SPDIF audio driver for NVIDIA Tegra SoCs
|
||||
*
|
||||
* Copyright (c) 2008-2009, NVIDIA Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA_SPDIF_H
|
||||
#define _TEGRA_SPDIF_H
|
||||
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
#define TEGRA_SPDIF_MAGIC 's'
|
||||
|
||||
|
||||
|
||||
struct tegra_audio_buf_config {
|
||||
unsigned size; /* order */
|
||||
unsigned threshold; /* order */
|
||||
unsigned chunk; /* order */
|
||||
};
|
||||
|
||||
|
||||
|
||||
#define TEGRA_AUDIO_OUT_SET_BUF_CONFIG _IOW(TEGRA_SPDIF_MAGIC, 0, \
|
||||
const struct tegra_audio_buf_config *)
|
||||
#define TEGRA_AUDIO_OUT_GET_BUF_CONFIG _IOR(TEGRA_SPDIF_MAGIC, 1, \
|
||||
struct tegra_audio_buf_config *)
|
||||
|
||||
#define TEGRA_AUDIO_OUT_GET_ERROR_COUNT _IOR(TEGRA_SPDIF_MAGIC, 2, \
|
||||
unsigned *)
|
||||
|
||||
struct tegra_audio_out_preload {
|
||||
void *data;
|
||||
size_t len;
|
||||
size_t len_written;
|
||||
};
|
||||
|
||||
#define TEGRA_AUDIO_OUT_PRELOAD_FIFO _IOWR(TEGRA_SPDIF_MAGIC, 3, \
|
||||
struct tegra_audio_out_preload *)
|
||||
|
||||
#endif/*_TEGRA_SPDIF_H*/
|
||||
Reference in New Issue
Block a user