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drm/rockchip: dsi2: optimize power-on sequence

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1.set dsi lane to LP11 status before powering on the sceen
2.Support for init codes can be transmitted at LP or HS mode
3.HS clk comes out when the high-speed video signal is sent

Change-Id: I192a9b9d6ac3fb0cdbb4b4d462203e97c6427028
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2024-02-19 02:41:49 +00:00
committed by Tao Huang
parent 1a3e95ad13
commit 53c35ed667
1 changed files with 29 additions and 13 deletions
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42
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
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@@ -243,6 +243,7 @@ struct dw_mipi_dsi2 {
struct clk *pclk;
struct clk *sys_clk;
bool phy_enabled;
bool phy_request_clkhs;
struct phy *dcphy;
union phy_configure_opts phy_opts;
@@ -822,14 +823,6 @@ static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2)
dw_mipi_dsi2_irq_enable(dsi2, 1);
mipi_dcphy_power_on(dsi2);
/*
* initial deskew calibration is send after phy_power_on,
* then we can configure clk_type.
*/
if (!(dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG,
CLK_TYPE_MASK, CONTIUOUS_CLK);
regmap_write(dsi2->regmap, DSI2_PWR_UP, POWER_UP);
dw_mipi_dsi2_set_cmd_mode(dsi2);
@@ -839,9 +832,21 @@ static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2)
static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2)
{
u32 mode;
u32 clk_type, mode;
int ret;
/*
* initial deskew calibration is send after phy_power_on,
* then we can configure clk_type.
*/
if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
clk_type = NON_CONTINUOUS_CLK;
else
clk_type = CONTIUOUS_CLK;
regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG,
CLK_TYPE_MASK, clk_type);
dw_mipi_dsi2_ipi_set(dsi2);
if (dsi2->auto_calc_mode) {
@@ -1601,10 +1606,18 @@ static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2,
u32 val;
u32 mode;
regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG,
LPDT_DISPLAY_CMD_EN,
msg->flags & MIPI_DSI_MSG_USE_LPM ?
LPDT_DISPLAY_CMD_EN : 0);
if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG,
CLK_TYPE_MASK, dsi2->phy_request_clkhs ?
CONTIUOUS_CLK : NON_CONTINUOUS_CLK);
regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG,
LPDT_DISPLAY_CMD_EN, LPDT_DISPLAY_CMD_EN);
} else {
regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG,
CLK_TYPE_MASK, CONTIUOUS_CLK);
regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG,
LPDT_DISPLAY_CMD_EN, 0);
}
/* create a packet to the DSI protocol */
ret = mipi_dsi_create_packet(&packet, msg);
@@ -1692,6 +1705,9 @@ static int dw_mipi_dsi2_probe(struct platform_device *pdev)
dsi2->pdata = of_device_get_match_data(dev);
platform_set_drvdata(pdev, dsi2);
if (device_property_read_bool(dev, "phy-request-clkhs"))
dsi2->phy_request_clkhs = true;
if (device_property_read_bool(dev, "auto-calculation-mode"))
dsi2->auto_calc_mode = true;