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tm2: emmc run hs200 busmode [1/1]

Browse Source 
PD#SWPL-5658

Problem:
emmc run high speed now

Solution:
modify dts

Verify:
passed on t962e2_ab319

Change-Id: Iedef30bed9547e7f57c883077462f1762c55fda3
Signed-off-by: ruixuan.li <ruixuan.li@amlogic.com>
This commit is contained in:
ruixuan.li
2019-04-02 11:11:56 +08:00
committed by Jianxiong Pan
parent b8cef5e8cb
commit 53cd8bad01
10 changed files with 27 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/amlogic/mesontm2.dtsi
View File

@@ -1172,9 +1172,8 @@
<&clkc CLKID_SD_EMMC_C_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV2P5>,
<&clkc CLKID_GP0_PLL>,
<&xtal>;
clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
clock-names = "core","clkin0","clkin1","clkin2","xtal";
bus-width = <8>;
cap-sd-highspeed;

12
arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -1220,7 +1220,7 @@
sd_emmc_b: sdio@ffe05000 {
status = "okay";
compatible = "amlogic, meson-mmc-tl1";
compatible = "amlogic, meson-mmc-tm2";
reg = <0xffe05000 0x800>;
interrupts = <0 190 4>;
@@ -1266,7 +1266,7 @@
/* sd_emmc_b: sd@ffe05000 {
* status = "okay";
* compatible = "amlogic, meson-mmc-tl1";
* compatible = "amlogic, meson-mmc-tm2";
* reg = <0xffe05000 0x800>;
* interrupts = <0 190 1>;
*
@@ -1731,11 +1731,11 @@
"MMC_CAP_1_8V_DDR",
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23",
"MMC_CAP_DRIVER_TYPE_D";
//caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
"MMC_CAP_CMD23";
caps2 = "MMC_CAP2_HS200";
/* "MMC_CAP2_HS400";*/
f_min = <400000>;
f_max = <50000000>;
f_max = <200000000>;
};
};

8
arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -1161,7 +1161,7 @@
sd_emmc_b: sd@ffe05000 {
status = "okay";
compatible = "amlogic, meson-mmc-tl1";
compatible = "amlogic, meson-mmc-tm2";
reg = <0xffe05000 0x800>;
interrupts = <0 190 1>;
@@ -1614,14 +1614,14 @@
"MMC_CAP_MMC_HIGHSPEED",
"MMC_CAP_SD_HIGHSPEED",
"MMC_CAP_NONREMOVABLE",
/*"MMC_CAP_1_8V_DDR",*/
"MMC_CAP_1_8V_DDR",
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23";
//caps2 = "MMC_CAP2_HS200";
caps2 = "MMC_CAP2_HS200";
/* "MMC_CAP2_HS400";*/
f_min = <400000>;
f_max = <50000000>;
f_max = <200000000>;
};
};

2
arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -1161,7 +1161,7 @@
sd_emmc_b: sd@ffe05000 {
status = "okay";
compatible = "amlogic, meson-mmc-tl1";
compatible = "amlogic, meson-mmc-tm2";
reg = <0xffe05000 0x800>;
interrupts = <0 190 1>;

3
arch/arm64/boot/dts/amlogic/mesontm2.dtsi
View File

@@ -1152,9 +1152,8 @@
<&clkc CLKID_SD_EMMC_C_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV2P5>,
<&clkc CLKID_GP0_PLL>,
<&xtal>;
clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
clock-names = "core","clkin0","clkin1","clkin2","xtal";
bus-width = <8>;
cap-sd-highspeed;

12
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -1215,7 +1215,7 @@
sd_emmc_b: sdio@ffe05000 {
status = "okay";
compatible = "amlogic, meson-mmc-tl1";
compatible = "amlogic, meson-mmc-tm2";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <0 190 4>;
@@ -1260,7 +1260,7 @@
};
/* sd_emmc_b: sd@ffe05000 {
* status = "okay";
* compatible = "amlogic, meson-mmc-tl1";
* compatible = "amlogic, meson-mmc-tm2";
* reg = <0xffe05000 0x800>;
* interrupts = <0 190 1>;
*
@@ -1690,11 +1690,11 @@
"MMC_CAP_1_8V_DDR",
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23",
"MMC_CAP_DRIVER_TYPE_D";
//caps2 = "MMC_CAP2_HS200"; /* "MMC_CAP2_HS400";*/
"MMC_CAP_CMD23";
caps2 = "MMC_CAP2_HS200";
/* "MMC_CAP2_HS400";*/
f_min = <400000>;
f_max = <50000000>;
f_max = <200000000>;
};
};

9
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -18,7 +18,7 @@
/dts-v1/;
#include "mesontm2.dtsi"
#include "partition_mbox_normal.dtsi"
#include "partition_mbox_normal_P_32.dtsi"
/ {
model = "Amlogic TM2 T962E2 AB319";
@@ -1613,13 +1613,14 @@
"MMC_CAP_MMC_HIGHSPEED",
"MMC_CAP_SD_HIGHSPEED",
"MMC_CAP_NONREMOVABLE",
/*"MMC_CAP_1_8V_DDR",*/
"MMC_CAP_1_8V_DDR",
"MMC_CAP_HW_RESET",
"MMC_CAP_ERASE",
"MMC_CAP_CMD23";
/*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/
caps2 = "MMC_CAP2_HS200";
/* "MMC_CAP2_HS400";*/
f_min = <400000>;
f_max = <50000000>;
f_max = <200000000>;
};
};

2
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -1160,7 +1160,7 @@
sd_emmc_b: sd@ffe05000 {
status = "okay";
compatible = "amlogic, meson-mmc-tl1";
compatible = "amlogic, meson-mmc-tm2";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <0 190 1>;

2
drivers/amlogic/clk/tl1/tl1_clk_sdemmc.c
View File

@@ -27,7 +27,7 @@
#include "tl1.h"
PNAME(sd_emmc_parent_names) = { "xtal", "fclk_div2",
"fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll3", "gp0_pll" };
"fclk_div3", "fclk_div5", "fclk_div2p5", "mpll2", "mpll3", "gp0_pll" };
/*sd_emmc B*/
static MUX(sd_emmc_p0_mux_B, HHI_SD_EMMC_CLK_CNTL, 0x7, 25,
sd_emmc_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);

2
drivers/amlogic/mmc/aml_sd_emmc_v3.c
View File

@@ -241,7 +241,7 @@ static int meson_mmc_clk_set_rate_v3(struct mmc_host *mmc,
host->mux_parent[0]);
if (ret)
pr_warn("set comp0 as mux_clk parent error\n");
} else if (((host->data->chip_type == MMC_CHIP_TL1)
} else if (((host->data->chip_type >= MMC_CHIP_TL1)
|| (host->data->chip_type == MMC_CHIP_G12B))
&& (clk_ios >= 166000000)) {
src0_clk = devm_clk_get(host->dev, "clkin2");