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arm64: dts: rockchip: add rv1126b-evb-5x-cam.dtsi

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Signed-off-by: LongChang Ma <chad.ma@rock-chips.com>
Change-Id: If04bc01d4fc20e854caaa1a9fac9ce606077d358
This commit is contained in:
LongChang Ma
2025-08-02 11:14:27 +08:00
committed by Tao Huang
parent 40669e1d8e
commit 54f981afcb
1 changed files with 618 additions and 0 deletions
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arch/arm64/boot/dts/rockchip/rv1126b-evb-5x-cam.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*
*/
/*
* csi2_dphy1 -> csi0(rx0) clk0 + 2 lane 0/1
* csi2_dphy2 -> csi0(rx0) clk1 + 2 lane 2/3
* csi2_dphy4 -> csi1(rx1) clk0 + 2 lane 0/1
* csi2_dphy5 -> csi1(rx1) clk1 + 2 lane 2/3
*/
&csi2_dphy1 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy1_input0: endpoint@1 {
reg = <1>;
remote-endpoint = <&sc200ai_2_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy1_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&csi2_dphy2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy2_input1: endpoint@1 {
reg = <1>;
remote-endpoint = <&sc200ai_1_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy2_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi1_csi2_input>;
};
};
};
};
&csi2_dphy4 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy4_input0: endpoint@1 {
reg = <1>;
remote-endpoint = <&sc200ai_4_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy4_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&csi2_dphy5 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy5_input0: endpoint@1 {
reg = <1>;
remote-endpoint = <&sc200ai_5_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy5_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_csi2_input>;
};
};
};
};
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3m1_pins>;
sc200ai_1: sc200ai-1@30 {
compatible = "smartsens,sc200ai";
status = "okay";
reg = <0x30>;
clocks = <&cru CLK_MIPI1_OUT2IO>;
clock-names = "xvclk";
reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
// pwdn-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk1_pins>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
// rockchip,camera-module-sync-mode = "internal_master";
port {
sc200ai_1_out: endpoint {
remote-endpoint = <&csi_dphy2_input1>;
data-lanes = <1 2>;
};
};
};
sc200ai_2: sc200ai-2@32 {
compatible = "smartsens,sc200ai";
status = "okay";
reg = <0x32>;
clocks = <&cru CLK_MIPI0_OUT2IO>;
clock-names = "xvclk";
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
// pwdn-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk0_pins>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
// rockchip,camera-module-sync-mode = "external_master";
port {
sc200ai_2_out: endpoint {
remote-endpoint = <&csi_dphy1_input0>;
data-lanes = <1 2>;
};
};
};
ar0230: ar0230@10 {
compatible = "aptina,ar0230";
reg = <0x10>;
clocks = <&cru CLK_CIF_OUT2IO>;
clock-names = "xvclk";
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
// pinctrl-0 = <&vi_cifm0_pins>;
rockchip,camera-module-index = <4>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
ar0230_out: endpoint {
remote-endpoint = <&cif_para_in>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-0 = <&i2c5m3_pins>;
sc200ai_3: sc200ai-3@30 {
compatible = "smartsens,sc200ai";
status = "okay";
reg = <0x30>;
clocks = <&cru CLK_MIPI3_OUT2IO>;
clock-names = "xvclk";
/* pwdn need connect to reset */
reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk3_pins>;
rockchip,camera-module-index = <3>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
// rockchip,camera-module-sync-mode = "external_master";
port {
sc200ai_5_out: endpoint {
remote-endpoint = <&csi_dphy5_input0>;
data-lanes = <1 2>;
};
};
};
sc200ai_4: sc200ai-4@32 {
compatible = "smartsens,sc200ai";
status = "okay";
reg = <0x32>;
clocks = <&cru CLK_MIPI2_OUT2IO>;
clock-names = "xvclk";
/* pwdn need connect to reset */
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk2_pins>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
// rockchip,camera-module-sync-mode = "external_master";
port {
sc200ai_4_out: endpoint {
remote-endpoint = <&csi_dphy4_input0>;
data-lanes = <1 2>;
};
};
};
};
&rkcif_dvp {
status = "okay";
/* configure according to pinctrl */
cif-pins-group = <0>;
pinctrl-names = "default";
pinctrl-0 = <&vi_cifm0_pins>;
port {
#address-cells = <1>;
#size-cells = <0>;
/* Parallel bus endpoint */
cif_para_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&ar0230_out>;
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy1_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in0>;
};
};
};
};
&mipi1_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy2_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi1_in0>;
};
};
};
};
&mipi2_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy4_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi2_in0>;
};
};
};
};
&mipi3_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy5_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi3_in0>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in0: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_vir0>;
};
};
};
&rkcif_mipi_lvds1 {
status = "okay";
port {
cif_mipi1_in0: endpoint {
remote-endpoint = <&mipi1_csi2_output>;
};
};
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
port {
mipi_lvds1_sditf: endpoint {
remote-endpoint = <&isp_vir1>;
};
};
};
&rkcif_mipi_lvds2 {
status = "okay";
port {
cif_mipi2_in0: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
port {
mipi_lvds2_sditf: endpoint {
remote-endpoint = <&isp_vir2>;
};
};
};
&rkcif_mipi_lvds3 {
status = "okay";
port {
cif_mipi3_in0: endpoint {
remote-endpoint = <&mipi3_csi2_output>;
};
};
};
&rkcif_mipi_lvds3_sditf {
status = "okay";
port {
mipi_lvds3_sditf: endpoint {
remote-endpoint = <&isp_vir3>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkcif_dvp_sditf {
status = "okay";
port {
dvp_sditf: endpoint {
remote-endpoint = <&isp_vir4>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&rkisp_vir0_sditf {
status = "okay";
};
&rkisp_vir1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds1_sditf>;
};
};
};
&rkisp_vir1_sditf {
status = "okay";
};
&rkisp_vir2 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir2: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds2_sditf>;
};
};
};
&rkisp_vir2_sditf {
status = "okay";
};
&rkisp_vir3 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir3: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds3_sditf>;
};
};
};
&rkisp_vir3_sditf {
status = "okay";
};
&rkisp_vir4 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir4: endpoint@0 {
reg = <0>;
remote-endpoint = <&dvp_sditf>;
};
};
};
&rkvpss {
status = "okay";
dvbm = <&rkdvbm>;
};
&rkvpss_mmu {
status = "okay";
};
&rkvpss_vir0 {
status = "okay";
};
&rkvpss_vir1 {
status = "okay";
};
&rkvpss_vir2 {
status = "okay";
};
&rkvpss_vir3 {
status = "okay";
};