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drm/amd/display: DMUB Outbound Interrupt Process-X86

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[Why]
dmub would notify x86 response time violation by GPINT_DATAOUT

[How]
1. Use GPINT_DATAOUT to trigger x86 interrupt
2. Register GPINT_DATAOUT interrupt handler.
3. Trigger ACR while GPINT_DATAOUT occurred.

Signed-off-by: Chun-Liang Chang <Chun-Liang.Chang@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Chun-Liang Chang
2021-06-11 11:05:20 +08:00
committed by Alex Deucher
parent 1bc6c29f58
commit 556a979d3c
8 changed files with 88 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/drm/amd/display/dc/core/dc_stat.c
View File

@@ -62,3 +62,27 @@ void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification
status = dmub_srv_stat_get_notification(dmub, notify);
ASSERT(status == DMUB_STATUS_OK);
}
/**
*****************************************************************************
* Function: dc_stat_get_dmub_dataout
*
* @brief
* Calls dmub layer to retrieve dmub gpint dataout
*
* @param
* [in] dc: dc structure
* [in] dataout: dmub gpint dataout
*
* @return
* None
*****************************************************************************
*/
void dc_stat_get_dmub_dataout(const struct dc *dc, uint32_t *dataout)
{
struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;
enum dmub_status status;
status = dmub_srv_get_gpint_dataout(dmub, dataout);
ASSERT(status == DMUB_STATUS_OK);
}

1
drivers/gpu/drm/amd/display/dc/dc_stat.h
View File

@@ -38,5 +38,6 @@
#include "dmub/dmub_srv.h"
void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification *notify);
void dc_stat_get_dmub_dataout(const struct dc *dc, uint32_t *dataout);
#endif /* _DC_STAT_H_ */

2
drivers/gpu/drm/amd/display/dc/irq_types.h
View File

@@ -152,7 +152,7 @@ enum dc_irq_source {
DC_IRQ_SOURCE_DC6_VLINE1,
DC_IRQ_SOURCE_DMCUB_OUTBOX,
DC_IRQ_SOURCE_DMCUB_OUTBOX0,
DC_IRQ_SOURCE_DMCUB_GENERAL_DATAOUT,
DAL_IRQ_SOURCES_NUMBER
};

18
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
View File

@@ -352,6 +352,8 @@ struct dmub_srv_hw_funcs {
uint32_t (*get_gpint_response)(struct dmub_srv *dmub);
uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub);
void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
uint32_t (*get_current_time)(struct dmub_srv *dmub);
@@ -676,6 +678,22 @@ dmub_srv_send_gpint_command(struct dmub_srv *dmub,
enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
uint32_t *response);
/**
* dmub_srv_get_gpint_dataout() - Queries the GPINT DATAOUT.
* @dmub: the dmub service
* @dataout: the data for the GPINT DATAOUT
*
* Returns the response code for the last GPINT DATAOUT interrupt.
*
* Can be called after software initialization.
*
* Return:
* DMUB_STATUS_OK - success
* DMUB_STATUS_INVALID - unspecified error
*/
enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
uint32_t *dataout);
/**
* dmub_flush_buffer_mem() - Read back entire frame buffer region.
* This ensures that the write from x86 has been flushed and will not

15
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
View File

@@ -305,6 +305,21 @@ uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)
return REG_READ(DMCUB_SCRATCH7);
}
uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub)
{
uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
return dataout;
}
union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)
{
union dmub_fw_boot_status status;

10
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h
View File

@@ -114,7 +114,9 @@ struct dmub_srv;
DMUB_SR(DMCUB_TIMER_CURRENT) \
DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR)
DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
DMUB_SR(DMCUB_INTERRUPT_ACK)
#define DMUB_DCN31_FIELDS() \
DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
@@ -147,7 +149,9 @@ struct dmub_srv;
DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR)
DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK)
struct dmub_srv_dcn31_reg_offset {
#define DMUB_SR(reg) uint32_t reg;
@@ -222,6 +226,8 @@ bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);
uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub);
void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

17
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@@ -224,6 +224,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->set_gpint = dmub_dcn31_set_gpint;
funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
@@ -719,6 +720,22 @@ enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
return DMUB_STATUS_OK;
}
enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
uint32_t *dataout)
{
*dataout = 0;
if (!dmub->sw_init)
return DMUB_STATUS_INVALID;
if (!dmub->hw_funcs.get_gpint_dataout)
return DMUB_STATUS_INVALID;
*dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
return DMUB_STATUS_OK;
}
enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
union dmub_fw_boot_status *status)
{

4
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
View File

@@ -5971,6 +5971,7 @@
#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb
#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc
#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0xd
#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT 0x11
#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L
#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L
#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L
@@ -5985,6 +5986,7 @@
#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L
#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L
#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00002000L
#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK 0x00020000L
//DMCUB_INTERRUPT_ACK
#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0
#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1
@@ -6000,6 +6002,7 @@
#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb
#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc
#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0xd
#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT 0x11
#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L
#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L
#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L
@@ -6014,6 +6017,7 @@
#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L
#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L
#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00002000L
#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK 0x00020000L
//DMCUB_INTERRUPT_STATUS
#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0
#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1