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nvmem: rockchip-otp: refactor rockchip_data

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Add clocks and reg_read to rockchip_data, allow support more SoCs.

Change-Id: I45271d69dae808d741c953ce61b921b9a3d21202
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang
2020-05-09 10:53:02 +08:00
parent d821f78322
commit 5572fc7fe8
1 changed files with 20 additions and 15 deletions
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35
drivers/nvmem/rockchip-otp.c
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@@ -62,13 +62,11 @@ struct rockchip_otp {
struct reset_control *rst;
};
/* list of required clocks */
static const char * const rockchip_otp_clocks[] = {
"otp", "apb_pclk", "phy",
};
struct rockchip_data {
int size;
const char * const *clocks;
int num_clks;
nvmem_reg_read_t reg_read;
int (*init)(struct rockchip_otp *otp);
};
@@ -93,7 +91,7 @@ static int rockchip_otp_reset(struct rockchip_otp *otp)
return 0;
}
static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag)
static int px30_otp_wait_status(struct rockchip_otp *otp, u32 flag)
{
u32 status = 0;
int ret;
@@ -109,7 +107,7 @@ static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag)
return 0;
}
static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
static int px30_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
{
int ret = 0;
@@ -126,15 +124,15 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE);
ret = px30_otp_wait_status(otp, OTPC_SBPI_DONE);
if (ret < 0)
dev_err(otp->dev, "timeout during ecc_enable\n");
return ret;
}
static int rockchip_otp_read(void *context, unsigned int offset,
void *val, size_t bytes)
static int px30_otp_read(void *context, unsigned int offset, void *val,
size_t bytes)
{
struct rockchip_otp *otp = context;
u8 *buf = val;
@@ -152,7 +150,7 @@ static int rockchip_otp_read(void *context, unsigned int offset,
goto disable_clks;
}
ret = rockchip_otp_ecc_enable(otp, false);
ret = px30_otp_ecc_enable(otp, false);
if (ret < 0) {
dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
goto disable_clks;
@@ -165,7 +163,7 @@ static int rockchip_otp_read(void *context, unsigned int offset,
otp->base + OTPC_USER_ADDR);
writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
otp->base + OTPC_USER_ENABLE);
ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE);
ret = px30_otp_wait_status(otp, OTPC_USER_DONE);
if (ret < 0) {
dev_err(otp->dev, "timeout during read setup\n");
goto read_end;
@@ -187,11 +185,17 @@ static struct nvmem_config otp_config = {
.read_only = true,
.stride = 1,
.word_size = 1,
.reg_read = rockchip_otp_read,
};
static const char * const px30_otp_clocks[] = {
"otp", "apb_pclk", "phy",
};
static const struct rockchip_data px30_data = {
.size = 0x40,
.clocks = px30_otp_clocks,
.num_clks = ARRAY_SIZE(px30_otp_clocks),
.reg_read = px30_otp_read,
};
static const struct of_device_id rockchip_otp_match[] = {
@@ -231,14 +235,14 @@ static int __init rockchip_otp_probe(struct platform_device *pdev)
if (IS_ERR(otp->base))
return PTR_ERR(otp->base);
otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks);
otp->num_clks = data->num_clks;
otp->clks = devm_kcalloc(dev, otp->num_clks,
sizeof(*otp->clks), GFP_KERNEL);
if (!otp->clks)
return -ENOMEM;
for (i = 0; i < otp->num_clks; ++i)
otp->clks[i].id = rockchip_otp_clocks[i];
otp->clks[i].id = data->clocks[i];
ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks);
if (ret)
@@ -255,6 +259,7 @@ static int __init rockchip_otp_probe(struct platform_device *pdev)
}
otp_config.size = data->size;
otp_config.reg_read = data->reg_read;
otp_config.priv = otp;
otp_config.dev = dev;
nvmem = devm_nvmem_register(dev, &otp_config);