shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 10:58:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

phy: rockchip-typec: set usb3 to usb2 only for dp 4 lanes

Browse Source 
If the Type-C PHY works as DP 4 lanes, the Tx/Rx lanes
of Type-C USB 3.0 PHY is used for DP lanes, so it needs
to force the USB 3.0 to USB 2.0 only, and make sure USB
3.0 xHCI controller doesn't support USB 3.0 port.

With this patch, an ASUS Type-C to HDMI dongle which
supports DP 4 lanes and USB 2.0 simultaneously can
suspend/resume successfully.

Change-Id: I77049702c768bd56d638d11c29aae07eeb608282
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This commit is contained in:
William Wu
2019-12-16 16:34:58 +08:00
committed by Frank Wang
parent 96cb061468
commit 559e760d78
1 changed files with 13 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/phy/rockchip/phy-rockchip-typec.c
View File

@@ -1235,6 +1235,18 @@ static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy)
writel(val, tcphy->base + TX_DIG_CTRL_REG_2);
}
static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_typec_phy *tcphy,
bool value)
{
const struct rockchip_usb3phy_port_cfg *cfg = tcphy->port_cfgs;
property_enable(tcphy, &cfg->usb3tousb2_en, value);
property_enable(tcphy, &cfg->usb3_host_disable, value);
property_enable(tcphy, &cfg->usb3_host_port, !value);
return 0;
}
static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
{
const struct rockchip_usb3phy_port_cfg *cfg = tcphy->port_cfgs;
@@ -1262,6 +1274,7 @@ static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
tcphy_set_lane_mapping(tcphy, mode);
if (mode == MODE_DFP_DP) {
tcphy_cfg_usb3_to_usb2_only(tcphy, true);
tcphy_cfg_dp_pll(tcphy, DP_DEFAULT_RATE);
for (i = 0; i < 4; i++)
tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, i);
@@ -1367,18 +1380,6 @@ static int tcphy_get_mode(struct rockchip_typec_phy *tcphy)
return mode;
}
static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_typec_phy *tcphy,
bool value)
{
const struct rockchip_usb3phy_port_cfg *cfg = tcphy->port_cfgs;
property_enable(tcphy, &cfg->usb3tousb2_en, value);
property_enable(tcphy, &cfg->usb3_host_disable, value);
property_enable(tcphy, &cfg->usb3_host_port, !value);
return 0;
}
static int _rockchip_usb3_phy_power_on(struct rockchip_typec_phy *tcphy)
{
const struct rockchip_usb3phy_port_cfg *cfg = tcphy->port_cfgs;