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[ARM] tegra: clock: Add host and avp clocks

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Change-Id: Icde28cb63ecb7c210a05d25fbc6be96337f96a17
Signed-off-by: Colin Cross <ccross@android.com>
This commit is contained in:
Colin Cross
2010-10-20 19:30:48 -07:00
parent 766197150f
commit 56a2d8caf7
1 changed files with 7 additions and 0 deletions
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7
arch/arm/mach-tegra/tegra2_clocks.c
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@@ -1795,6 +1795,8 @@ struct clk tegra_periph_clks[] = {
PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
PERIPH_CLK("vcp", "vcp", NULL, 29, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsea", "bsea", NULL, 62, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
/* FIXME: what is la? */
@@ -1868,6 +1870,11 @@ struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
};
#define CLK(dev, con, ck) \