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rk3288-mipi-dsi: add rk3288 mipi dsi driver.

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This commit is contained in:
libing
2014-03-30 22:57:14 +08:00
parent 519044a4b8
commit 571476228f
6 changed files with 516 additions and 556 deletions
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72
drivers/video/rockchip/screen/lcd_B080XAN02_mipi.c
View File

@@ -1,72 +0,0 @@
#ifndef __LCD_B080XAN02__
#define __LCD_B080XAN02__
#if defined(CONFIG_MIPI_DSI)
#include "../transmitter/mipi_dsi.h"
#endif
#include <linux/delay.h>
#define RK_SCREEN_INIT 1
/* about mipi */
#define MIPI_DSI_LANE 4
#define MIPI_DSI_HS_CLK 528*1000000 //1000*1000000
#if defined(RK_SCREEN_INIT)
static struct rk29lcd_info *gLcd_info = NULL;
int rk_lcd_init(void) {
u8 dcs[16] = {0};
if(dsi_is_active() != 1)
return -1;
/*below is changeable*/
dsi_enable_hs_clk(1);
dcs[0] = LPDT;
dcs[1] = dcs_exit_sleep_mode;
dsi_send_dcs_packet(dcs, 2);
msleep(1);
dcs[0] = LPDT;
dcs[1] = dcs_set_display_on;
dsi_send_dcs_packet(dcs, 2);
msleep(10);
//dsi_enable_command_mode(0);
dsi_enable_video_mode(1);
printk("++++++++++++++++%s:%d\n", __func__, __LINE__);
return 0;
}
int rk_lcd_standby(u8 enable) {
u8 dcs[16] = {0};
if(dsi_is_active() != 1)
return -1;
if(enable) {
/*below is changeable*/
dcs[0] = LPDT;
dcs[1] = dcs_set_display_off;
dsi_send_dcs_packet(dcs, 2);
msleep(1);
dcs[0] = LPDT;
dcs[1] = dcs_enter_sleep_mode;
dsi_send_dcs_packet(dcs, 2);
msleep(1);
printk("++++enable++++++++++++%s:%d\n", __func__, __LINE__);
} else {
/*below is changeable*/
rk_lcd_init();
printk("++++++++++++++++%s:%d\n", __func__, __LINE__);
}
return 0;
}
#endif
#endif

70
drivers/video/rockchip/screen/lcd_LD089WU1_mipi.c
View File

@@ -1,70 +0,0 @@
#ifndef __LCD_LD089WU1__
#define __LCD_LD089WU1__
#if defined(CONFIG_MIPI_DSI)
#include "../transmitter/mipi_dsi.h"
#endif
#define RK_SCREEN_INIT 1
/* about mipi */
#define MIPI_DSI_LANE 4
#define MIPI_DSI_HS_CLK 1000*1000000
#if defined(RK_SCREEN_INIT)
static struct rk29lcd_info *gLcd_info = NULL;
int rk_lcd_init(void) {
u8 dcs[16] = {0};
if(dsi_is_active() != 1)
return -1;
/*below is changeable*/
dsi_enable_hs_clk(1);
dsi_enable_video_mode(0);
dsi_enable_command_mode(1);
dcs[0] = dcs_exit_sleep_mode;
dsi_send_dcs_packet(dcs, 1);
msleep(1);
dcs[0] = dcs_set_display_on;
dsi_send_dcs_packet(dcs, 1);
msleep(10);
dsi_enable_command_mode(0);
dsi_enable_video_mode(1);
//printk("++++++++++++++++%s:%d\n", __func__, __LINE__);
};
int rk_lcd_standby(u8 enable) {
u8 dcs[16] = {0};
if(dsi_is_active() != 1)
return -1;
if(enable) {
dsi_enable_video_mode(0);
dsi_enable_command_mode(1);
/*below is changeable*/
dcs[0] = dcs_set_display_off;
dsi_send_dcs_packet(dcs, 1);
msleep(1);
dcs[0] = dcs_enter_sleep_mode;
dsi_send_dcs_packet(dcs, 1);
msleep(1);
//printk("++++++++++++++++%s:%d\n", __func__, __LINE__);
} else {
/*below is changeable*/
rk_lcd_init();
//printk("++++++++++++++++%s:%d\n", __func__, __LINE__);
}
};
#endif
#endif

24
drivers/video/rockchip/transmitter/mipi_dsi.c
View File

@@ -38,11 +38,11 @@
static struct mipi_dsi_ops *dsi_ops[MAX_DSI_CHIPS] = {NULL};
static struct mipi_dsi_ops *cur_dsi_ops;
//static struct mipi_dsi_ops *cur_dsi_ops;
int register_dsi_ops(unsigned int id, struct mipi_dsi_ops *ops) {
int i = 0;
//int i = 0;
if(id > (MAX_DSI_CHIPS - 1))
return -EINVAL;
@@ -249,11 +249,31 @@ int dsi_is_active(unsigned int id) {
}
EXPORT_SYMBOL(dsi_is_active);
int dsi_is_enable(unsigned int id, u32 enable){
struct mipi_dsi_ops *ops = NULL;
if(id > (MAX_DSI_CHIPS - 1))
return -EINVAL;
ops = dsi_ops[id];
if(!ops)
return -EINVAL;
if(ops->dsi_is_enable)
ops->dsi_is_enable(ops->dsi, enable);
return 0;
}
EXPORT_SYMBOL(dsi_is_enable);
int dsi_send_dcs_packet(unsigned int id, unsigned char *packet, u32 n) {
struct mipi_dsi_ops *ops = NULL;
printk("dsi_send_dcs_packet-------id=%d\n",id);
if(id > (MAX_DSI_CHIPS - 1))
return -EINVAL;

61
drivers/video/rockchip/transmitter/mipi_dsi.h
View File

@@ -8,6 +8,13 @@ drivers/video/rockchip/transmitter/mipi_dsi.h
#include "..\..\common\config.h"
#endif
#ifdef CONFIG_OF
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <dt-bindings/gpio/gpio.h>
#endif
//DSI DATA TYPE
#define DTYPE_DCS_SWRITE_0P 0x05
#define DTYPE_DCS_SWRITE_1P 0x15
@@ -74,6 +81,11 @@ drivers/video/rockchip/transmitter/mipi_dsi.h
#define dcs_write_memory_continue 0x3c
#define dcs_write_memory_start 0x2c
#ifndef MHz
#define MHz 1000000
#endif
#if 0
typedef signed char s8;
typedef unsigned char u8;
@@ -180,15 +192,15 @@ struct mipi_dsi_ops {
int (*dsi_send_dcs_packet)(void *, unsigned char *, u32 n);
int (*dsi_read_dcs_packet)(void *, unsigned char *, u32 n);
int (*dsi_send_packet)(void *, void *, u32 n);
int (*dsi_is_enable)(void *, u32 enable);
int (*dsi_is_active)(void *);
int (*power_up)(void *);
int (*power_down)(void *);
};
/* Screen description */
struct mipi_dsi_screen {
u16 type;
u16 face;
u8 lcdc_id;
@@ -218,26 +230,45 @@ struct mipi_dsi_screen {
u8 dsi_lane;
u8 dsi_video_mode;
u32 hs_tx_clk;
#if defined(CONFIG_ARCH_RK3288)
u8 screen_init;
u8 mipi_screen_id;
int lcd_rst_gpio;
int lcd_rst_delay;
u8 lcd_rst_atv_val;
int lcd_en_gpio;
int lcd_en_dealay;
u8 lcd_en_atv_val;
#else
/* Operation function*/
int (*init)(void);
int (*standby)(u8 enable);
#endif
};
#define INVALID_GPIO -1
struct dcs_cmd {
u8 type;
u8 dsi_id;
u8 cmd_len;
int cmds[32];
int delay;
char name[32];
};
struct mipi_dcs_cmd_ctr_list {
struct list_head list;
struct dcs_cmd dcs_cmd;
};
struct mipi_screen
{
u8 screen_init;
u8 mipi_dsi_num;
u8 lcd_rst_atv_val;
u8 lcd_en_atv_val;
u8 dsi_lane;
u32 hs_tx_clk;
u32 lcd_en_gpio;
u32 lcd_en_delay;
u32 lcd_rst_gpio;
u32 lcd_rst_delay;
struct list_head cmdlist_head;
};
int register_dsi_ops(unsigned int id, struct mipi_dsi_ops *ops);
int del_dsi_ops(struct mipi_dsi_ops *ops);
@@ -255,4 +286,6 @@ int dsi_set_regs(unsigned int id, void *array, u32 n);
int dsi_send_dcs_packet(unsigned int id, unsigned char *packet, u32 n);
int dsi_read_dcs_packet(unsigned int id, unsigned char *packet, u32 n);
int dsi_send_packet(unsigned int id, void *packet, u32 n);
int dsi_is_enable(unsigned int id, u32 enable);
#endif /* end of MIPI_DSI_H_ */

777
drivers/video/rockchip/transmitter/rk616_mipi_dsi.c
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File diff suppressed because it is too large Load Diff

68
drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
View File

@@ -1,6 +1,7 @@
/*
drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
*/
#include <linux/rockchip/grf.h>
#ifndef RK616_MIPI_DSI_H
#define RK616_MIPI_DSI_H
@@ -122,7 +123,7 @@ drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
#define phylock DSI_HOST_BITS(0x60, 1, 0)
#else //***************************************************************//
//DWC_DSI_VERSION_0x3133302A
#define VERSION DSI_HOST_BITS(0x000, 32, 0)
#define shutdownz DSI_HOST_BITS(0x004, 1, 0)
#define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8)
@@ -143,8 +144,11 @@ drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
#define bta_en DSI_HOST_BITS(0x02c, 1, 2)
#define eotp_rx_en DSI_HOST_BITS(0x02c, 1, 1)
#define eotp_tx_en DSI_HOST_BITS(0x02c, 1, 0)
#define gen_vid_rx DSI_HOST_BITS(0x030, 2, 5)
#define gen_vid_rx DSI_HOST_BITS(0x030, 2, 0) //libing (0x030, 2, 5)-> (0x030, 2, 0)
#define cmd_video_mode DSI_HOST_BITS(0x034, 1, 0)
#define vpg_orientation DSI_HOST_BITS(0x038, 1, 24) //libing
#define vpg_mode DSI_HOST_BITS(0x038, 1, 20) //libing
#define vpg_en DSI_HOST_BITS(0x038, 1, 16) //libing
#define lp_cmd_en DSI_HOST_BITS(0x038, 1, 15)
#define frame_bta_ack_en DSI_HOST_BITS(0x038, 1, 14)
#define lp_hfp_en DSI_HOST_BITS(0x038, 1, 13)
@@ -189,8 +193,8 @@ drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
#define gen_cmd_empty DSI_HOST_BITS(0x074, 1, 0)
#define hstx_to_cnt DSI_HOST_BITS(0x078, 16, 16) //need modify
#define lprx_to_cnt DSI_HOST_BITS(0x078, 16, 0)
#define hs_rd_to_cnt DSI_HOST_BITS(0x07c, 16, 0) //new
#define lp_rd_to_cnt DSI_HOST_BITS(0x080, 16, 0) //new
#define hs_rd_to_cnt DSI_HOST_BITS(0x07c, 16, 0) //new(read)
#define lp_rd_to_cnt DSI_HOST_BITS(0x080, 16, 0) //new(read)
#define presp_to_mode DSI_HOST_BITS(0x084, 1, 24) //new
#define hs_wr_to_cnt DSI_HOST_BITS(0x084, 16, 0) //new
#define lp_wr_to_cnt DSI_HOST_BITS(0x088, 16, 0) //new
@@ -202,13 +206,15 @@ drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
//#define mode_3d DSI_HOST_BITS(0x090, 2, 0) //new
#define auto_clklane_ctrl DSI_HOST_BITS(0x094, 1, 1) //new
#define phy_txrequestclkhs DSI_HOST_BITS(0x094, 1, 0)
#define phy_hs2lp_time_clk_lane DSI_HOST_BITS(0x098, 10, 16) //libing
#define phy_hs2hs_time_clk_lane DSI_HOST_BITS(0x098, 10, 0) //libing
#define phy_hs2lp_time DSI_HOST_BITS(0x09c, 8, 24)
#define phy_lp2hs_time DSI_HOST_BITS(0x09c, 8, 16)
#define max_rd_time DSI_HOST_BITS(0x09c, 15, 0)
#define phy_forcepll DSI_HOST_BITS(0x0a0, 1, 3) //new
#define phy_forcepll DSI_HOST_BITS(0x0a0, 1, 3) //new Dependency: DSI_HOST_FPGA = 0. Otherwise, this bit is reserved.
#define phy_enableclk DSI_HOST_BITS(0x0a0, 1, 2)
//#define phy_rstz DSI_HOST_BITS(0x0a0, 1, 1)
//#define phy_shutdownz DSI_HOST_BITS(0x0a0, 1, 0)
#define phy_rstz DSI_HOST_BITS(0x0a0, 1, 1) //libing
#define phy_shutdownz DSI_HOST_BITS(0x0a0, 1, 0) //libing
#define phy_stop_wait_time DSI_HOST_BITS(0x0a4, 8, 8)
#define n_lanes DSI_HOST_BITS(0x0a4, 2, 0)
#define phy_txexitulpslan DSI_HOST_BITS(0x0a8, 1, 3)
@@ -225,10 +231,33 @@ drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
#define phy_testdout DSI_HOST_BITS(0x0b8, 8, 8)
#define phy_testdin DSI_HOST_BITS(0x0b8, 8, 0)
#define PHY_TEST_CTRL1 DSI_HOST_BITS(0x0b8, 17, 0)
#define PHY_TEST_CTRL0 DSI_HOST_BITS(0x0b4, 2, 0)
#define INT_ST0 DSI_HOST_BITS(0x0bc, 21, 0)
#define INT_ST1 DSI_HOST_BITS(0x0c0, 18, 0)
#define INT_MKS0 DSI_HOST_BITS(0x0c4, 21, 0)
#define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0)
#define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0) //libing
#define INT_FORCE0 DSI_HOST_BITS(0x0d8, 21, 0) //libing
#define INT_FORCE1 DSI_HOST_BITS(0x0dc, 18, 0) //libing
#define code_hs_rx_clock 0x34
#define code_hs_rx_lane0 0x44
#define code_hs_rx_lane1 0x54
#define code_hs_rx_lane2 0x84
#define code_hs_rx_lane3 0x94
#define code_pll_input_div_rat 0x17
#define code_pll_loop_div_rat 0x18
#define code_pll_input_loop_div_rat 0x19
#define code_hstxdatalanerequsetstatetime 0x70
#define code_hstxdatalanepreparestatetime 0x71
#define code_hstxdatalanehszerostatetime 0x72
//#define en_null_pkt DSI_HOST_BITS(0x1c, 1, 13) //delete
//#define en_multi_pkt DSI_HOST_BITS(0x1c, 1, 13) //delete
@@ -382,7 +411,6 @@ struct dsi_phy {
};
struct dsi_host {
u8 flag;
u8 lane;
@@ -396,20 +424,6 @@ struct dsi_host {
#endif
};
struct dcs_cmd {
int type;
int cmds[32];
int delay;
char name[32];
};
struct mipi_dcs_cmd_ctr_list {
struct list_head list;
struct dcs_cmd dcs_cmd;
};
struct dsi {
u8 dsi_id;
u8 lcdc_id;
@@ -426,14 +440,12 @@ struct dsi {
#endif
#endif
struct platform_device *pdev;
struct list_head cmdlist_head;
};
int rk_mipi_get_dsi_clk(void);
int rk_mipi_get_dsi_num(void);
int rk_mipi_get_dsi_lane(void);
#ifndef MHz
#define MHz 1000000
#endif
extern int rk616_mipi_dsi_ft_init(void);
int rk_mipi_dsi_init_lite(struct dsi *dsi);
#endif /* end of RK616_MIPI_DSI_H */