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drm/rockchip: vop2: add dsp_vcnt register define

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Adding the register definition for dsp_vcnt can improve compatibility.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ibd9a181834031fe2fd2d83eb1735b70ec1de3187
This commit is contained in:
Sandy Huang
2025-08-23 09:15:45 +08:00
parent 0d0de0337a
commit 571a6b9a39
3 changed files with 20 additions and 4 deletions
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3
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -1095,6 +1095,9 @@ struct vop2_video_port_regs {
/* clk calc*/
struct vop_reg calc_clk_en;
struct vop_reg calc_dclk_cnt;
/* dsp vcnt */
struct vop_reg dsp_vcnt;
};
struct vop2_power_domain_regs {

8
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -1650,13 +1650,13 @@ static bool vop2_fs_irq_is_pending(struct vop2_video_port *vp)
static uint32_t vop2_read_vcnt(struct vop2_video_port *vp)
{
uint32_t offset = RK3568_SYS_STATUS0 + (vp->id << 2);
struct vop2 *vop2 = vp->vop2;
uint32_t vcnt0, vcnt1;
int i = 0;
for (i = 0; i < 10; i++) {
vcnt0 = vop2_readl(vp->vop2, offset) >> 16;
vcnt1 = vop2_readl(vp->vop2, offset) >> 16;
vcnt0 = VOP_MODULE_GET(vop2, vp, dsp_vcnt);
vcnt1 = VOP_MODULE_GET(vop2, vp, dsp_vcnt);
if ((vcnt1 - vcnt0) <= 1)
break;
@@ -1664,7 +1664,7 @@ static uint32_t vop2_read_vcnt(struct vop2_video_port *vp)
if (i == 10) {
DRM_DEV_ERROR(vp->vop2->dev, "read VP%d vcnt error: %d %d\n", vp->id, vcnt0, vcnt1);
vcnt1 = vop2_readl(vp->vop2, offset) >> 16;
vcnt1 = VOP_MODULE_GET(vop2, vp, dsp_vcnt);
}
return vcnt1;

13
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1097,6 +1097,7 @@ static const struct vop2_video_port_regs rk3528_vop_vp0_regs = {
.csc_offset2 = VOP_REG(RK3528_VP0_CSC_OFFSET2, 0xffffffff, 0),
.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS0, 0x1fff, 16),
};
static const struct vop2_video_port_regs rk3528_vop_vp1_regs = {
@@ -1150,6 +1151,7 @@ static const struct vop2_video_port_regs rk3528_vop_vp1_regs = {
.layer_sel = VOP_REG(RK3528_OVL_PORT1_LAYER_SEL, 0xffff, 0),
.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS1, 0x1fff, 16),
};
static const struct vop3_ovl_mix_regs rk3576_vop_extra_mix_regs = {
@@ -1306,6 +1308,7 @@ static const struct vop2_video_port_regs rk3562_vop_vp0_regs = {
.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS0, 0x1fff, 16),
};
static const struct vop2_video_port_data rk3562_vop_video_ports[] = {
@@ -1412,6 +1415,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS0, 0x1fff, 16),
};
static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
@@ -1467,6 +1471,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS1, 0x1fff, 16),
};
static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
@@ -1522,6 +1527,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
.color_bar_mode = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS2, 0x1fff, 16),
};
static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
@@ -1681,6 +1687,7 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {
.calc_dclk_cnt = VOP_REG(RK3576_VP0_POST_CLK_CNT, 0x7fff, 0),
.calc_clk_en = VOP_REG(RK3576_VP0_POST_CLK_CNT, 0x1, 15),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS0, 0x1fff, 16),
};
static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
@@ -1773,6 +1780,7 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
.calc_dclk_cnt = VOP_REG(RK3576_VP1_POST_CLK_CNT, 0x7fff, 0),
.calc_clk_en = VOP_REG(RK3576_VP1_POST_CLK_CNT, 0x1, 15),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS1, 0x1fff, 16),
};
static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
@@ -1862,6 +1870,7 @@ static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
.calc_dclk_cnt = VOP_REG(RK3576_VP2_POST_CLK_CNT, 0x7fff, 0),
.calc_clk_en = VOP_REG(RK3576_VP2_POST_CLK_CNT, 0x1, 15),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS2, 0x1fff, 16),
};
static const struct vop3_ovl_regs rk3576_vop_vp0_ovl_regs = {
@@ -2041,6 +2050,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS0, 0x1fff, 16),
};
/*
@@ -2139,6 +2149,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS1, 0x1fff, 16),
};
static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
@@ -2203,6 +2214,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
.color_bar_mode = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS2, 0x1fff, 16),
};
static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
@@ -2262,6 +2274,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
.color_bar_mode = VOP_REG(RK3588_VP3_COLOR_BAR_CTRL, 0x1, 1),
.color_bar_en = VOP_REG(RK3588_VP3_COLOR_BAR_CTRL, 0x1, 0),
.dsp_vcnt = VOP_REG(RK3568_SYS_STATUS3, 0x1fff, 16),
};
static const struct vop2_video_port_data rk3588_vop_video_ports[] = {