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hdmitx: hdmitx bringup for tm2 [3/3]

Browse Source 
PD#SWPL-5617

Problem:
hdmitx bringup for tm2

Solution:
echo null > /sys/class/display/mode
echo 1080p60hz > /sys/class/display/mode

test method:
echo bist1920 > /sys/class/amhdmitx/amhdmitx0/debug
echo bistoff > /sys/class/amhdmitx/amhdmitx0/debug

Verify:
tm2 ptm

Change-Id: I4c69ec1e1e26c1ae7fde0fca5cd8b98c13e609f2
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
This commit is contained in:
Yi Zhou
2019-03-23 18:02:37 +08:00
committed by Jianxiong Pan
parent d807c881d0
commit 573c005b4e
10 changed files with 262 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arm/boot/dts/amlogic/mesontm2.dtsi
View File

@@ -1353,6 +1353,33 @@
clock-names = "vpu_clkc";
};
amhdmitx: amhdmitx{
compatible = "amlogic, amhdmitx";
dev_name = "amhdmitx";
status = "okay";
vend-data = <&vend_data>;
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_MUX>;
clock-names = "venci_top_gate",
"venci_0_gate",
"venci_1_gate",
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B 12:SM1 13:TM2
*/
ic_type = <13>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
vendor_id = <0x000000>;
};
};
ge2d {
compatible = "amlogic, ge2d-sm1";
status = "okay";

28
arch/arm64/boot/dts/amlogic/mesontm2.dtsi
View File

@@ -1333,6 +1333,34 @@
clock-names = "vpu_clkc";
};
amhdmitx: amhdmitx{
compatible = "amlogic, amhdmitx";
dev_name = "amhdmitx";
status = "okay";
vend-data = <&vend_data>;
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_MUX>;
clock-names = "venci_top_gate",
"venci_0_gate",
"venci_1_gate",
"hdmi_vapb_clk",
"hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
* 10:G12A 11:G12B 12:SM1 13:TM2
*/
ic_type = <13>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
vendor_id = <0x000000>;
};
};
ge2d {
compatible = "amlogic, ge2d-sm1";
status = "okay";

7
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
View File

@@ -4536,13 +4536,18 @@ static int amhdmitx_get_dt_info(struct platform_device *pdev)
pr_info(SYS "get hdmi platform data\n");
}
#endif
hdmitx_device.irq_hpd = platform_get_irq_byname(pdev, "hdmitx_hpd");
pr_info("hdmitx: testtest\n");
hdmitx_device.irq_hpd = 39;
// platform_get_irq_byname(pdev, "hdmitx_hpd");
#if 0
if (hdmitx_device.irq_hpd == -ENXIO) {
pr_err("%s: ERROR: hdmitx hpd irq No not found\n",
__func__);
return -ENXIO;
}
pr_info(SYS "hpd irq = %d\n", hdmitx_device.irq_hpd);
#endif
return ret;
}

1
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h
View File

@@ -67,6 +67,7 @@ void set_hpll_od3_g12a(unsigned int div);
int hdmitx_hpd_hw_op_txlx(enum hpd_op cmd);
int hdmitx_hpd_hw_op_g12a(enum hpd_op cmd);
int hdmitx_hpd_hw_op_tm2(enum hpd_op cmd);
int read_hpd_gpio_txlx(void);
int hdmitx_ddc_hw_op_txlx(enum ddc_op cmd);
extern unsigned int hdmitx_get_format_txlx(void);

97
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

@@ -119,6 +119,8 @@ int hdmitx_hpd_hw_op(enum hpd_op cmd)
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
return hdmitx_hpd_hw_op_g12a(cmd);
case MESON_CPU_ID_TM2:
return hdmitx_hpd_hw_op_tm2(cmd);
default:
break;
}
@@ -142,6 +144,7 @@ int read_hpd_gpio(void)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
return read_hpd_gpio_txlx();
default:
break;
@@ -166,6 +169,7 @@ int hdmitx_ddc_hw_op(enum ddc_op cmd)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
return hdmitx_ddc_hw_op_txlx(cmd);
default:
break;
@@ -395,6 +399,7 @@ static unsigned int hdmitx_get_format(void)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
ret = hdmitx_get_format_txlx();
break;
case MESON_CPU_ID_GXBB:
@@ -442,6 +447,7 @@ void hdmitx_sys_reset(void)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
hdmitx_sys_reset_txlx();
break;
case MESON_CPU_ID_GXBB:
@@ -1870,6 +1876,31 @@ static void set_phy_by_mode(unsigned int mode)
break;
}
break;
case MESON_CPU_ID_TM2:
switch (mode) {
case 1: /* 5.94/4.5/3.7Gbps */
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
if (hdev->dongle_mode)
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case 2: /* 2.97Gbps */
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb6262);
if (hdev->dongle_mode)
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0,
0x33eb4262);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
case 3: /* 1.485Gbps, and below */
default:
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL0, 0x33eb4242);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
}
break;
case MESON_CPU_ID_M8B:
case MESON_CPU_ID_GXBB:
case MESON_CPU_ID_GXTVBB:
@@ -1924,8 +1955,30 @@ static void hdmitx_set_phy(struct hdmitx_dev *hdev)
{
if (!hdev)
return;
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x0);
if (hdev->chip_type == MESON_CPU_ID_TM2) {
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x0);
/* P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset */
#define RESET_HDMI_PHY() \
do { \
hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0xf, 0, 4); \
mdelay(2); \
hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0xe, 0, 4); \
mdelay(2); \
} while (0)
hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0x0390, 16, 16);
hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0x1, 17, 1);
hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0x0, 17, 1);
hd_set_reg_bits(P_TM2_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4);
msleep(100);
RESET_HDMI_PHY();
RESET_HDMI_PHY();
RESET_HDMI_PHY();
#undef RESET_HDMI_PHY
} else {
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x0);
/* P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset */
#define RESET_HDMI_PHY() \
do { \
@@ -1935,16 +1988,17 @@ do { \
mdelay(2); \
} while (0)
hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0390, 16, 16);
hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x1, 17, 1);
if (hdev->chip_type >= MESON_CPU_ID_GXL)
hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 17, 1);
hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4);
msleep(100);
RESET_HDMI_PHY();
RESET_HDMI_PHY();
RESET_HDMI_PHY();
hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0390, 16, 16);
hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x1, 17, 1);
if (hdev->chip_type >= MESON_CPU_ID_GXL)
hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 17, 1);
hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4);
msleep(100);
RESET_HDMI_PHY();
RESET_HDMI_PHY();
RESET_HDMI_PHY();
#undef RESET_HDMI_PHY
}
switch (hdev->cur_VIC) {
case HDMI_4k2k_24:
@@ -2756,6 +2810,7 @@ static int hdmitx_cntl(struct hdmitx_dev *hdev, unsigned int cmd,
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 1, 29, 1);
udelay(50);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0, 28, 1);
@@ -4257,6 +4312,28 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf)
(P_HHI_HDMI_PHY_STATUS));
}
break;
case MESON_CPU_ID_TM2:
for (i = 0; i < 4; i++) {
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL1,
0x0390000f);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL1,
0x0390000e);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL1,
0x03904002);
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL4,
0x0001efff | (i << 20));
hd_write_reg(P_TM2_HHI_HDMI_PHY_CNTL1,
0xef904002);
mdelay(10);
if (i > 0)
pr_info("prbs D[%d]:%x\n", i - 1,
hd_read_reg
(P_TM2_HHI_HDMI_PHY_STATUS));
else
pr_info("prbs clk :%x\n", hd_read_reg
(P_TM2_HHI_HDMI_PHY_STATUS));
}
break;
default:
break;
}

10
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -166,6 +166,7 @@ void hdmitx_set_cts_hdcp22_clk(struct hdmitx_dev *hdev)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
default:
hd_write_reg(P_HHI_HDCP22_CLK_CNTL, 0x01000100);
break;
@@ -443,6 +444,7 @@ static void set_hpll_clk_out(unsigned int clk)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
set_g12a_hpll_clk_out(frac_rate, clk);
break;
default:
@@ -461,6 +463,7 @@ static void set_hpll_sspll(enum hdmi_vic vic)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
set_hpll_sspll_g12a(vic);
break;
case MESON_CPU_ID_GXBB:
@@ -507,6 +510,7 @@ static void set_hpll_od1(unsigned int div)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
set_hpll_od1_g12a(div);
break;
default:
@@ -546,6 +550,7 @@ static void set_hpll_od2(unsigned int div)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
set_hpll_od2_g12a(div);
break;
default:
@@ -587,6 +592,11 @@ static void set_hpll_od3(unsigned int div)
case MESON_CPU_ID_SM1:
set_hpll_od3_g12a(div);
break;
case MESON_CPU_ID_TM2:
set_hpll_od3_g12a(div);
/* new added in TM2 */
hd_set_reg_bits(P_HHI_LVDS_TX_PHY_CNTL1, 1, 29, 1);
break;
default:
set_hpll_od3_gxl(div);
break;

29
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
View File

@@ -411,6 +411,35 @@ int hdmitx_hpd_hw_op_g12a(enum hpd_op cmd)
return ret;
}
int hdmitx_hpd_hw_op_tm2(enum hpd_op cmd)
{
int ret = 0;
switch (cmd) {
case HPD_INIT_DISABLE_PULLUP:
hd_set_reg_bits(P_PAD_PULL_UP_REG2, 0, 16, 1);
break;
case HPD_INIT_SET_FILTER:
hdmitx_wr_reg(HDMITX_TOP_HPD_FILTER,
((0xa << 12) | (0xa0 << 0)));
break;
case HPD_IS_HPD_MUXED:
ret = !!(hd_read_reg(P_PERIPHS_PIN_MUX_9) & (6 << 0));
break;
case HPD_MUX_HPD:
hd_set_reg_bits(P_PERIPHS_PIN_MUX_9, 6, 0, 4);
break;
case HPD_UNMUX_HPD:
hd_set_reg_bits(P_PERIPHS_PIN_MUX_9, 0, 0, 4);
break;
case HPD_READ_HPD_GPIO:
ret = hdmitx_rd_reg(HDMITX_DWC_PHY_STAT0) & (1 << 1);
break;
default:
break;
}
return ret;
}
void set_hpll_sspll_g12a(enum hdmi_vic vic)
{

18
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
View File

@@ -154,6 +154,20 @@ void init_reg_map(unsigned int type);
#define PAD_PULL_UP_EN_REG4 0x4c
#define P_PAD_PULL_UP_EN_REG4 PERIPHS_REG_ADDR(PAD_PULL_UP_EN_REG4)
#define TM2_HHI_HDMI_PHY_CNTL0 0x05
#define P_TM2_HHI_HDMI_PHY_CNTL0 HHI_REG_ADDR(TM2_HHI_HDMI_PHY_CNTL0)
#define TM2_HHI_HDMI_PHY_CNTL1 0x06
#define P_TM2_HHI_HDMI_PHY_CNTL1 HHI_REG_ADDR(TM2_HHI_HDMI_PHY_CNTL1)
#define TM2_HHI_HDMI_PHY_CNTL2 0x07
#define P_TM2_HHI_HDMI_PHY_CNTL2 HHI_REG_ADDR(TM2_HHI_HDMI_PHY_CNTL2)
#define TM2_HHI_HDMI_PHY_CNTL3 0x08
#define P_TM2_HHI_HDMI_PHY_CNTL3 HHI_REG_ADDR(TM2_HHI_HDMI_PHY_CNTL3)
#define TM2_HHI_HDMI_PHY_CNTL4 0x09
#define P_TM2_HHI_HDMI_PHY_CNTL4 HHI_REG_ADDR(TM2_HHI_HDMI_PHY_CNTL4)
#define TM2_HHI_HDMI_PHY_CNTL5 0x0a
#define P_TM2_HHI_HDMI_PHY_CNTL5 HHI_REG_ADDR(TM2_HHI_HDMI_PHY_CNTL5)
#define TM2_HHI_HDMI_PHY_STATUS 0x0d
#define P_TM2_HHI_HDMI_PHY_STATUS HHI_REG_ADDR(TM2_HHI_HDMI_PHY_STATUS)
#define HHI_MEM_PD_REG0 0x40
#define P_HHI_MEM_PD_REG0 HHI_REG_ADDR(HHI_MEM_PD_REG0)
@@ -210,6 +224,10 @@ void init_reg_map(unsigned int type);
#define P_HHI_HDMI_AFC_CNTL HHI_REG_ADDR(HHI_HDMI_AFC_CNTL)
#define HHI_VPU_CLKB_CNTL 0x83
#define P_HHI_VPU_CLKB_CNTL HHI_REG_ADDR(HHI_VPU_CLKB_CNTL)
#define HHI_LVDS_TX_PHY_CNTL0 0x9a
#define P_HHI_LVDS_TX_PHY_CNTL0 HHI_REG_ADDR(HHI_LVDS_TX_PHY_CNTL0)
#define HHI_LVDS_TX_PHY_CNTL1 0x9b
#define P_HHI_LVDS_TX_PHY_CNTL1 HHI_REG_ADDR(HHI_LVDS_TX_PHY_CNTL1)
#define HHI_VDAC_CNTL0 0xbd
#define P_HHI_VDAC_CNTL0 HHI_REG_ADDR(HHI_VDAC_CNTL0)
#define HHI_VDAC_CNTL1 0xbe

55
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.c
View File

@@ -156,6 +156,46 @@ static struct reg_map reg_maps_g12a[] = {
},
};
/* For TM2 */
static struct reg_map reg_maps_tm2[] = {
[CBUS_REG_IDX] = { /* CBUS */
.phy_addr = 0xffd00000,
.size = 0x100000,
},
[PERIPHS_REG_IDX] = { /* PERIPHS */
.phy_addr = 0xff634400,
.size = 0x2000,
},
[VCBUS_REG_IDX] = { /* VPU */
.phy_addr = 0xff900000,
.size = 0x40000,
},
[AOBUS_REG_IDX] = { /* RTI */
.phy_addr = 0xff800000,
.size = 0x100000,
},
[HHI_REG_IDX] = { /* HIU */
.phy_addr = 0xff63c000,
.size = 0x2000,
},
[RESET_CBUS_REG_IDX] = { /* RESET */
.phy_addr = 0xffd00000,
.size = 0x1100,
},
[HDMITX_SEC_REG_IDX] = { /* HDMITX DWC LEVEL*/
.phy_addr = 0xff670000,
.size = 0x8000,
},
[HDMITX_REG_IDX] = { /* HDMITX TOP LEVEL*/
.phy_addr = 0xff678000,
.size = 0x4000,
},
[ELP_ESM_REG_IDX] = {
.phy_addr = 0xffe01000,
.size = 0x100,
},
};
static struct reg_map *map;
void init_reg_map(unsigned int type)
@@ -178,6 +218,19 @@ void init_reg_map(unsigned int type)
}
}
break;
case MESON_CPU_ID_TM2:
map = reg_maps_tm2;
for (i = 0; i < REG_IDX_END; i++) {
map[i].p = ioremap(map[i].phy_addr, map[i].size);
if (!map[i].p) {
pr_info("hdmitx20: failed Mapped PHY: 0x%x\n",
map[i].phy_addr);
} else {
pr_info("hdmitx20: Mapped PHY: 0x%x\n",
map[i].phy_addr);
}
}
break;
case MESON_CPU_ID_TXLX:
map = reg_maps_txlx;
break;
@@ -254,6 +307,7 @@ unsigned int hd_read_reg(unsigned int addr)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
default:
val = readl(TO_PMAP_ADDR(addr));
break;
@@ -304,6 +358,7 @@ void hd_write_reg(unsigned int addr, unsigned int val)
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
case MESON_CPU_ID_TM2:
default:
writel(val, TO_PMAP_ADDR(addr));
break;

1
include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
View File

@@ -43,6 +43,7 @@
#define MESON_CPU_ID_G12A 10
#define MESON_CPU_ID_G12B 11
#define MESON_CPU_ID_SM1 12
#define MESON_CPU_ID_TM2 13
/*****************************