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rk29: L2 Data RAM latency set to 9 cycles

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黄涛
2011-02-22 18:16:26 +08:00
parent 005c8d3581
commit 5854697912
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mm/proc-v7.S
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@@ -272,7 +272,7 @@ __v7_setup:
bic r5, r5, #7 << 6
bic r5, r5, #15
orr r5, r5, #3 << 6 @ Tag RAM latency: b011 = 4 cycles
orr r5, r5, #12 @ Data RAM latency: b0101 = 6 cycles
orr r5, r5, #8 @ Data RAM latency: b1000 = 9 cycles
mcr p15, 1, r5, c9, c0, 2
#endif