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hdmirx: modify input clk of aud pll [1/1]

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PD#SWPL-15343

Problem:
HBR audio cannot work well

Solution:
input clk of aud pll set to maximum.
and increase division coefficient at backend to ensure aud pll is right.

Verify:
on TL1 TM2

Change-Id: I243dde2d00327b924e265f26e7e31687c3e23ad1
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
This commit is contained in:
Lei Yang
2019-11-12 15:52:35 +08:00
committed by Luke Go
parent 185e20ea60
commit 58788b839b
2 changed files with 11 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -34,7 +34,7 @@
#include "hdmi_rx_edid.h"
#define RX_VER0 "ver.2019/10/21"
#define RX_VER0 "ver.2019/11/12"
/*
*
*

15
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -3892,11 +3892,16 @@ struct apll_param apll_tab[] = {
/*od for tmds: 2/4/8/16/32*/
/*od2 for audio: 1/2/4/8/16*/
/* bw M, N, od, od_div, od2, od2_div, aud_div */
{pll_frq_band_0, 160, 1, 0x5, 32, 0x2, 8, 2},/*tmdsx4*/
{pll_frq_band_1, 80, 1, 0x4, 16, 0x2, 8, 1},/*tmdsx2*/
{pll_frq_band_2, 40, 1, 0x3, 8, 0x2, 8, 0},/*tmds*/
{pll_frq_band_3, 40, 2, 0x2, 4, 0x1, 4, 0},/*tmds*/
{pll_frq_band_4, 40, 1, 0x1, 2, 0x0, 2, 0},/*tmds*/
/* {pll_frq_band_0, 160, 1, 0x5, 32,0x2, 8, 2}, */
{pll_frq_band_0, 160, 1, 0x5, 32, 0x1, 8, 3},/* 16 x 27 */
/* {pll_frq_band_1, 80, 1, 0x4, 16, 0x2, 8, 1}, */
{pll_frq_band_1, 80, 1, 0x4, 16, 0x0, 8, 3},/* 8 x 74 */
/* {pll_frq_band_2, 40, 1, 0x3, 8, 0x2, 8, 0}, */
{pll_frq_band_2, 40, 1, 0x3, 8, 0x0, 8, 2}, /* 4 x 148 */
/* {pll_frq_band_3, 40, 2, 0x2, 4, 0x1, 4, 0}, */
{pll_frq_band_3, 40, 2, 0x2, 4, 0x0, 4, 1},/* 2 x 297 */
/* {pll_frq_band_4, 40, 1, 0x1, 2, 0x0, 2, 0}, */
{pll_frq_band_4, 40, 1, 0x1, 2, 0x0, 2, 0},/* 594 */
{pll_frq_null, 40, 1, 0x3, 8, 0x2, 8, 0},
};