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clk: rockchip: half-divider: Use maximal and best divider
The bigger the divider, the better the clock jitter. Change-Id: I4b4e06c71c2f0bdb0e32422fb42c8d490c3ec4bd Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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@@ -14,9 +14,9 @@ static bool _is_best_half_div(unsigned long rate, unsigned long now,
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unsigned long best, unsigned long flags)
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{
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if (flags & CLK_DIVIDER_ROUND_CLOSEST)
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return abs(rate - now) < abs(rate - best);
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return abs(rate - now) <= abs(rate - best);
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return now <= rate && now > best;
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return now <= rate && now >= best;
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}
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static unsigned long clk_half_divider_recalc_rate(struct clk_hw *hw,
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@@ -38,7 +38,7 @@ static int clk_half_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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{
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unsigned int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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unsigned long parent_rate_saved = *best_parent_rate;
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bool is_bestdiv = false;
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if (!rate)
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rate = 1;
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@@ -51,7 +51,7 @@ static int clk_half_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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if (bestdiv < 3)
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bestdiv = 0;
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else
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bestdiv = (bestdiv - 3) / 2;
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bestdiv = DIV_ROUND_UP(bestdiv - 3, 2);
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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}
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@@ -63,28 +63,20 @@ static int clk_half_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 0; i <= maxdiv; i++) {
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if (((u64)rate * (i * 2 + 3)) == ((u64)parent_rate_saved * 2)) {
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/*
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* It's the most ideal case if the requested rate can be
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* divided from parent clock without needing to change
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* parent rate, so return the divider immediately.
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*/
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*best_parent_rate = parent_rate_saved;
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return i;
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}
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parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
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((u64)rate * (i * 2 + 3)) / 2);
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now = DIV_ROUND_UP_ULL(((u64)parent_rate * 2),
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(i * 2 + 3));
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if (_is_best_half_div(rate, now, best, flags)) {
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is_bestdiv = true;
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bestdiv = i;
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best = now;
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*best_parent_rate = parent_rate;
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}
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}
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if (!bestdiv) {
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if (!is_bestdiv) {
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bestdiv = div_mask(width);
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*best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
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}
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@@ -114,7 +106,7 @@ static int clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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u32 val;
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value = DIV_ROUND_UP_ULL(((u64)parent_rate * 2), rate);
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value = (value - 3) / 2;
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value = DIV_ROUND_UP(value - 3, 2);
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value = min_t(unsigned int, value, div_mask(divider->width));
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if (divider->lock)
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