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dv: add dolby vision driver for g12a

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PD#156734: dv: add dolby vision driver for g12a

Change-Id: I02490c69f6f834f491278403dfcc8923a3fcee77
Signed-off-by: zhilei.wu <zhilei.wu@amlogic.com>
This commit is contained in:
zhilei.wu
2018-03-02 15:43:21 +08:00
committed by Yixun Lan
parent b2eca7a2de
commit 59aee35fda
30 changed files with 7491 additions and 2774 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
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@@ -14367,3 +14367,8 @@ F: sound/soc/amlogic/auge/*
AMLOGIC G12A BL_EXTERN LP8556 DRIVER
M: Weiming Liu <weiming.liu@amlogic.com>
F: drivers/amlogic/media/vout/backlight/bl_extern/bl_extern_i2c.c
AMLOGIC G12A Dolby Vision DRIVER
M: Zhilei Wu <zhilei.wu@amlogic.com>
F: drivers/amlogic/media/enhancement/amdolby_vision*
F: include/linux/amlogic/media/amdolbyvision/*

6
arch/arm64/boot/dts/amlogic/g12a_skt.dts
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@@ -869,7 +869,11 @@
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
};
amdolby_vision {
compatible = "amlogic, aml_amdolby_vision_driver";
dev_name = "aml_amdolby_vision_driver";
status = "okay";
};
meson-amvideom {
compatible = "amlogic, amvideom";
dev_name = "amvideom";

6
arch/arm64/boot/dts/amlogic/g12a_skt_buildroot.dts
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@@ -980,7 +980,11 @@
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
};
amdolby_vision {
compatible = "amlogic, aml_amdolby_vision_driver";
dev_name = "aml_amdolby_vision_driver";
status = "okay";
};
meson-amvideom {
compatible = "amlogic, amvideom";
dev_name = "amvideom";

1
arch/arm64/configs/meson64_defconfig
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@@ -309,6 +309,7 @@ CONFIG_AMLOGIC_IONVIDEO=y
CONFIG_AMLOGIC_PIC_DEC=y
CONFIG_AMLOGIC_MEDIA_ENHANCEMENT=y
CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM=y
CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION=y
CONFIG_AMLOGIC_MMC=y
CONFIG_AMLOGIC_NAND=y
CONFIG_AMLOGIC_VRTC=y

1
arch/arm64/configs/meson64_smarthome_defconfig
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@@ -278,6 +278,7 @@ CONFIG_AMLOGIC_VIDEOBUF2_ION=y
CONFIG_AMLOGIC_IONVIDEO=y
CONFIG_AMLOGIC_MEDIA_ENHANCEMENT=y
CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM=y
CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION=y
CONFIG_AMLOGIC_MMC=y
CONFIG_AMLOGIC_NAND=y
CONFIG_AMLOGIC_VRTC=y

4
drivers/amlogic/media/common/vfm/vfm.c
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@@ -397,7 +397,7 @@ static void vfm_init(void)
char tvpath_chain[] = "vdin0 deinterlace amvideo";
#endif
#endif /**/
#ifdef CONFIG_AM_VDEC_DV
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
char def_dvbl_id[] = "dvblpath";
/* char def_dvbl_chain[] = "dvbldec dvbl amvideo";*/
char def_dvbl_chain[] = "dvbldec amvideo";
@@ -427,7 +427,7 @@ static void vfm_init(void)
#ifdef CONFIG_AMLOGIC_V4L_VIDEO2
vfm_map_add(def_amlvideo2_id, def_amlvideo2_chain);
#endif /**/
#ifdef CONFIG_AM_VDEC_DV
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
vfm_map_add(def_dvbl_id, def_dvbl_chain);
vfm_map_add(def_dvel_id, def_dvel_chain);
#endif

1
drivers/amlogic/media/enhancement/Kconfig
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@@ -11,6 +11,7 @@ config AMLOGIC_MEDIA_ENHANCEMENT
if AMLOGIC_MEDIA_ENHANCEMENT
source "drivers/amlogic/media/enhancement/amvecm/Kconfig"
source "drivers/amlogic/media/enhancement/amdolby_vision/Kconfig"
endif
endmenu

1
drivers/amlogic/media/enhancement/Makefile
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@@ -1 +1,2 @@
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) += amvecm/
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION) += amdolby_vision/

15
drivers/amlogic/media/enhancement/amdolby_vision/Kconfig Normal file
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@@ -0,0 +1,15 @@
#
# AMLOGIC amdolby_vision devices configuration
#
comment "Amlogic amdolby_vision Drivers"
menu "Amlogic amdolby_vision Driver"
config AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
bool "Amlogic amdolby_vision driver"
default n
help
"Amlogic amdolby_vision module init"
endmenu

7
drivers/amlogic/media/enhancement/amdolby_vision/Makefile Normal file
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@@ -0,0 +1,7 @@
#
# Makefile for amdolby_vision
#
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION) += amdolby_vision.o

6042
drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c Normal file
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File diff suppressed because it is too large Load Diff

623
drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.h Normal file
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@@ -0,0 +1,623 @@
/*
* drivers/amlogic/media/enhancement/amvecm/dolby_vision/amdolby_vision.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _AMDV_H_
#define _AMDV_H_
#define V1_5
#define V2_4
#include <linux/types.h>
#define DEF_G2L_LUT_SIZE_2P 8
#define DEF_G2L_LUT_SIZE (1 << DEF_G2L_LUT_SIZE_2P)
#ifdef V2_4
#define EXT_MD_AVAIL_LEVEL_1 (1 << 0)
#define EXT_MD_AVAIL_LEVEL_2 (1 << 1)
#define EXT_MD_AVAIL_LEVEL_4 (1 << 2)
#define EXT_MD_AVAIL_LEVEL_5 (1 << 3)
#define EXT_MD_AVAIL_LEVEL_6 (1 << 4)
#define EXT_MD_AVAIL_LEVEL_255 (1 << 31)
#endif
#define PQ2G_LUT_SIZE (4 + 1024 * 4 + 16 * 3)
#define GM_LUT_HDR_SIZE (13 + 2*9)
#define LUT_DIM 17
#define GM_LUT_SIZE (3 * LUT_DIM * LUT_DIM * LUT_DIM * 2)
#define BACLIGHT_LUT_SIZE 4096
#define TUNING_LUT_ENTRIES 14
#define TUNINGMODE_FORCE_ABSOLUTE 0x1
#define TUNINGMODE_EXTLEVEL1_DISABLE 0x2
#define TUNINGMODE_EXTLEVEL2_DISABLE 0x4
#define TUNINGMODE_EXTLEVEL4_DISABLE 0x8
#define TUNINGMODE_EXTLEVEL5_DISABLE 0x10
#define TUNINGMODE_EL_FORCEDDISABLE 0x20
/*! @brief Output CSC configuration.*/
# pragma pack(push, 1)
struct TgtOutCscCfg {
int32_t lms2RgbMat[3][3]; /**<@brief LMS to RGB matrix */
int32_t lms2RgbMatScale; /**<@brief LMS 2 RGB matrix scale */
uint8_t whitePoint[3]; /**<@brief White point */
uint8_t whitePointScale; /**<@brief White point scale */
int32_t reserved[3];
};
#pragma pack(pop)
/*! @brief Global dimming configuration.*/
# pragma pack(push, 1)
struct TgtGDCfg {
int32_t gdEnable;
uint32_t gdWMin;
uint32_t gdWMax;
uint32_t gdWMm;
uint32_t gdWDynRngSqrt;
uint32_t gdWeightMean;
uint32_t gdWeightStd;
uint32_t gdDelayMilliSec_hdmi;
int32_t gdRgb2YuvExt;
int32_t gdM33Rgb2Yuv[3][3];
int32_t gdM33Rgb2YuvScale2P;
int32_t gdRgb2YuvOffExt;
int32_t gdV3Rgb2YuvOff[3];
uint32_t gdUpBound;
uint32_t gdLowBound;
uint32_t lastMaxPq;
uint16_t gdWMinPq;
uint16_t gdWMaxPq;
uint16_t gdWMmPq;
uint16_t gdTriggerPeriod;
uint32_t gdTriggerLinThresh;
uint32_t gdDelayMilliSec_ott;
#ifdef V1_5
uint32_t reserved[6];
#else
uint32_t reserved[9];
#endif
};
#pragma pack(pop)
/*! @defgroup general Enumerations and data structures*/
# pragma pack(push, 1)
struct TargetDisplayConfig {
uint16_t gain;
uint16_t offset;
uint16_t gamma; /**<@brief Gamma */
uint16_t eotf;
uint16_t bitDepth; /**<@brief Bit Depth */
uint16_t rangeSpec;
uint16_t diagSize; /**<@brief Diagonal Size */
uint16_t maxPq;
uint16_t minPq;
uint16_t mSWeight;
uint16_t mSEdgeWeight;
int16_t minPQBias;
int16_t midPQBias;
int16_t maxPQBias;
int16_t trimSlopeBias;
int16_t trimOffsetBias;
int16_t trimPowerBias;
int16_t msWeightBias;
int16_t brightness; /**<@brief Brighness */
int16_t contrast; /**<@brief Contrast */
int16_t chromaWeightBias;
int16_t saturationGainBias;
uint16_t chromaWeight;
uint16_t saturationGain;
uint16_t crossTalk;
uint16_t tuningMode;
int16_t reserved0;
int16_t dbgExecParamsPrintPeriod;
int16_t dbgDmMdPrintPeriod;
int16_t dbgDmCfgPrintPeriod;
uint16_t maxPq_dupli;
uint16_t minPq_dupli;
int32_t keyWeight;
int32_t intensityVectorWeight;
int32_t chromaVectorWeight;
int16_t chip_fpga_lowcomplex;
int16_t midPQBiasLut[TUNING_LUT_ENTRIES];
int16_t saturationGainBiasLut[TUNING_LUT_ENTRIES];
int16_t chromaWeightBiasLut[TUNING_LUT_ENTRIES];
int16_t slopeBiasLut[TUNING_LUT_ENTRIES];
int16_t offsetBiasLut[TUNING_LUT_ENTRIES];
int16_t backlightBiasLut[TUNING_LUT_ENTRIES];
struct TgtGDCfg gdConfig;
#ifdef V1_5
uint8_t vsvdb[7];
uint8_t reserved1[5];
#endif
int32_t min_lin;
int32_t max_lin;
int16_t backlight_scaler;
int32_t min_lin_dupli;
int32_t max_lin_dupli;
struct TgtOutCscCfg ocscConfig;
#ifdef V1_5
int16_t reserved2;
#else
int16_t reserved00;
#endif
int16_t brightnessPreservation;
int32_t iintensityVectorWeight;
int32_t ichromaVectorWeight;
int16_t isaturationGainBias;
int16_t chip_12b_ocsc;
int16_t chip_512_tonecurve;
int16_t chip_nolvl5;
int16_t padding[8];
};
#pragma pack(pop)
/*! @brief PQ config main data structure.*/
struct pq_config_s {
unsigned char default_gm_lut[GM_LUT_HDR_SIZE + GM_LUT_SIZE];
unsigned char gd_gm_lut_min[GM_LUT_HDR_SIZE + GM_LUT_SIZE];
unsigned char gd_gm_lut_max[GM_LUT_HDR_SIZE + GM_LUT_SIZE];
unsigned char pq2gamma[sizeof(int32_t)*PQ2G_LUT_SIZE];
unsigned char backlight_lut[BACLIGHT_LUT_SIZE];
struct TargetDisplayConfig target_display_config;
};
enum input_mode_e {
INPUT_MODE_OTT = 0,
INPUT_MODE_HDMI = 1
};
struct ui_menu_params_s {
uint16_t u16BackLightUIVal;
uint16_t u16BrightnessUIVal;
uint16_t u16ContrastUIVal;
};
enum signal_format_e {
FORMAT_INVALID = -1,
FORMAT_DOVI = 0,
FORMAT_HDR10 = 1,
FORMAT_SDR = 2,
FORMAT_DOVI_LL = 3
};
enum priority_mode_e {
VIDEO_PRIORITY = 0,
GRAPHIC_PRIORITY = 1
};
enum cp_signal_range_e {
SIG_RANGE_SMPTE = 0, /* head range */
SIG_RANGE_FULL = 1, /* full range */
SIG_RANGE_SDI = 2 /* PQ */
};
enum graphics_format_e {
GF_SDR_YUV = 0, /* BT.709 YUV BT1886 */
GF_SDR_RGB = 1, /* BT.709 RGB BT1886 */
GF_HDR_YUV = 2, /* BT.2020 YUV PQ */
GF_HDR_RGB = 3 /* BT.2020 RGB PQ */
};
struct run_mode_s {
uint16_t width;
uint16_t height;
uint16_t el_width;
uint16_t el_height;
uint16_t hdmi_mode;
};
struct composer_register_ipcore_s {
/* offset 0xc8 */
uint32_t Composer_Mode;
uint32_t VDR_Resolution;
uint32_t Bit_Depth;
uint32_t Coefficient_Log2_Denominator;
uint32_t BL_Num_Pivots_Y;
uint32_t BL_Pivot[5];
uint32_t BL_Order;
uint32_t BL_Coefficient_Y[8][3];
uint32_t EL_NLQ_Offset_Y;
uint32_t EL_Coefficient_Y[3];
uint32_t Mapping_IDC_U;
uint32_t BL_Num_Pivots_U;
uint32_t BL_Pivot_U[3];
uint32_t BL_Order_U;
uint32_t BL_Coefficient_U[4][3];
uint32_t MMR_Coefficient_U[22][2];
uint32_t MMR_Order_U;
uint32_t EL_NLQ_Offset_U;
uint32_t EL_Coefficient_U[3];
uint32_t Mapping_IDC_V;
uint32_t BL_Num_Pivots_V;
uint32_t BL_Pivot_V[3];
uint32_t BL_Order_V;
uint32_t BL_Coefficient_V[4][3];
uint32_t MMR_Coefficient_V[22][2];
uint32_t MMR_Order_V;
uint32_t EL_NLQ_Offset_V;
uint32_t EL_Coefficient_V[3];
};
/** @brief DM registers for IPCORE 1 */
struct dm_register_ipcore_1_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Frame_Format_1;
uint32_t Frame_Format_2;
uint32_t Frame_Pixel_Def;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t EOTF;
/* uint32_t Sparam_1;*/
/* uint32_t Sparam_2;*/
/* uint32_t Sgamma; */
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t Active_area_left_top;
uint32_t Active_area_bottom_right;
};
/** @brief DM registers for IPCORE 2 */
struct dm_register_ipcore_2_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t Frame_Format;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t VDR_Resolution;
};
/** @brief DM registers for IPCORE 3 */
struct dm_register_ipcore_3_s {
uint32_t D2C_coefficient_1;
uint32_t D2C_coefficient_2;
uint32_t D2C_coefficient_3;
uint32_t D2C_coefficient_4;
uint32_t D2C_coefficient_5;
uint32_t B2A_Coefficient_1;
uint32_t B2A_Coefficient_2;
uint32_t B2A_Coefficient_3;
uint32_t B2A_Coefficient_4;
uint32_t B2A_Coefficient_5;
uint32_t Eotf_param_1;
uint32_t Eotf_param_2;
uint32_t IPT_Scale;
uint32_t IPT_Offset_1;
uint32_t IPT_Offset_2;
uint32_t IPT_Offset_3;
uint32_t Output_range_1;
uint32_t Output_range_2;
uint32_t RGB2YUV_coefficient_register1;
uint32_t RGB2YUV_coefficient_register2;
uint32_t RGB2YUV_coefficient_register3;
uint32_t RGB2YUV_coefficient_register4;
uint32_t RGB2YUV_coefficient_register5;
uint32_t RGB2YUV_offset_0;
uint32_t RGB2YUV_offset_1;
uint32_t RGB2YUV_offset_2;
};
/** @brief DM luts for IPCORE 1 and 2 */
struct dm_lut_ipcore_s {
uint32_t TmLutI[64*4];
uint32_t TmLutS[64*4];
uint32_t SmLutI[64*4];
uint32_t SmLutS[64*4];
uint32_t G2L[DEF_G2L_LUT_SIZE];
};
/** @brief hdmi metadata for IPCORE 3 */
struct md_reister_ipcore_3_s {
uint32_t raw_metadata[128];
uint32_t size;
};
struct hdr_10_infoframe_s {
uint8_t infoframe_type_code;
uint8_t infoframe_version_number;
uint8_t length_of_info_frame;
uint8_t data_byte_1;
uint8_t data_byte_2;
uint8_t display_primaries_x_0_LSB;
uint8_t display_primaries_x_0_MSB;
uint8_t display_primaries_y_0_LSB;
uint8_t display_primaries_y_0_MSB;
uint8_t display_primaries_x_1_LSB;
uint8_t display_primaries_x_1_MSB;
uint8_t display_primaries_y_1_LSB;
uint8_t display_primaries_y_1_MSB;
uint8_t display_primaries_x_2_LSB;
uint8_t display_primaries_x_2_MSB;
uint8_t display_primaries_y_2_LSB;
uint8_t display_primaries_y_2_MSB;
uint8_t white_point_x_LSB;
uint8_t white_point_x_MSB;
uint8_t white_point_y_LSB;
uint8_t white_point_y_MSB;
uint8_t max_display_mastering_luminance_LSB;
uint8_t max_display_mastering_luminance_MSB;
uint8_t min_display_mastering_luminance_LSB;
uint8_t min_display_mastering_luminance_MSB;
uint8_t max_content_light_level_LSB;
uint8_t max_content_light_level_MSB;
uint8_t max_frame_average_light_level_LSB;
uint8_t max_frame_average_light_level_MSB;
};
struct hdr10_param_s {
uint32_t min_display_mastering_luminance;
uint32_t max_display_mastering_luminance;
uint16_t Rx;
uint16_t Ry;
uint16_t Gx;
uint16_t Gy;
uint16_t Bx;
uint16_t By;
uint16_t Wx;
uint16_t Wy;
uint16_t max_content_light_level;
uint16_t max_pic_average_light_level;
};
#ifdef V2_4
struct ext_level_1_s {
uint8_t min_PQ_hi;
uint8_t min_PQ_lo;
uint8_t max_PQ_hi;
uint8_t max_PQ_lo;
uint8_t avg_PQ_hi;
uint8_t avg_PQ_lo;
};
struct ext_level_2_s {
uint8_t target_max_PQ_hi;
uint8_t target_max_PQ_lo;
uint8_t trim_slope_hi;
uint8_t trim_slope_lo;
uint8_t trim_offset_hi;
uint8_t trim_offset_lo;
uint8_t trim_power_hi;
uint8_t trim_power_lo;
uint8_t trim_chroma_weight_hi;
uint8_t trim_chroma_weight_lo;
uint8_t trim_saturation_gain_hi;
uint8_t trim_saturation_gain_lo;
uint8_t ms_weight_hi;
uint8_t ms_weight_lo;
};
struct ext_level_4_s {
uint8_t anchor_PQ_hi;
uint8_t anchor_PQ_lo;
uint8_t anchor_power_hi;
uint8_t anchor_power_lo;
};
struct ext_level_5_s {
uint8_t active_area_left_offset_hi;
uint8_t active_area_left_offset_lo;
uint8_t active_area_right_offset_hi;
uint8_t active_area_right_offset_lo;
uint8_t active_area_top_offset_hi;
uint8_t active_area_top_offset_lo;
uint8_t active_area_bottom_offset_hi;
uint8_t active_area_bottom_offset_lo;
};
struct ext_level_6_s {
uint8_t max_display_mastering_luminance_hi;
uint8_t max_display_mastering_luminance_lo;
uint8_t min_display_mastering_luminance_hi;
uint8_t min_display_mastering_luminance_lo;
uint8_t max_content_light_level_hi;
uint8_t max_content_light_level_lo;
uint8_t max_frame_average_light_level_hi;
uint8_t max_frame_average_light_level_lo;
};
struct ext_level_255_s {
uint8_t dm_run_mode;
uint8_t dm_run_version;
uint8_t dm_debug0;
uint8_t dm_debug1;
uint8_t dm_debug2;
uint8_t dm_debug3;
};
struct ext_md_s {
uint32_t available_level_mask;
struct ext_level_1_s level_1;
struct ext_level_2_s level_2;
struct ext_level_4_s level_4;
struct ext_level_5_s level_5;
struct ext_level_6_s level_6;
struct ext_level_255_s level_255;
};
#endif
struct dovi_setting_s {
struct composer_register_ipcore_s comp_reg;
struct dm_register_ipcore_1_s dm_reg1;
struct dm_register_ipcore_2_s dm_reg2;
struct dm_register_ipcore_3_s dm_reg3;
struct dm_lut_ipcore_s dm_lut1;
struct dm_lut_ipcore_s dm_lut2;
/* for dovi output */
struct md_reister_ipcore_3_s md_reg3;
/* for hdr10 output */
struct hdr_10_infoframe_s hdr_info;
/* current process */
enum signal_format_e src_format;
enum signal_format_e dst_format;
/* enhanced layer */
bool el_flag;
bool el_halfsize_flag;
/* frame width & height */
uint32_t video_width;
uint32_t video_height;
#ifdef V2_4
/* use for stb 2.4 */
enum graphics_format_e g_format;
uint32_t g_bitdepth;
uint32_t dovi2hdr10_nomapping;
uint32_t use_ll_flag;
uint32_t ll_rgb_desired;
uint32_t diagnostic_enable;
uint32_t diagnostic_mux_select;
uint32_t dovi_ll_enable;
uint32_t vout_width;
uint32_t vout_height;
u8 vsvdb_tbl[32];
struct ext_md_s ext_md;
uint32_t vsvdb_len;
uint32_t vsvdb_changed;
#endif
};
struct amdolby_vision_port_t {
const char *name;
struct device *dev;
const struct file_operations *fops;
void *runtime;
};
extern int control_path(
enum signal_format_e in_format,
enum signal_format_e out_format,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
enum priority_mode_e set_priority,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
int set_graphic_min_lum, int set_graphic_max_lum,
int set_target_min_lum, int set_target_max_lum,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct dovi_setting_s *output);
struct tv_dovi_setting_s {
uint64_t core1_reg_lut[3754];
/* current process */
enum signal_format_e src_format;
enum signal_format_e dst_format;
/* enhanced layer */
bool el_flag;
bool el_halfsize_flag;
/* frame width & height */
uint32_t video_width;
uint32_t video_height;
enum input_mode_e input_mode;
};
extern int tv_control_path(
enum signal_format_e in_format,
enum input_mode_e in_mode,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
struct pq_config_s *pq_config,
struct ui_menu_params_s *menu_param,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct tv_dovi_setting_s *output);
extern void *metadata_parser_init(int flag);
extern int metadata_parser_reset(int flag);
extern int metadata_parser_process(
char *src_rpu, int rpu_len,
char *dst_comp, int *comp_len,
char *dst_md, int *md_len, bool src_eos);
extern void metadata_parser_release(void);
struct dolby_vision_func_s {
const char *version_info;
void * (*metadata_parser_init)(int flag);
int (*metadata_parser_reset)(int flag);
int (*metadata_parser_process)(
char *src_rpu, int rpu_len,
char *dst_comp, int *comp_len,
char *dst_md, int *md_len, bool src_eos);
void (*metadata_parser_release)(void);
int (*control_path)(
enum signal_format_e in_format,
enum signal_format_e out_format,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
enum priority_mode_e set_priority,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
int set_graphic_min_lum, int set_graphic_max_lum,
int set_target_min_lum, int set_target_max_lum,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct dovi_setting_s *output);
int (*tv_control_path)(
enum signal_format_e in_format,
enum input_mode_e in_mode,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
struct pq_config_s *pq_config,
struct ui_menu_params_s *menu_param,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct tv_dovi_setting_s *output);
};
extern int register_dv_functions(const struct dolby_vision_func_s *func);
extern int unregister_dv_functions(void);
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)
#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
WRITE_VPP_REG_BITS(adr, val, start, len)
#else
extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
extern u32 VSYNC_RD_MPEG_REG(u32 adr);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#endif
#endif

3
drivers/amlogic/media/enhancement/amvecm/Makefile
View File

@@ -2,7 +2,6 @@
# AMLOGIC VE & CM.
#
ccflags-y := -I$(PWD)/$(src)/dolby_vision/
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) += am_vecm.o
am_vecm-objs := amve.o amcm.o amcsc.o amvecm.o amdolby_vision.o keystone_correction.o bitdepth.o set_hdr2_v0.o
am_vecm-objs := amve.o amcm.o amcsc.o amvecm.o keystone_correction.o bitdepth.o set_hdr2_v0.o

15
drivers/amlogic/media/enhancement/amvecm/amcm.c
View File

@@ -28,6 +28,7 @@
#include "arch/cm_regs.h"
#include "amcm.h"
#include "amcm_regmap.h"
#include <linux/amlogic/media/amdolbyvision/dolby_vision.h>
#define pr_amcm_dbg(fmt, args...)\
do {\
@@ -249,15 +250,13 @@ void amcm_enable(void)
{
int temp;
if (!is_dolby_vision_enable()) {
if (!(READ_VPP_REG(VPP_MISC) & (0x1 << 28)))
WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1);
if (!(READ_VPP_REG(VPP_MISC) & (0x1 << 28)))
WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1);
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
if (!(temp & 0x2)) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
if (!(temp & 0x2)) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp | 0x2);
}
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp | 0x2);
}
}

93
drivers/amlogic/media/enhancement/amvecm/amcsc.c
View File

@@ -35,7 +35,7 @@
#include "amcsc.h"
#include "set_hdr2_v0.h"
#include <linux/amlogic/media/amdolbyvision/dolby_vision.h>
#define pr_csc(fmt, args...)\
do {\
@@ -2585,6 +2585,97 @@ static void vpp_set_mtx_en_read(void)
OSD1_MTX_EN_MASK);
}
/* dvll output 12bit */
static int dvll_RGB_to_YUV709l_coeff[MATRIX_5x3_COEF_SIZE] = {
0, 0, 0, /* pre offset */
COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765),
COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
0, 0, 0, /* 10'/11'/12' */
0, 0, 0, /* 20'/21'/22' */
64, 512, 512, /* offset */
0, 0, 0 /* mode, right_shift, clip_en */
};
static int *cur_post_mtx = bypass_coeff;
static int cur_post_on = CSC_OFF;
static int32_t *post_mtx_backup;
static int32_t post_on_backup;
static bool restore_post_table;
/* coeff: pointer to target coeff array */
/* bits: how many bits for target coeff, could be 10 ~ 12, default 10 */
int enable_rgb_to_yuv_matrix_for_dvll(
int32_t on, uint32_t *coeff_orig, uint32_t bits)
{
int32_t i, j;
uint32_t coeff01, coeff23, coeff45, coeff67;
uint32_t coeff8, scale, shift, offset[3];
int32_t *coeff = dvll_RGB_to_YUV709l_coeff;
if ((bits < 10) || (bits > 12))
return -1;
if (on && !coeff_orig)
return -2;
if (on) {
/* only store the start one */
if (cur_post_mtx !=
dvll_RGB_to_YUV709l_coeff) {
post_mtx_backup = cur_post_mtx;
post_on_backup = cur_post_on;
}
coeff01 = coeff_orig[0];
coeff23 = coeff_orig[1];
coeff45 = coeff_orig[2];
coeff67 = coeff_orig[3];
coeff8 = coeff_orig[4] & 0xffff;
scale = (coeff_orig[4] >> 16) & 0x0f;
offset[0] = 0; /* coeff_orig[5]; */
offset[1] = 0; /* coeff_orig[6]; */
offset[2] = 0; /* coeff_orig[7]; */
if (scale >= bits) {
shift = scale - bits;
coeff[5] = (coeff01 & 0xffff) >> shift;
coeff[3] = ((coeff01 >> 16) & 0xffff) >> shift;
coeff[4] = (coeff23 & 0xffff) >> shift;
coeff[8] = ((coeff23 >> 16) & 0xffff) >> shift;
coeff[6] = (coeff45 & 0xffff) >> shift;
coeff[7] = ((coeff45 >> 16) & 0xffff) >> shift;
coeff[11] = (coeff67 & 0xffff) >> shift;
coeff[9] = ((coeff67 >> 16) & 0xffff) >> shift;
coeff[10] = (coeff8 & 0xffff) >> shift;
} else {
shift = bits - scale;
coeff[5] = (coeff01 & 0xffff) << shift;
coeff[3] = ((coeff01 >> 16) & 0xffff) << shift;
coeff[4] = (coeff23 & 0xffff) << shift;
coeff[8] = ((coeff23 >> 16) & 0xffff) << shift;
coeff[6] = (coeff45 & 0xffff) << shift;
coeff[7] = ((coeff45 >> 16) & 0xffff) << shift;
coeff[11] = (coeff67 & 0xffff) << shift;
coeff[9] = ((coeff67 >> 16) & 0xffff) << shift;
coeff[10] = (coeff8 & 0xffff) << shift;
}
coeff[18] = offset[0] >> (12 - bits);
coeff[19] = offset[1] >> (12 - bits);
coeff[20] = offset[2] >> (12 - bits);
for (i = 3; i < 12; i++) {
if (coeff[i] & (1 << bits))
for (j = bits + 1; j <= 12; j++)
coeff[i] |= 1 << j;
}
coeff[22] = bits - 10;
set_vpp_matrix(VPP_MATRIX_POST,
coeff, CSC_ON);
vpp_set_mtx_en_write();
restore_post_table = true;
} else if (restore_post_table) {
set_vpp_matrix(VPP_MATRIX_POST,
post_mtx_backup, post_on_backup);
vpp_set_mtx_en_write();
restore_post_table = false;
}
return 0;
}
EXPORT_SYMBOL(enable_rgb_to_yuv_matrix_for_dvll);
static void vpp_set_matrix(
enum vpp_matrix_sel_e vd1_or_vd2_or_post,
unsigned int on,

2086
drivers/amlogic/media/enhancement/amvecm/amdolby_vision.c
View File

File diff suppressed because it is too large Load Diff

77
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

@@ -55,6 +55,7 @@
#include "amcsc.h"
#include "keystone_correction.h"
#include "bitdepth.h"
#include <linux/amlogic/media/amdolbyvision/dolby_vision.h>
#define pr_amvecm_dbg(fmt, args...)\
do {\
@@ -3178,8 +3179,8 @@ static void amvecm_pq_enable(int enable)
{
if (enable) {
vecm_latch_flag |= FLAG_VE_DNLP_EN;
amcm_enable();
if (!is_dolby_vision_enable())
amcm_enable();
WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1);
WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1);
@@ -3452,14 +3453,9 @@ static const char *amvecm_debug_usage_str = {
"echo vpp_mtx vd1_12 rgb2yuv > /sys/class/amvecm/debug; 12bit vd1 mtx\n"
"echo vpp_mtx vd1_12 yuv2rgb > /sys/class/amvecm/debug; 12bit vd1 mtx\n"
"echo bitdepth 10/12/other-num > /sys/class/amvecm/debug; config data path\n"
"echo dolby_config 0/1/2.. > /sys/class/amvecm/debug; dolby dma table config\n"
"echo dolby_crc 0/1 > /sys/class/amvecm/debug; dolby_crc insert or clr\n"
"echo datapath_config param1(D) param2(D) > /sys/class/amvecm/debug; config data path\n"
"echo datapath_status > /sys/class/amvecm/debug; data path status\n"
"echo dolby_dma index(D) value(H) > /sys/class/amvecm/debug; dolby dma table modify\n"
"echo clip_config 0/1/2/.. 0/1/... 0/1 > /sys/class/amvecm/debug; config clip\n"
"echo dv_efuse > /sys/class/amvecm/debug; get dv efuse info\n"
"echo dv_el > /sys/class/amvecm/debug; get dv enhanced layer info\n"
};
static ssize_t amvecm_debug_show(struct class *cla,
struct class_attribute *attr, char *buf)
@@ -3749,63 +3745,6 @@ static ssize_t amvecm_debug_store(struct class *cla,
return count;
}
/* supported mode: IPT_TUNNEL/HDR10/SDR10 */
static const int dv_mode_table[6] = {
5, /*DOLBY_VISION_OUTPUT_MODE_BYPASS*/
0, /*DOLBY_VISION_OUTPUT_MODE_IPT*/
1, /*DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL*/
2, /*DOLBY_VISION_OUTPUT_MODE_HDR10*/
3, /*DOLBY_VISION_OUTPUT_MODE_SDR10*/
4, /*DOLBY_VISION_OUTPUT_MODE_SDR8*/
};
static const char dv_mode_str[6][12] = {
"IPT",
"IPT_TUNNEL",
"HDR10",
"SDR10",
"SDR8",
"BYPASS"
};
static ssize_t amvecm_dv_mode_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
pr_info("usage: echo mode > /sys/class/amvecm/dv_mode\n");
pr_info("\tDOLBY_VISION_OUTPUT_MODE_BYPASS 0\n");
pr_info("\tDOLBY_VISION_OUTPUT_MODE_IPT 1\n");
pr_info("\tDOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL 2\n");
pr_info("\tDOLBY_VISION_OUTPUT_MODE_HDR10 3\n");
pr_info("\tDOLBY_VISION_OUTPUT_MODE_SDR10 4\n");
pr_info("\tDOLBY_VISION_OUTPUT_MODE_SDR8 5\n");
if (is_dolby_vision_enable())
pr_info("current dv_mode = %s\n",
dv_mode_str[get_dolby_vision_mode()]);
else
pr_info("current dv_mode = off\n");
return 0;
}
static ssize_t amvecm_dv_mode_store(struct class *cla,
struct class_attribute *attr,
const char *buf, size_t count)
{
size_t r;
int val;
r = sscanf(buf, "%x\n", &val);
if ((r != 1))
return -EINVAL;
if ((val >= 0) && (val < 6))
set_dolby_vision_mode(dv_mode_table[val]);
else if (val & 0x200)
dolby_vision_dump_struct();
else if (val & 0x70)
dolby_vision_dump_setting(val);
return count;
}
static const char *amvecm_reg_usage_str = {
"Usage:\n"
"echo rv addr(H) > /sys/class/amvecm/reg;\n"
@@ -4086,8 +4025,6 @@ static struct class_attribute amvecm_class_attrs[] = {
set_hdr_289lut_show, set_hdr_289lut_store),
__ATTR(vpp_demo, 0644,
amvecm_vpp_demo_show, amvecm_vpp_demo_store),
__ATTR(dv_mode, 0644,
amvecm_dv_mode_show, amvecm_dv_mode_store),
__ATTR(reg, 0644,
amvecm_reg_show, amvecm_reg_store),
__ATTR(pq_user_set, 0644,
@@ -4160,8 +4097,10 @@ static void aml_vecm_dt_parse(struct platform_device *pdev)
amvecm_gamma_init(gamma_en);
if (!is_dolby_vision_enable())
WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1);
if (cm_en)
amcm_enable();
if (cm_en) {
if (!is_dolby_vision_enable())
amcm_enable();
}
else
amcm_disable();
/* WRITE_VPP_REG_BITS(VPP_MISC, cm_en, 28, 1); */
@@ -4274,8 +4213,6 @@ static int aml_vecm_probe(struct platform_device *pdev)
else
vlock_en = 0;
aml_vecm_dt_parse(pdev);
if (is_meson_gxm_cpu())
dolby_vision_init_receiver();
probe_ok = 1;
pr_info("%s: ok\n", __func__);
return 0;

21
drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h
View File

@@ -60,15 +60,34 @@
#define DOLBY_CORE3_SWAP_CTRL4 0x36f5
#define DOLBY_CORE3_SWAP_CTRL5 0x36f6
#define DOLBY_CORE3_SWAP_CTRL6 0x36f7
#define DOLBY_CORE3_DIAG_CTRL 0x36f8
#define DOLBY_CORE3_CRC_CTRL 0x36fb
#define DOLBY_CORE3_INPUT_CSC_CRC 0x36fc
#define DOLBY_CORE3_OUTPUT_CSC_CRC 0x36fd
#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d
#define DOLBY_PATH_CTRL 0x1a0c
#define VIU_MISC_CTRL1 0x1a07
#define VPP_DOLBY_CTRL 0x1d93
#define VIU_SW_RESET 0x1a01
#define VPU_HDMI_FMT_CTRL 0x2743
#define DOLBY_TV_REG_START 0x3300
#define DOLBY_TV_CLKGATE_CTRL 0x33f1
#define DOLBY_TV_SWAP_CTRL0 0x33f2
#define DOLBY_TV_SWAP_CTRL1 0x33f3
#define DOLBY_TV_SWAP_CTRL2 0x33f4
#define DOLBY_TV_SWAP_CTRL3 0x33f5
#define DOLBY_TV_SWAP_CTRL4 0x33f6
#define DOLBY_TV_SWAP_CTRL5 0x33f7
#define DOLBY_TV_SWAP_CTRL6 0x33f8
#define DOLBY_TV_SWAP_CTRL7 0x33f9
#define DOLBY_TV_AXI2DMA_CTRL0 0x33fa
#define DOLBY_TV_AXI2DMA_CTRL1 0x33fb
#define DOLBY_TV_AXI2DMA_CTRL2 0x33fc
#define DOLBY_TV_AXI2DMA_CTRL3 0x33fd
#define DOLBY_TV_STATUS0 0x33fe
#define DOLBY_TV_STATUS1 0x33ff
#if 0
/* core 1 display manager 24 registers */
struct dm_register_ipcore_1_s {

302
drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h
View File

@@ -1,302 +0,0 @@
/*
* drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _DV_H_
#define _DV_H_
#include <linux/types.h>
#define DEF_G2L_LUT_SIZE_2P 8
#define DEF_G2L_LUT_SIZE (1 << DEF_G2L_LUT_SIZE_2P)
enum signal_format_e {
FORMAT_DOVI = 0,
FORMAT_HDR10 = 1,
FORMAT_SDR = 2
};
enum priority_mode_e {
VIDEO_PRIORITY = 0,
GRAPHIC_PRIORITY = 1
};
enum cp_signal_range_e {
SIG_RANGE_SMPTE = 0, /* head range */
SIG_RANGE_FULL = 1, /* full range */
SIG_RANGE_SDI = 2 /* PQ */
};
struct composer_register_ipcore_s {
uint32_t Composer_Mode;
uint32_t VDR_Resolution;
uint32_t Bit_Depth;
uint32_t Coefficient_Log2_Denominator;
uint32_t BL_Num_Pivots_Y;
uint32_t BL_Pivot[5];
uint32_t BL_Order;
uint32_t BL_Coefficient_Y[8][3];
uint32_t EL_NLQ_Offset_Y;
uint32_t EL_Coefficient_Y[3];
uint32_t Mapping_IDC_U;
uint32_t BL_Num_Pivots_U;
uint32_t BL_Pivot_U[3];
uint32_t BL_Order_U;
uint32_t BL_Coefficient_U[4][3];
uint32_t MMR_Coefficient_U[22][2];
uint32_t MMR_Order_U;
uint32_t EL_NLQ_Offset_U;
uint32_t EL_Coefficient_U[3];
uint32_t Mapping_IDC_V;
uint32_t BL_Num_Pivots_V;
uint32_t BL_Pivot_V[3];
uint32_t BL_Order_V;
uint32_t BL_Coefficient_V[4][3];
uint32_t MMR_Coefficient_V[22][2];
uint32_t MMR_Order_V;
uint32_t EL_NLQ_Offset_V;
uint32_t EL_Coefficient_V[3];
};
/** @brief DM registers for IPCORE 1 */
struct dm_register_ipcore_1_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Frame_Format_1;
uint32_t Frame_Format_2;
uint32_t Frame_Pixel_Def;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t Active_area_left_top;
uint32_t Active_area_bottom_right;
};
/** @brief DM registers for IPCORE 2 */
struct dm_register_ipcore_2_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t Frame_Format;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t VDR_Resolution;
};
/** @brief DM registers for IPCORE 3 */
struct dm_register_ipcore_3_s {
uint32_t D2C_coefficient_1;
uint32_t D2C_coefficient_2;
uint32_t D2C_coefficient_3;
uint32_t D2C_coefficient_4;
uint32_t D2C_coefficient_5;
uint32_t B2A_Coefficient_1;
uint32_t B2A_Coefficient_2;
uint32_t B2A_Coefficient_3;
uint32_t B2A_Coefficient_4;
uint32_t B2A_Coefficient_5;
uint32_t Eotf_param_1;
uint32_t Eotf_param_2;
uint32_t IPT_Scale;
uint32_t IPT_Offset_1;
uint32_t IPT_Offset_2;
uint32_t IPT_Offset_3;
uint32_t Output_range_1;
uint32_t Output_range_2;
uint32_t RGB2YUV_coefficient_register1;
uint32_t RGB2YUV_coefficient_register2;
uint32_t RGB2YUV_coefficient_register3;
uint32_t RGB2YUV_coefficient_register4;
uint32_t RGB2YUV_coefficient_register5;
uint32_t RGB2YUV_offset_0;
uint32_t RGB2YUV_offset_1;
uint32_t RGB2YUV_offset_2;
};
/** @brief DM luts for IPCORE 1 and 2 */
struct dm_lut_ipcore_s {
uint32_t TmLutI[64*4];
uint32_t TmLutS[64*4];
uint32_t SmLutI[64*4];
uint32_t SmLutS[64*4];
uint32_t G2L[DEF_G2L_LUT_SIZE];
};
/** @brief hdmi metadata for IPCORE 3 */
struct md_reister_ipcore_3_s {
uint32_t raw_metadata[128];
uint32_t size;
};
struct hdr_10_infoframe_s {
uint8_t infoframe_type_code;
uint8_t infoframe_version_number;
uint8_t length_of_info_frame;
uint8_t data_byte_1;
uint8_t data_byte_2;
uint8_t display_primaries_x_0_LSB;
uint8_t display_primaries_x_0_MSB;
uint8_t display_primaries_y_0_LSB;
uint8_t display_primaries_y_0_MSB;
uint8_t display_primaries_x_1_LSB;
uint8_t display_primaries_x_1_MSB;
uint8_t display_primaries_y_1_LSB;
uint8_t display_primaries_y_1_MSB;
uint8_t display_primaries_x_2_LSB;
uint8_t display_primaries_x_2_MSB;
uint8_t display_primaries_y_2_LSB;
uint8_t display_primaries_y_2_MSB;
uint8_t white_point_x_LSB;
uint8_t white_point_x_MSB;
uint8_t white_point_y_LSB;
uint8_t white_point_y_MSB;
uint8_t max_display_mastering_luminance_LSB;
uint8_t max_display_mastering_luminance_MSB;
uint8_t min_display_mastering_luminance_LSB;
uint8_t min_display_mastering_luminance_MSB;
uint8_t max_content_light_level_LSB;
uint8_t max_content_light_level_MSB;
uint8_t max_frame_average_light_level_LSB;
uint8_t max_frame_average_light_level_MSB;
};
struct hdr10_param_s {
uint32_t min_display_mastering_luminance;
uint32_t max_display_mastering_luminance;
uint16_t Rx;
uint16_t Ry;
uint16_t Gx;
uint16_t Gy;
uint16_t Bx;
uint16_t By;
uint16_t Wx;
uint16_t Wy;
uint16_t max_content_light_level;
uint16_t max_pic_average_light_level;
};
struct dovi_setting_s {
struct composer_register_ipcore_s comp_reg;
struct dm_register_ipcore_1_s dm_reg1;
struct dm_register_ipcore_2_s dm_reg2;
struct dm_register_ipcore_3_s dm_reg3;
struct dm_lut_ipcore_s dm_lut1;
struct dm_lut_ipcore_s dm_lut2;
/* for dovi output */
struct md_reister_ipcore_3_s md_reg3;
/* for hdr10 output */
struct hdr_10_infoframe_s hdr_info;
/* current process */
enum signal_format_e src_format;
enum signal_format_e dst_format;
/* enhanced layer */
bool el_flag;
bool el_halfsize_flag;
/* frame width & height */
uint32_t video_width;
uint32_t video_height;
};
extern int control_path(
enum signal_format_e in_format,
enum signal_format_e out_format,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
enum priority_mode_e set_priority,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
int set_graphic_min_lum, int set_graphic_max_lum,
int set_target_min_lum, int set_target_max_lum,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct dovi_setting_s *output);
extern void *metadata_parser_init(int flag);
extern int metadata_parser_reset(int flag);
extern int metadata_parser_process(
char *src_rpu, int rpu_len,
char *dst_comp, int *comp_len,
char *dst_md, int *md_len, bool src_eos);
extern void metadata_parser_release(void);
struct dolby_vision_func_s {
void * (*metadata_parser_init)(int);
int (*metadata_parser_reset)(int flag);
int (*metadata_parser_process)(
char *src_rpu, int rpu_len,
char *dst_comp, int *comp_len,
char *dst_md, int *md_len, bool src_eos);
void (*metadata_parser_release)(void);
int (*control_path)(
enum signal_format_e in_format,
enum signal_format_e out_format,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
enum priority_mode_e set_priority,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
int set_graphic_min_lum, int set_graphic_max_lum,
int set_target_min_lum, int set_target_max_lum,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct dovi_setting_s *output);
};
extern int register_dv_functions(const struct dolby_vision_func_s *func);
extern int unregister_dv_functions(void);
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)
#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
WRITE_VPP_REG_BITS(adr, val, start, len)
#else
extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
extern u32 VSYNC_RD_MPEG_REG(u32 adr);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#endif
#endif

2
drivers/amlogic/media/osd/osd_fb.c
View File

@@ -3048,7 +3048,7 @@ static struct osd_device_data_s osd_g12a = {
.has_deband = 1,
.has_lut = 1,
.has_rdma = 1,
.has_dolby_vision = 0,
.has_dolby_vision = 1,
.osd_fifo_len = 64, /* fifo len 64*8 = 512 */
.vpp_fifo_len = 0xfff,/* 2048 */
.dummy_data = 0x00808000,

22
drivers/amlogic/media/osd/osd_hw.c
View File

@@ -5203,6 +5203,7 @@ static void osd_basic_update_disp_geometry(u32 index)
{
struct hw_osd_reg_s *osd_reg = &hw_osd_reg_array[index];
u32 data32;
u32 buffer_w, buffer_h;
data32 = (osd_hw.dispdata[index].x_start & 0xfff)
| (osd_hw.dispdata[index].x_end & 0xfff) << 16;
@@ -5347,6 +5348,27 @@ static void osd_basic_update_disp_geometry(u32 index)
| (osd_hw.pandata[index].y_end & 0x1fff) << 16;
VSYNCOSD_WR_MPEG_REG(osd_reg->osd_blk0_cfg_w2, data32);
}
data32 = (osd_hw.free_src_data[OSD1].x_start & 0x1fff) |
(osd_hw.free_src_data[OSD1].x_end & 0x1fff) << 16;
VSYNCOSD_WR_MPEG_REG(
hw_osd_reg_array[OSD1].osd_blk0_cfg_w1, data32);
buffer_w = ((data32 >> 16) & 0x1fff) - (data32 & 0x1fff) + 1;
data32 = ((osd_hw.free_src_data[OSD1].y_start
+ osd_hw.pandata[OSD1].y_start) & 0x1fff)
| ((osd_hw.free_src_data[OSD1].y_end
+ osd_hw.pandata[OSD1].y_start) & 0x1fff) << 16;
VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W2, data32);
buffer_h = ((data32 >> 16) & 0x1fff) - (data32 & 0x1fff) + 1;
if (osd_hw.osd_meson_dev.has_dolby_vision) {
VSYNCOSD_WR_MPEG_REG(
DOLBY_CORE2A_SWAP_CTRL1,
((buffer_w + 0x40) << 16)
| (buffer_h + 0x80 + 0));
VSYNCOSD_WR_MPEG_REG(
DOLBY_CORE2A_SWAP_CTRL2,
(buffer_w << 16) | (buffer_h + 0));
}
data32 = VSYNCOSD_RD_MPEG_REG(osd_reg->osd_ctrl_stat);
data32 &= ~0x1ff008;//0x1ff00e;
data32 |= osd_hw.gbl_alpha[index] << 12;

147
drivers/amlogic/media/video_sink/video.c
View File

@@ -85,6 +85,7 @@ MODULE_AMLOG(LOG_LEVEL_ERROR, 0, LOG_DEFAULT_LEVEL_DESC, LOG_MASK_DESC);
#include <linux/amlogic/media/codec_mm/configs.h>
#include "../common/vfm/vfm.h"
#include <linux/amlogic/media/amdolbyvision/dolby_vision.h>
static u32 osd_vpp_misc;
static u32 osd_vpp_misc_mask;
@@ -672,7 +673,6 @@ static u32 ori_end_x_lines;
static u32 ori_start_y_lines;
static u32 ori_end_y_lines;
#if DEBUG_TMP
static u32 zoom2_start_x_lines;
static u32 zoom2_end_x_lines;
static u32 zoom2_start_y_lines;
@@ -682,7 +682,6 @@ static u32 ori2_start_x_lines;
static u32 ori2_end_x_lines;
static u32 ori2_start_y_lines;
static u32 ori2_end_y_lines;
#endif
/* wide settings */
static u32 wide_setting;
@@ -852,7 +851,7 @@ static int android_clone_rate = 30;
static int noneseamless_play_clone_rate = 5;
#endif
#define CONFIG_AM_VOUT //DEBUG_TMP
#define CONFIG_AM_VOUT
void safe_disble_videolayer(void)
{
@@ -970,10 +969,8 @@ static inline void video_vf_put(struct vframe_s *vf)
if (vfp && vf && atomic_dec_and_test(&vf->use_cnt)) {
vf_put(vf, RECEIVER_NAME);
#if DEBUG_TMP
if (is_dolby_vision_enable())
dolby_vision_vf_put(vf);
#endif
video_notify_flag |= VIDEO_NOTIFY_PROVIDER_PUT;
}
}
@@ -1174,7 +1171,6 @@ static void vpp_settings_h(struct vpp_frame_par_s *framePtr)
framePtr->VPP_line_in_length_);
}
#if DEBUG_TMP
static void vd2_settings_h(struct vframe_s *vf)
{
u32 VPP_hd_start_lines_;
@@ -1192,7 +1188,6 @@ static void vd2_settings_h(struct vframe_s *vf)
VPP_VD_SIZE_MASK) << VPP_VD1_END_BIT));
}
}
#endif
static void vpp_settings_v(struct vpp_frame_par_s *framePtr)
{
@@ -1362,7 +1357,6 @@ static void vpp_settings_v(struct vpp_frame_par_s *framePtr)
vpp_filter->vpp_vsc_start_phase_step);
}
#if DEBUG_TMP
static void vd2_settings_v(struct vframe_s *vf)
{
u32 VPP_vd_start_lines_;
@@ -1381,7 +1375,6 @@ static void vd2_settings_v(struct vframe_s *vf)
VPP_VD_SIZE_MASK) << VPP_VD1_END_BIT));
}
}
#endif
#ifdef TV_3D_FUNCTION_OPEN
@@ -1668,7 +1661,6 @@ static void zoom_display_horz(int hscale)
1) >> hscale) << VD1_FMT_CHROMA_WIDTH_BIT));
}
#if DEBUG_TMP
static void vd2_zoom_display_horz(int hscale)
{
u32 ls, le, rs, re;
@@ -1751,7 +1743,6 @@ static void vd2_zoom_display_horz(int hscale)
(((le / 2 - ls / 2 + 1) >> hscale)
<< VD1_FMT_CHROMA_WIDTH_BIT));
}
#endif
static void zoom_display_vert(void)
{
@@ -1904,7 +1895,6 @@ static void zoom_display_vert(void)
}
}
#if DEBUG_TMP
static void vd2_zoom_display_vert(void)
{
@@ -1970,7 +1960,6 @@ static void vd2_zoom_display_vert(void)
}
}
}
#endif
#ifdef TV_3D_FUNCTION_OPEN
/* judge the out mode is 240:LBRBLRBR or 120:LRLRLR */
@@ -2037,10 +2026,9 @@ bool has_enhanced_layer(struct vframe_s *vf)
return 0;
if (vf->source_type != VFRAME_SOURCE_TYPE_OTHERS)
return 0;
#if DEBUG_TMP
if (!is_dolby_vision_on())
return 0;
#endif
req.vf = vf;
req.bot_flag = 0;
req.aux_buf = NULL;
@@ -2062,10 +2050,8 @@ static void vsync_toggle_frame(struct vframe_s *vf)
return;
frame_count++;
toggle_count++;
#if DEBUG_TMP
if (is_dolby_vision_enable())
vf_with_el = has_enhanced_layer(vf);
#endif
ori_start_x_lines = 0;
ori_end_x_lines = ((vf->type & VIDTYPE_COMPRESS) ?
vf->compWidth : vf->width) - 1;
@@ -2608,8 +2594,8 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
#ifdef TV_REVERSE
if (reverse) {
if (is_meson_txlx_package_962X()
/*&& !is_dolby_vision_stb_mode()*/
/*&& is_dolby_vision_on()*/)/*DEBUG_TMP*/
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on())
VSYNC_WR_MPEG_REG(
AFBC_VD_CFMT_CTRL,
HFORMATTER_REPEAT |
@@ -2632,8 +2618,8 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
#endif
{
if (is_meson_txlx_package_962X()
/*&& !is_dolby_vision_stb_mode()*/
/*&& is_dolby_vision_on()*/)/*DEBUG_TMP*/
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on())
VSYNC_WR_MPEG_REG(
AFBC_VD_CFMT_CTRL,
HFORMATTER_REPEAT |
@@ -2724,10 +2710,8 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
VDIF_DEMUX_MODE_RGB_444;
}
}
#if DEBUG_TMP
if (is_dolby_vision_enable())
vf_with_el = has_enhanced_layer(vf);
#endif
if (frame_par->hscale_skip_count)
r |= VDIF_CHROMA_HZ_AVG | VDIF_LUMA_HZ_AVG;
@@ -2800,8 +2784,8 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
else
vformatter = 0;
if (is_meson_txlx_package_962X()
/*&& !is_dolby_vision_stb_mode()*/
/*&& is_dolby_vision_on()*/) {/*DEBUG_TMP*/
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VIU_VD1_FMT_CTRL + cur_dev->viu_off,
HFORMATTER_REPEAT |
@@ -2837,7 +2821,7 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
} else {
VSYNC_WR_MPEG_REG(
VIU_VD1_FMT_CTRL + cur_dev->viu_off,
(/*is_dolby_vision_on()*/0 ?/*DEBUG_TMP*/
(is_dolby_vision_on() ?
HFORMATTER_REPEAT : 0) |
HFORMATTER_YC_RATIO_2_1 | HFORMATTER_EN |
VFORMATTER_RPTLINE0_EN | vini_phase | vphase |
@@ -2854,7 +2838,7 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
} else {
VSYNC_WR_MPEG_REG(
VIU_VD1_FMT_CTRL + cur_dev->viu_off,
(/*is_dolby_vision_on()*/0 ?/*DEBUG_TMP*/
(is_dolby_vision_on() ?
HFORMATTER_REPEAT : 0) |
HFORMATTER_YC_RATIO_2_1 | HFORMATTER_EN |
VFORMATTER_RPTLINE0_EN |
@@ -2902,8 +2886,8 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
<< VFORMATTER_PHASE_BIT) | VFORMATTER_EN);
} else {
if (is_meson_txlx_package_962X()
/*&& !is_dolby_vision_stb_mode()*/
/*&& is_dolby_vision_on()*/) {/*DEBUG_TMP*/
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VIU_VD1_FMT_CTRL + cur_dev->viu_off,
HFORMATTER_REPEAT |
@@ -2917,7 +2901,7 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
} else {
VSYNC_WR_MPEG_REG(
VIU_VD1_FMT_CTRL + cur_dev->viu_off,
(/*is_dolby_vision_on()*/0 ?/*DEBUG_TMP*/
(is_dolby_vision_on() ?
HFORMATTER_REPEAT : 0) |
HFORMATTER_YC_RATIO_2_1 |
HFORMATTER_EN |
@@ -3145,8 +3129,8 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
#ifdef TV_REVERSE
if (reverse) {
if (is_meson_txlx_package_962X()
/*&& !is_dolby_vision_stb_mode()*/
/*&& is_dolby_vision_on()*/) {/*DEBUG_TMP*/
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VD2_AFBC_VD_CFMT_CTRL,
HFORMATTER_REPEAT |
@@ -3171,8 +3155,8 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
} else {
#endif
if (is_meson_txlx_package_962X()
/*&& !is_dolby_vision_stb_mode()*/
/*&& is_dolby_vision_on()*/) {/*DEBUG_TMP*/
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VD2_AFBC_VD_CFMT_CTRL,
HFORMATTER_REPEAT |
@@ -3284,8 +3268,8 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
((type & VIDTYPE_VIU_422) ? 0x10 : 0x08) <<
VFORMATTER_PHASE_BIT;
if (is_meson_txlx_package_962X()
/*&& !is_dolby_vision_stb_mode()*/
/*&& is_dolby_vision_on()*/) {/*DEBUG_TMP*/
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VIU_VD2_FMT_CTRL + cur_dev->viu_off,
HFORMATTER_REPEAT |
@@ -3311,7 +3295,7 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
} else {
VSYNC_WR_MPEG_REG(
VIU_VD2_FMT_CTRL + cur_dev->viu_off,
(/*is_dolby_vision_on()*/0 ?/*DEBUG_TMP*/
(is_dolby_vision_on() ?
HFORMATTER_REPEAT : 0) |
HFORMATTER_YC_RATIO_2_1 | HFORMATTER_EN |
VFORMATTER_RPTLINE0_EN |
@@ -3321,7 +3305,7 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
} else {
VSYNC_WR_MPEG_REG(
VIU_VD2_FMT_CTRL + cur_dev->viu_off,
(/*is_dolby_vision_on()*/0 ?/*DEBUG_TMP*/
(is_dolby_vision_on() ?
HFORMATTER_REPEAT : 0) |
HFORMATTER_YC_RATIO_2_1 | HFORMATTER_EN |
VFORMATTER_RPTLINE0_EN | vini_phase | vphase |
@@ -3354,8 +3338,8 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
VFORMATTER_EN);
} else {
if (is_meson_txlx_package_962X()
/*&& !is_dolby_vision_stb_mode()*/
/*&& is_dolby_vision_on()*/) {/*DEBUG_TMP*/
&& !is_dolby_vision_stb_mode()
&& is_dolby_vision_on()) {
VSYNC_WR_MPEG_REG(
VIU_VD2_FMT_CTRL + cur_dev->viu_off,
HFORMATTER_REPEAT |
@@ -3370,7 +3354,7 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
} else {
VSYNC_WR_MPEG_REG(
VIU_VD2_FMT_CTRL + cur_dev->viu_off,
(/*is_dolby_vision_on()*/0 ?/*DEBUG_TMP*/
(is_dolby_vision_on() ?
HFORMATTER_REPEAT : 0) |
HFORMATTER_YC_RATIO_2_1 |
HFORMATTER_EN |
@@ -3379,7 +3363,7 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
(((type & VIDTYPE_VIU_422) ? 0x10 : 0x08)
<< VFORMATTER_PHASE_BIT) | VFORMATTER_EN);
pr_info("\tvd2 set fmt(dovi:%d)\n",
/*is_dolby_vision_on()*/0);/*DEBUG_TMP*/
/*is_dolby_vision_on()*/0);
}
}
/* LOOP/SKIP pattern */
@@ -3900,11 +3884,11 @@ static enum vmode_e new_vmode = VMODE_MAX;
static inline bool video_vf_disp_mode_check(struct vframe_s *vf)
{
struct provider_disp_mode_req_s req;
//int ret = -1;
int ret = -1;
req.vf = vf;
req.disp_mode = 0;
req.req_mode = 1;
#if DEBUG_TMP
if (is_dolby_vision_enable()) {
ret = vf_notify_provider_by_name("dv_vdin",
VFRAME_EVENT_RECEIVER_DISP_MODE, (void *)&req);
@@ -3912,7 +3896,6 @@ static inline bool video_vf_disp_mode_check(struct vframe_s *vf)
vf_notify_provider_by_name("vdin0",
VFRAME_EVENT_RECEIVER_DISP_MODE, (void *)&req);
} else
#endif
vf_notify_provider_by_name("vdin0",
VFRAME_EVENT_RECEIVER_DISP_MODE, (void *)&req);
if (req.disp_mode == VFRAME_DISP_MODE_OK)
@@ -3924,11 +3907,11 @@ static inline bool video_vf_disp_mode_check(struct vframe_s *vf)
static enum vframe_disp_mode_e video_vf_disp_mode_get(struct vframe_s *vf)
{
struct provider_disp_mode_req_s req;
//int ret = -1;
int ret = -1;
req.vf = vf;
req.disp_mode = 0;
req.req_mode = 0;
#if DEBUG_TMP
if (is_dolby_vision_enable()) {
ret = vf_notify_provider_by_name("dv_vdin",
VFRAME_EVENT_RECEIVER_DISP_MODE, (void *)&req);
@@ -3936,7 +3919,6 @@ static enum vframe_disp_mode_e video_vf_disp_mode_get(struct vframe_s *vf)
vf_notify_provider_by_name("vdin0",
VFRAME_EVENT_RECEIVER_DISP_MODE, (void *)&req);
} else
#endif
vf_notify_provider_by_name("vdin0",
VFRAME_EVENT_RECEIVER_DISP_MODE, (void *)&req);
return req.disp_mode;
@@ -3977,7 +3959,6 @@ static inline bool video_vf_dirty_put(struct vframe_s *vf)
}
#if DEBUG_TMP
struct vframe_s *dolby_vision_toggle_frame(struct vframe_s *vf)
{
struct vframe_s *toggle_vf = NULL;
@@ -4050,9 +4031,7 @@ struct vframe_s *dolby_vision_toggle_frame(struct vframe_s *vf)
}
return toggle_vf;
}
#endif
#if DEBUG_TMP
static int dolby_vision_need_wait(void)
{
struct vframe_s *vf;
@@ -4062,7 +4041,6 @@ static int dolby_vision_need_wait(void)
return 1;
return 0;
}
#endif
/* patch for 4k2k bandwidth issue, skiw mali and vpu mif */
static void dmc_adjust_for_mali_vpu(unsigned int width, unsigned int height)
@@ -4075,8 +4053,9 @@ static void dmc_adjust_for_mali_vpu(unsigned int width, unsigned int height)
}
/*avoid 3840x2160 crop*/
if ((width >= 2000) && (height >= 1400) &&
(dmc_config_state != 1) && (toggle_same_count < 30)) {
if (0) {/* if (is_dolby_vision_enable()) { */
(dmc_config_state != 1) &&
(toggle_same_count < 30)) {
if (is_dolby_vision_enable()) {
/* vpu dmc */
WRITE_DMCREG(
DMC_AM0_CHAN_CTRL,
@@ -4200,7 +4179,6 @@ void correct_vd1_mif_size_for_DV(struct vpp_frame_par_s *par)
}
}
#if DEBUG_TMP
void correct_vd2_mif_size_for_DV(
struct vpp_frame_par_s *par,
struct vframe_s *bl_vf)
@@ -4244,7 +4222,6 @@ void correct_vd2_mif_size_for_DV(
/* TODO: if el len is 0, need disable bl */
}
}
#endif
#ifdef FIQ_VSYNC
void vsync_fisr_in(void)
@@ -4268,9 +4245,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
#ifdef CONFIG_AM_VIDEO_LOG
int toggle_cnt;
#endif
#if DEBUG_TMP
struct vframe_s *toggle_vf = NULL;
#endif
struct vframe_s *toggle_frame = NULL;
int video1_off_req = 0;
struct vframe_s *cur_dispbuf_back = cur_dispbuf;
@@ -4398,11 +4373,9 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
enable_rdma_log_count--;
}
#endif
#if DEBUG_TMP
/* check video frame before VECM process */
if (is_dolby_vision_enable() && vf)
dolby_vision_check_hdr10(vf);
#endif
#ifdef CONFIG_TVIN_VDIN
/* patch for m8 4k2k wifidisplay bandwidth bottleneck */
@@ -4631,11 +4604,9 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
0) == 1)
break;
#endif
#if DEBUG_TMP
if (is_dolby_vision_enable()
&& dolby_vision_need_wait())
break;
#endif
/*
*two special case:
*case1:4k display case,input buffer not enough &
@@ -4675,8 +4646,8 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
}
vsync_toggle_frame(vf);
toggle_frame = vf;
if (0/*is_dolby_vision_enable()*/) { /*DEBUG_TMP*/
//toggle_vf = dolby_vision_toggle_frame(vf);
if (is_dolby_vision_enable()) {
toggle_vf = dolby_vision_toggle_frame(vf);
video_pause_global = 0;
} else {
cur_dispbuf2 = NULL;
@@ -4705,11 +4676,9 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
vf = video_vf_peek();
if (!vf)
next_peek_underflow++;
#if DEBUG_TMP
if (for_dolby_vision_certification()
&& toggle_vf)
break;
#endif
if (debug_flag & DEBUG_FLAG_TOGGLE_FRAME_PER_VSYNC)
break;
video_get_vf_cnt++;
@@ -4738,11 +4707,9 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
"sys.time = 0x%x, video time = 0x%x\n",
timestamp_pcrscr_get(),
timestamp_vpts_get());
#if DEBUG_TMP
if (is_dolby_vision_enable()
&& dolby_vision_need_wait())
break;
#endif
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
refresh_on_vs(vf);
if (amvecm_on_vs(
@@ -4762,12 +4729,10 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
break;
vsync_toggle_frame(vf);
toggle_frame = vf;
#if DEBUG_TMP
if (is_dolby_vision_enable())
toggle_vf =
dolby_vision_toggle_frame(vf);
else
#endif
cur_dispbuf2 = NULL;
frame_repeat_count = 0;
@@ -4796,8 +4761,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
cur_dispbuf);
} else
vsync_toggle_frame(cur_dispbuf);
/*DEBUG_TMP*/
if (0/*is_dolby_vision_enable()*/) {
if (is_dolby_vision_enable()) {
pause_vf = cur_dispbuf;
video_pause_global = 1;
} else {
@@ -4805,14 +4769,13 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
video_pause_global = 2;
}
}
#if DEBUG_TMP
if (pause_vf && (video_pause_global == 1)
&& is_dolby_vision_enable()) {
toggle_vf = pause_vf;
dolby_vision_parse_metadata(cur_dispbuf, true);
dolby_vision_parse_metadata(
cur_dispbuf, 0, false);
dolby_vision_set_toggle_flag(1);
}
#endif
break;
}
@@ -4853,10 +4816,27 @@ SET_FILTER:
frame_par_di_set = 1;
}
#if DEBUG_TMP
if (is_dolby_vision_enable()) {
u32 frame_size = 0, h_size, v_size;
/* force toggle when keeping frame after playing */
if ((cur_dispbuf == &vf_local)
&& !toggle_vf
&& is_dolby_vision_on()) {
toggle_vf = cur_dispbuf;
dolby_vision_parse_metadata(
cur_dispbuf, 2, false);
dolby_vision_set_toggle_flag(1);
}
/* force toggle in pause mode */
if (cur_dispbuf
&& (cur_dispbuf != &vf_local)
&& !toggle_vf
&& is_dolby_vision_on()) {
toggle_vf = cur_dispbuf;
dolby_vision_parse_metadata(
cur_dispbuf, 0, false);
dolby_vision_set_toggle_flag(1);
}
if (cur_frame_par) {
if (cur_frame_par->VPP_hd_start_lines_
>= cur_frame_par->VPP_hd_end_lines_)
@@ -4883,7 +4863,6 @@ SET_FILTER:
dolby_vision_process(toggle_vf, frame_size);
dolby_vision_update_setting();
}
#endif
if ((platform_type == 1) || (platform_type == 0)) {
if (mode_3d_changed) {
mode_3d_changed = 0;
@@ -5139,7 +5118,6 @@ SET_FILTER:
zoom_start_y_lines = zoom_start_y;
zoom_end_y_lines = zoom_end_y;
zoom_display_vert();
#if DEBUG_TMP
if (is_dolby_vision_enable() && cur_dispbuf2) {
zoom2_start_x_lines = ori2_start_x_lines;
zoom2_end_x_lines = ori2_end_x_lines;
@@ -5150,7 +5128,6 @@ SET_FILTER:
vd2_zoom_display_horz(0);
vd2_zoom_display_vert();
}
#endif
}
/*vpp input size setting*/
VSYNC_WR_MPEG_REG(VPP_IN_H_V_SIZE,
@@ -5176,7 +5153,7 @@ SET_FILTER:
/* vpp filters */
/* SET_MPEG_REG_MASK(VPP_SC_MISC + cur_dev->vpp_off, */
/* VPP_SC_TOP_EN | VPP_SC_VERT_EN | VPP_SC_HORZ_EN); */
if (/*for_dolby_vision_certification()*/0) {/*DEBUG_TMP*/
if (for_dolby_vision_certification()) {
/* turn off PPS for Dolby Vision certification */
VSYNC_WR_MPEG_REG_BITS(VPP_SC_MISC + cur_dev->vpp_off,
0, VPP_SC_TOP_EN_BIT, VPP_SC_TOP_EN_WID);
@@ -5340,12 +5317,10 @@ SET_FILTER:
vpp_settings_h(cur_frame_par);
vpp_settings_v(cur_frame_par);
#if DEBUG_TMP
if (is_dolby_vision_enable() && cur_dispbuf2) {
vd2_settings_h(cur_dispbuf2);
vd2_settings_v(cur_dispbuf2);
}
#endif
frame_par_ready_to_set = 0;
frame_par_force_to_set = 0;
first_set = 1;
@@ -5819,7 +5794,7 @@ static void video_vf_unreg_provider(void)
cur_dispbuf = &vf_local;
cur_dispbuf->video_angle = 0;
}
if (0/*is_dolby_vision_enable()*/) {/*DEBUG_TMP*/
if (is_dolby_vision_enable()) {
if (cur_dispbuf2 == &vf_local2)
cur_dispbuf2 = NULL;
else if (cur_dispbuf2 != NULL) {
@@ -7505,7 +7480,7 @@ static ssize_t video_test_screen_store(struct class *cla,
data &= (~VPP_VD1_POSTBLEND);
#endif
#if 0 //DEBUG_TMP
#if DEBUG_TMP
if (test_screen & 0x04000000)
data |= VPP_VD2_PREBLEND;
else
@@ -7557,7 +7532,7 @@ static ssize_t video_rgb_screen_store(struct class *cla,
if (r < 0)
return -EINVAL;
#if 0 //DEBUG_TMP
#if DEBUG_TMP
/* vdin0 pre post blend enable or disabled */
data = READ_VCBUS_REG(VPP_MISC);

192
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
View File

@@ -767,81 +767,147 @@ static void Edid_ParsingVendSpec(struct rx_cap *pRXCap,
{
struct dv_info *dv = &pRXCap->dv_info;
unsigned char *dat = buf;
unsigned char len;
unsigned char pos = 0;
len = dat[pos] & 0x1f;
memset(dv, 0, sizeof(struct dv_info));
dv->block_flag = CORRECT;
dv->length = dat[pos] & 0x1f;
memcpy(dv->rawdata, dat, dv->length + 1);
pos++;
if (dat[pos] != 1) {
pr_info(EDID "parsing fail %s[%d]\n", __func__,
pr_info("hdmitx: edid: parsing fail %s[%d]\n", __func__,
__LINE__);
} else {
pos++;
return;
}
pos++;
dv->ieeeoui = dat[pos++];
dv->ieeeoui += dat[pos++] << 8;
dv->ieeeoui += dat[pos++] << 16;
if (dv->ieeeoui != DV_IEEE_OUI) {
dv->block_flag = ERROR_LENGTH;
return;
}
dv->ver = (dat[pos] >> 5) & 0x7;
/* Refer to DV 2.6 Page 11 */
/* Refer to DV 2.9 Page 27 */
if (dv->ver == 0) {
dv->sup_yuv422_12bit = dat[pos] & 0x1;
dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
dv->sup_global_dimming = (dat[pos] >> 2) & 0x1;
pos++;
dv->vers.ver0.chrom_red_primary_x =
(dat[pos+1] << 8) | (dat[pos] >> 4);
dv->vers.ver0.chrom_red_primary_y =
(dat[pos+2] << 8) | (dat[pos] & 0xf);
pos += 3;
dv->vers.ver0.chrom_green_primary_x =
(dat[pos+1] << 8) | (dat[pos] >> 4);
dv->vers.ver0.chrom_green_primary_y =
(dat[pos+2] << 8) | (dat[pos] & 0xf);
pos += 3;
dv->vers.ver0.chrom_blue_primary_x =
(dat[pos+1] << 8) | (dat[pos] >> 4);
dv->vers.ver0.chrom_blue_primary_y =
(dat[pos+2] << 8) | (dat[pos] & 0xf);
pos += 3;
dv->vers.ver0.chrom_white_primary_x =
(dat[pos+1] << 8) | (dat[pos] >> 4);
dv->vers.ver0.chrom_white_primary_y =
(dat[pos+2] << 8) | (dat[pos] & 0xf);
pos += 3;
dv->vers.ver0.target_min_pq =
(dat[pos+1] << 8) | (dat[pos] >> 4);
dv->vers.ver0.target_max_pq =
(dat[pos+2] << 8) | (dat[pos] & 0xf);
pos += 3;
dv->vers.ver0.dm_major_ver = dat[pos] >> 4;
dv->vers.ver0.dm_minor_ver = dat[pos] & 0xf;
pos++;
}
/* Refer to DV 2.6 Page 14 */
if (dv->ver == 1) {
dv->vers.ver1.dm_version = (dat[pos] >> 2) & 0x7;
dv->sup_yuv422_12bit = dat[pos] & 0x1;
dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
pos++;
dv->sup_global_dimming = dat[pos] & 0x1;
dv->vers.ver1.target_max_lum = dat[pos] >> 1;
pos++;
dv->colorimetry = dat[pos] & 0x1;
dv->vers.ver1.target_min_lum = dat[pos] >> 1;
pos += 2; /* byte8 is reserved as 0 */
dv->vers.ver1.chrom_red_primary_x = dat[pos++];
dv->vers.ver1.chrom_red_primary_y = dat[pos++];
dv->vers.ver1.chrom_green_primary_x = dat[pos++];
dv->vers.ver1.chrom_green_primary_y = dat[pos++];
dv->vers.ver1.chrom_blue_primary_x = dat[pos++];
dv->vers.ver1.chrom_blue_primary_y = dat[pos++];
}
if (dv->length == 0x19) {
dv->sup_yuv422_12bit = dat[pos] & 0x1;
dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
dv->sup_global_dimming = (dat[pos] >> 2) & 0x1;
pos++;
dv->Rx =
(dat[pos+1] << 4) | (dat[pos] >> 4);
dv->Ry =
(dat[pos+2] << 4) | (dat[pos] & 0xf);
pos += 3;
dv->Gx =
(dat[pos+1] << 4) | (dat[pos] >> 4);
dv->Gy =
(dat[pos+2] << 4) | (dat[pos] & 0xf);
pos += 3;
dv->Bx =
(dat[pos+1] << 4) | (dat[pos] >> 4);
dv->By =
(dat[pos+2] << 4) | (dat[pos] & 0xf);
pos += 3;
dv->Wx =
(dat[pos+1] << 4) | (dat[pos] >> 4);
dv->Wy =
(dat[pos+2] << 4) | (dat[pos] & 0xf);
pos += 3;
dv->tminPQ =
(dat[pos+1] << 4) | (dat[pos] >> 4);
dv->tmaxPQ =
(dat[pos+2] << 4) | (dat[pos] & 0xf);
pos += 3;
dv->dm_major_ver = dat[pos] >> 4;
dv->dm_minor_ver = dat[pos] & 0xf;
pos++;
} else
dv->block_flag = ERROR_LENGTH;
}
if (pos > len)
if (dv->ver == 1) {
if (dv->length == 0x0B) {/* Refer to DV 2.9 Page 33 */
dv->dm_version = (dat[pos] >> 2) & 0x7;
dv->sup_yuv422_12bit = dat[pos] & 0x1;
dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
pos++;
dv->sup_global_dimming = dat[pos] & 0x1;
dv->tmaxLUM = dat[pos] >> 1;
pos++;
dv->colorimetry = dat[pos] & 0x1;
dv->tminLUM = dat[pos] >> 1;
pos++;
dv->low_latency = dat[pos] & 0x3;
dv->Bx = 0x20 | ((dat[pos] >> 5) & 0x7);
dv->By = 0x08 | ((dat[pos] >> 2) & 0x7);
pos++;
dv->Gx = 0x00 | (dat[pos] >> 1);
dv->Ry = 0x40 | ((dat[pos] & 0x1) |
((dat[pos + 1] & 0x1) << 1) |
((dat[pos + 2] & 0x3) << 2));
pos++;
dv->Gy = 0x80 | (dat[pos] >> 1);
pos++;
dv->Rx = 0xA0 | (dat[pos] >> 3);
pos++;
} else if (dv->length == 0x0E) {
dv->dm_version = (dat[pos] >> 2) & 0x7;
dv->sup_yuv422_12bit = dat[pos] & 0x1;
dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
pos++;
dv->sup_global_dimming = dat[pos] & 0x1;
dv->tmaxLUM = dat[pos] >> 1;
pos++;
dv->colorimetry = dat[pos] & 0x1;
dv->tminLUM = dat[pos] >> 1;
pos += 2; /* byte8 is reserved as 0 */
dv->Rx = dat[pos++];
dv->Ry = dat[pos++];
dv->Gx = dat[pos++];
dv->Gy = dat[pos++];
dv->Bx = dat[pos++];
dv->By = dat[pos++];
} else
dv->block_flag = ERROR_LENGTH;
}
if (dv->ver == 2) {
if (dv->length == 0x0B) {
dv->sup_2160p60hz = 0x1;/*default*/
dv->dm_version = (dat[pos] >> 2) & 0x7;
dv->sup_yuv422_12bit = dat[pos] & 0x1;
dv->sup_backlight_control = (dat[pos] >> 1) & 0x1;
pos++;
dv->sup_global_dimming = (dat[pos] >> 2) & 0x1;
dv->backlt_min_luma = dat[pos] & 0x3;
dv->tminPQ = dat[pos] >> 3;
pos++;
dv->Interface = dat[pos] & 0x3;
dv->tmaxPQ = dat[pos] >> 3;
pos++;
dv->sup_10b_12b_444 = ((dat[pos] & 0x1) << 1) |
(dat[pos + 1] & 0x1);
dv->Gx = 0x00 | (dat[pos] >> 1);
pos++;
dv->Gy = 0x80 | (dat[pos] >> 1);
pos++;
dv->Rx = 0xA0 | (dat[pos] >> 3);
dv->Bx = 0x20 | (dat[pos] & 0x7);
pos++;
dv->Ry = 0x40 | (dat[pos] >> 3);
dv->By = 0x08 | (dat[pos] & 0x7);
pos++;
} else
dv->block_flag = ERROR_LENGTH;
}
if (pos > dv->length)
pr_info("hdmitx: edid: maybe invalid dv%d data\n", dv->ver);
return;
}
/* ----------------------------------------------------------- */
@@ -2174,6 +2240,8 @@ bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
return 0;
if (pRXCap->dc_y444 && pRXCap->dc_30bit)
rx_y444_max_dc = COLORDEPTH_30B;
if (pRXCap->dc_y444 && pRXCap->dc_36bit)
rx_y444_max_dc = COLORDEPTH_36B;
if (para->cd <= rx_y444_max_dc)
valid = 1;
else
@@ -2186,6 +2254,8 @@ bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
return 0;
if (pRXCap->dc_y444 && pRXCap->dc_30bit)
rx_y422_max_dc = COLORDEPTH_30B;
if (pRXCap->dc_y444 && pRXCap->dc_36bit)
rx_y422_max_dc = COLORDEPTH_36B;
if (para->cd <= rx_y422_max_dc)
valid = 1;
else
@@ -2196,6 +2266,8 @@ bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
/* Always assume RX supports RGB444 */
if (pRXCap->dc_30bit)
rx_rgb_max_dc = COLORDEPTH_30B;
if (pRXCap->dc_36bit)
rx_rgb_max_dc = COLORDEPTH_36B;
if (para->cd <= rx_rgb_max_dc)
valid = 1;
else
@@ -2205,6 +2277,8 @@ bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
if (para->cs == COLORSPACE_YUV420) {
if (pRXCap->dc_30bit_420)
rx_y420_max_dc = COLORDEPTH_30B;
if (pRXCap->dc_36bit_420)
rx_y420_max_dc = COLORDEPTH_36B;
if (para->cd <= rx_y420_max_dc)
valid = 1;
else

377
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
View File

@@ -70,7 +70,8 @@ static struct class *hdmitx_class;
static int set_disp_mode_auto(void);
static void hdmitx_get_edid(struct hdmitx_dev *hdev);
static void hdmitx_set_drm_pkt(struct master_display_info_s *data);
static void hdmitx_set_vsif_pkt(enum eotf_type type, uint8_t tunnel_mode);
static void hdmitx_set_vsif_pkt(enum eotf_type type, enum mode_type
tunnel_mode, struct dv_vsif_para *data);
static int check_fbc_special(unsigned char *edid_dat);
static struct vinfo_s *hdmitx_get_current_vinfo(void);
@@ -1091,84 +1092,204 @@ static void hdmitx_set_drm_pkt(struct master_display_info_s *data)
CLR_AVI_BT2020);
}
static void hdmitx_set_vsif_pkt(enum eotf_type type, uint8_t tunnel_mode)
static void hdmitx_set_vsif_pkt(enum eotf_type type,
enum mode_type tunnel_mode, struct dv_vsif_para *data)
{
struct hdmitx_dev *hdev = &hdmitx_device;
struct dv_vsif_para para = {0};
unsigned char VEN_HB[3] = {0x81, 0x01};
unsigned char VEN_DB[24] = {0x00};
unsigned char VEN_DB1[24] = {0x00};
unsigned char VEN_DB2[27] = {0x00};
unsigned char len = 0;
unsigned int vic = hdev->cur_VIC;
unsigned int hdmi_vic_4k_flag = 0;
static enum eotf_type ltype = EOTF_T_NULL;
static uint8_t ltmode = -1;
if (hdev->chip_type < MESON_CPU_ID_GXL) {
pr_info("hdmitx: not support DolbyVision\n");
if ((hdev->ready == 0) || (hdev->RXCap.dv_info.ieeeoui
!= DV_IEEE_OUI)) {
ltype = EOTF_T_NULL;
ltmode = -1;
return;
}
if ((vic == HDMI_3840x2160p30_16x9) ||
(vic == HDMI_3840x2160p25_16x9) ||
(vic == HDMI_3840x2160p24_16x9) ||
(vic == HDMI_4096x2160p24_256x135))
hdmi_vic_4k_flag = 1;
switch (type) {
case EOTF_T_DOLBYVISION:
len = 0x18;
break;
case EOTF_T_HDR10:
len = 0x05;
break;
case EOTF_T_SDR:
len = 0x05;
break;
case EOTF_T_NULL:
default:
len = 0x05;
break;
if ((hdev->chip_type) < MESON_CPU_ID_GXL) {
pr_info("hdmitx: not support DolbyVision\n");
return;
}
/*ver0 and ver1_15 use hdmi 1.4b VSIF*/
if ((hdev->RXCap.dv_info.ver == 0) || ((hdev->RXCap.dv_info.ver == 1)
&& (hdev->RXCap.dv_info.length == 0xE))) {
if ((vic == HDMI_3840x2160p30_16x9) ||
(vic == HDMI_3840x2160p25_16x9) ||
(vic == HDMI_3840x2160p24_16x9) ||
(vic == HDMI_4096x2160p24_256x135))
hdmi_vic_4k_flag = 1;
VEN_HB[2] = len;
VEN_DB[0] = 0x03;
VEN_DB[1] = 0x0c;
VEN_DB[2] = 0x00;
VEN_DB[3] = 0x00;
if (hdmi_vic_4k_flag) {
VEN_DB[3] = 0x20;
if (vic == HDMI_3840x2160p30_16x9)
VEN_DB[4] = 0x1;
else if (vic == HDMI_3840x2160p25_16x9)
VEN_DB[4] = 0x2;
else if (vic == HDMI_3840x2160p24_16x9)
VEN_DB[4] = 0x3;
else if (vic == HDMI_4096x2160p24_256x135)
VEN_DB[4] = 0x4;
else
VEN_DB[4] = 0x0;
}
if (type == EOTF_T_DOLBYVISION) {
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, VEN_DB, VEN_HB);
if (tunnel_mode == 1) {
hdev->HWOp.CntlConfig(hdev, CONF_AVI_RGBYCC_INDIC,
COLORSPACE_RGB444);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_Q01,
RGB_RANGE_FUL);
} else {
hdev->HWOp.CntlConfig(hdev, CONF_AVI_RGBYCC_INDIC,
COLORSPACE_YUV422);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_YQ01,
YCC_RANGE_FUL);
switch (type) {
case EOTF_T_DOLBYVISION:
len = 0x18;
hdev->dv_src_feature = 1;
break;
case EOTF_T_HDR10:
case EOTF_T_SDR:
case EOTF_T_NULL:
default:
len = 0x05;
hdev->dv_src_feature = 0;
break;
}
VEN_HB[2] = len;
VEN_DB1[0] = 0x03;
VEN_DB1[1] = 0x0c;
VEN_DB1[2] = 0x00;
VEN_DB1[3] = 0x00;
if (hdmi_vic_4k_flag) {
VEN_DB1[3] = 0x20;
if (vic == HDMI_3840x2160p30_16x9)
VEN_DB1[4] = 0x1;
else if (vic == HDMI_3840x2160p25_16x9)
VEN_DB1[4] = 0x2;
else if (vic == HDMI_3840x2160p24_16x9)
VEN_DB1[4] = 0x3;
else if (vic == HDMI_4096x2160p24_256x135)
VEN_DB1[4] = 0x4;
else
VEN_DB1[4] = 0x0;
}
if (type == EOTF_T_DOLBYVISION) {
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, VEN_DB1, VEN_HB);
if (tunnel_mode == RGB_8BIT) {
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC,
COLORSPACE_RGB444);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_Q01,
RGB_RANGE_FUL);
} else {
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC,
COLORSPACE_YUV422);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_YQ01,
YCC_RANGE_FUL);
}
} else {
if (hdmi_vic_4k_flag)
hdev->HWOp.SetPacket(
HDMI_PACKET_VEND, VEN_DB1, VEN_HB);
else
hdev->HWOp.SetPacket(
HDMI_PACKET_VEND, NULL, NULL);
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC, hdev->para->cs);
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_Q01, RGB_RANGE_LIM);
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_YQ01, YCC_RANGE_LIM);
}
}
/*ver1_12 and ver2 use Dolby VSIF*/
if ((hdev->RXCap.dv_info.ver == 2) || ((hdev->RXCap.dv_info.ver == 1)
&& (hdev->RXCap.dv_info.length == 0xB))) {
if (data == NULL)
data = &para;
/*4k vsif package */
if ((vic == HDMI_3840x2160p30_16x9) ||
(vic == HDMI_3840x2160p25_16x9) ||
(vic == HDMI_3840x2160p24_16x9) ||
(vic == HDMI_4096x2160p24_256x135))
hdmi_vic_4k_flag = 1;
switch (type) {
case EOTF_T_DOLBYVISION:
case EOTF_T_LL_MODE:
len = 0x1b;
hdev->dv_src_feature = 1;
break;
case EOTF_T_HDR10:
case EOTF_T_SDR:
case EOTF_T_NULL:
default:
len = 0x5;
hdev->dv_src_feature = 0;
break;
}
VEN_HB[2] = len;
VEN_DB2[0] = 0x46;
VEN_DB2[1] = 0xd0;
VEN_DB2[2] = 0x00;
VEN_DB2[3] = (data->vers.ver2.low_latency) |
(data->vers.ver2.dobly_vision_signal << 1);
VEN_DB2[4] = (data->vers.ver2.eff_tmax_PQ_hi)
| (data->vers.ver2.auxiliary_MD_present << 6)
| (data->vers.ver2.backlt_ctrl_MD_present << 7);
VEN_DB2[5] = data->vers.ver2.eff_tmax_PQ_low;
VEN_DB2[6] = data->vers.ver2.auxiliary_runmode;
VEN_DB2[7] = data->vers.ver2.auxiliary_runversion;
VEN_DB2[8] = data->vers.ver2.auxiliary_debug0;
/*Dolby Vision standard case*/
if (type == EOTF_T_DOLBYVISION) {
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, VEN_DB2, VEN_HB);
if (tunnel_mode == RGB_8BIT) {/*RGB444*/
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC,
COLORSPACE_RGB444);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_Q01,
RGB_RANGE_FUL);
} else {/*YUV422*/
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC,
COLORSPACE_YUV422);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_YQ01,
YCC_RANGE_FUL);
}
}
/*Dolby Vision low-latency case*/
else if (type == EOTF_T_LL_MODE) {
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, VEN_DB2, VEN_HB);
if (tunnel_mode == RGB_10_12BIT) {/*10/12bit RGB444*/
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC,
COLORSPACE_RGB444);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_Q01,
RGB_RANGE_LIM);
} else if (tunnel_mode == YUV444_10_12BIT) {
/*10/12bit YUV444*/
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC,
COLORSPACE_YUV444);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_YQ01,
YCC_RANGE_LIM);
} else {/*YUV422*/
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC,
COLORSPACE_YUV422);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_YQ01,
YCC_RANGE_LIM);
}
}
/*SDR case*/
else {
if (hdmi_vic_4k_flag) {
VEN_DB1[0] = 0x03;
VEN_DB1[1] = 0x0c;
VEN_DB1[2] = 0x00;
hdev->HWOp.SetPacket(
HDMI_PACKET_VEND, VEN_DB2, VEN_HB);
} else
hdev->HWOp.SetPacket(
HDMI_PACKET_VEND, NULL, NULL);
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_RGBYCC_INDIC, hdev->para->cs);
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_Q01, RGB_RANGE_LIM);
hdev->HWOp.CntlConfig(hdev,
CONF_AVI_YQ01, YCC_RANGE_LIM);
}
} else {
if (hdmi_vic_4k_flag)
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, VEN_DB, VEN_HB);
else
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, NULL, NULL);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_RGBYCC_INDIC,
hdev->para->cs);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_Q01, RGB_RANGE_LIM);
hdev->HWOp.CntlConfig(hdev, CONF_AVI_YQ01, YCC_RANGE_LIM);
}
}
@@ -1290,7 +1411,7 @@ static ssize_t store_config(struct device *dev,
hdmitx_device.HWOp.SetPacket(HDMI_PACKET_DRM,
DRM_DB, DRM_HB);
} else if (strncmp(buf, "vsif", 4) == 0)
hdmitx_set_vsif_pkt(buf[4] - '0', buf[5] == '1');
hdmitx_set_vsif_pkt(buf[4] - '0', buf[5] == '1', NULL);
return 16;
}
@@ -1581,9 +1702,9 @@ static ssize_t show_dc_cap(struct device *dev,
#if 0
if (pRXCap->dc_48bit_420)
pos += snprintf(buf + pos, PAGE_SIZE, "420,16bit\n");
#endif
if (pRXCap->dc_36bit_420)
pos += snprintf(buf + pos, PAGE_SIZE, "420,12bit\n");
#endif
if (pRXCap->dc_30bit_420) {
pos += snprintf(buf + pos, PAGE_SIZE, "420,10bit\n");
pos += snprintf(buf + pos, PAGE_SIZE, "420,8bit\n");
@@ -1611,12 +1732,8 @@ static ssize_t show_dc_cap(struct device *dev,
}
next444:
if (pRXCap->dc_y444) {
#if 0
if (pRXCap->dc_36bit)
pos += snprintf(buf + pos, PAGE_SIZE, "444,12bit\n");
if (pRXCap->dc_36bit)
pos += snprintf(buf + pos, PAGE_SIZE, "422,12bit\n");
#endif
if (pRXCap->dc_30bit) {
pos += snprintf(buf + pos, PAGE_SIZE, "444,10bit\n");
pos += snprintf(buf + pos, PAGE_SIZE, "444,8bit\n");
@@ -1625,6 +1742,8 @@ next444:
if (pRXCap->dc_48bit)
pos += snprintf(buf + pos, PAGE_SIZE, "444,16bit\n");
#endif
if (pRXCap->dc_36bit)
pos += snprintf(buf + pos, PAGE_SIZE, "422,12bit\n");
if (pRXCap->dc_30bit) {
pos += snprintf(buf + pos, PAGE_SIZE, "422,10bit\n");
pos += snprintf(buf + pos, PAGE_SIZE, "422,8bit\n");
@@ -1640,9 +1759,9 @@ nextrgb:
#if 0
if (pRXCap->dc_48bit)
pos += snprintf(buf + pos, PAGE_SIZE, "rgb,16bit\n");
#endif
if (pRXCap->dc_36bit)
pos += snprintf(buf + pos, PAGE_SIZE, "rgb,12bit\n");
#endif
if (pRXCap->dc_30bit)
pos += snprintf(buf + pos, PAGE_SIZE, "rgb,10bit\n");
pos += snprintf(buf + pos, PAGE_SIZE, "rgb,8bit\n");
@@ -1740,29 +1859,103 @@ static ssize_t show_dv_cap(struct device *dev,
struct device_attribute *attr, char *buf)
{
int pos = 0;
int i;
const struct dv_info *dv = &(hdmitx_device.RXCap.dv_info);
if (dv->ieeeoui != 0x00d046)
if (dv->ieeeoui != DV_IEEE_OUI) {
pos += snprintf(buf + pos, PAGE_SIZE,
"The Rx don't support DolbyVision\n");
return pos;
}
if (dv->block_flag != CORRECT) {
pos += snprintf(buf + pos, PAGE_SIZE,
"DolbyVision block is error\n");
return pos;
}
pos += snprintf(buf + pos, PAGE_SIZE,
"DolbyVision%d RX support list:\n", dv->ver);
if (dv->sup_yuv422_12bit)
pos += snprintf(buf + pos, PAGE_SIZE, " yuv422_12bit\n");
pos += snprintf(buf + pos, PAGE_SIZE,
" 2160p%shz: 1\n", dv->sup_2160p60hz ? "60" : "30");
if (dv->sup_global_dimming)
pos += snprintf(buf + pos, PAGE_SIZE, " global dimming\n");
if (dv->colorimetry)
pos += snprintf(buf + pos, PAGE_SIZE, " colorimetry\n");
pos += snprintf(buf + pos, PAGE_SIZE,
" IEEEOUI: 0x%06x\n", dv->ieeeoui);
if (dv->ver == 0)
pos += snprintf(buf + pos, PAGE_SIZE, " DM Ver: %x:%x\n",
dv->vers.ver0.dm_major_ver, dv->vers.ver0.dm_minor_ver);
if (dv->ver == 1)
pos += snprintf(buf + pos, PAGE_SIZE, " DM Ver: %x\n",
dv->vers.ver1.dm_version);
"DolbyVision RX support list:\n");
if (dv->ver == 0) {
pos += snprintf(buf + pos, PAGE_SIZE,
"VSVDB Version: V%d\n", dv->ver);
pos += snprintf(buf + pos, PAGE_SIZE,
"2160p%shz: 1\n",
dv->sup_2160p60hz ? "60" : "30");
pos += snprintf(buf + pos, PAGE_SIZE,
"Support mode:\n");
pos += snprintf(buf + pos, PAGE_SIZE,
" DV_RGB_444_8BIT\n");
if (dv->sup_yuv422_12bit)
pos += snprintf(buf + pos, PAGE_SIZE,
" DV_YCbCr_422_12BIT\n");
}
if (dv->ver == 1) {
pos += snprintf(buf + pos, PAGE_SIZE,
"VSVDB Version: V%d(%d-byte)\n",
dv->ver, dv->length + 1);
if (dv->length == 0xB) {
pos += snprintf(buf + pos, PAGE_SIZE,
"2160p%shz: 1\n",
dv->sup_2160p60hz ? "60" : "30");
pos += snprintf(buf + pos, PAGE_SIZE,
"Support mode:\n");
pos += snprintf(buf + pos, PAGE_SIZE,
" DV_RGB_444_8BIT\n");
if (dv->sup_yuv422_12bit)
pos += snprintf(buf + pos, PAGE_SIZE,
" DV_YCbCr_422_12BIT\n");
if (dv->low_latency == 0x01)
pos += snprintf(buf + pos, PAGE_SIZE,
" LL_YCbCr_422_12BIT\n");
}
if (dv->length == 0xE) {
pos += snprintf(buf + pos, PAGE_SIZE,
"2160p%shz: 1\n",
dv->sup_2160p60hz ? "60" : "30");
pos += snprintf(buf + pos, PAGE_SIZE,
"Support mode:\n");
pos += snprintf(buf + pos, PAGE_SIZE,
" DV_RGB_444_8BIT\n");
if (dv->sup_yuv422_12bit)
pos += snprintf(buf + pos, PAGE_SIZE,
" DV_YCbCr_422_12BIT\n");
}
}
if (dv->ver == 2) {
pos += snprintf(buf + pos, PAGE_SIZE,
"VSVDB Version: V%d\n", dv->ver);
pos += snprintf(buf + pos, PAGE_SIZE,
"2160p60hz: 1\n");
pos += snprintf(buf + pos, PAGE_SIZE,
"Support mode:\n");
if ((dv->Interface != 0x00) && (dv->Interface != 0x01)) {
pos += snprintf(buf + pos, PAGE_SIZE,
" DV_RGB_444_8BIT\n");
if (dv->sup_yuv422_12bit)
pos += snprintf(buf + pos, PAGE_SIZE,
" DV_YCbCr_422_12BIT\n");
}
pos += snprintf(buf + pos, PAGE_SIZE,
" LL_YCbCr_422_12BIT\n");
if ((dv->Interface == 0x01) || (dv->Interface == 0x03)) {
if (dv->sup_10b_12b_444 == 0x1) {
pos += snprintf(buf + pos, PAGE_SIZE,
" LL_RGB_444_10BIT\n");
}
if (dv->sup_10b_12b_444 == 0x2) {
pos += snprintf(buf + pos, PAGE_SIZE,
" LL_RGB_444_12BIT\n");
}
}
}
pos += snprintf(buf + pos, PAGE_SIZE,
"IEEEOUI: 0x%06x\n", dv->ieeeoui);
pos += snprintf(buf + pos, PAGE_SIZE, "VSVDB: ");
for (i = 0; i < (dv->length + 1); i++)
pos += snprintf(buf+pos, PAGE_SIZE, "%02x",
dv->rawdata[i]);
pos += snprintf(buf + pos, PAGE_SIZE, "\n");
return pos;
}
@@ -2793,6 +2986,8 @@ static void hdmitx_hpd_plugout_handler(struct work_struct *work)
mutex_unlock(&setclk_mutex);
return;
}
/*after plugout, DV mode can't be supported*/
hdmitx_set_vsif_pkt(0, 0, NULL);
hdev->ready = 0;
if (hdev->repeater_tx)
rx_repeat_hpd_state(0);

34
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c
View File

@@ -35,7 +35,7 @@
#include "hw/common.h"
static void hdmitx_set_spd_info(struct hdmitx_dev *hdmitx_device);
static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdmitx_device,
static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdev,
enum hdmi_vic VideoCode);
static struct hdmitx_vidpara hdmi_tx_video_params[] = {
@@ -659,30 +659,40 @@ static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdev,
int i;
unsigned char VEN_DB[6];
unsigned char VEN_HB[3];
VEN_HB[0] = 0x81;
VEN_HB[1] = 0x01;
VEN_HB[2] = 0x5;
if (VideoCode == 0) { /* For non-4kx2k mode setting */
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, NULL, VEN_HB);
return;
}
if ((hdev->RXCap.dv_info.block_flag == CORRECT) ||
(hdev->dv_src_feature == 1)) { /* For dolby */
return;
}
for (i = 0; i < 0x6; i++)
VEN_DB[i] = 0;
VEN_DB[0] = 0x03;
VEN_DB[1] = 0x0c;
VEN_DB[2] = 0x00;
VEN_DB[3] = 0x20; /* 4k x 2k Spec P156 */
if (VideoCode == 0) { /* For non-4kx2k mode setting */
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, NULL, VEN_HB);
return;
}
if (VideoCode == HDMI_4k2k_30)
VEN_DB[3] = 0x00; /* 4k x 2k Spec P156 */
if (VideoCode == HDMI_4k2k_30) {
VEN_DB[3] = 0x20;
VEN_DB[4] = 0x1;
else if (VideoCode == HDMI_4k2k_25)
} else if (VideoCode == HDMI_4k2k_25) {
VEN_DB[3] = 0x20;
VEN_DB[4] = 0x2;
else if (VideoCode == HDMI_4k2k_24)
} else if (VideoCode == HDMI_4k2k_24) {
VEN_DB[3] = 0x20;
VEN_DB[4] = 0x3;
else if (VideoCode == HDMI_4k2k_smpte_24)
} else if (VideoCode == HDMI_4k2k_smpte_24) {
VEN_DB[3] = 0x20;
VEN_DB[4] = 0x4;
else
} else
;
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, VEN_DB, VEN_HB);
}

12
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

@@ -2020,8 +2020,13 @@ static void hdmitx_set_packet(int type, unsigned char *DB, unsigned char *HB)
case HDMI_PACKET_VEND:
if ((!DB) || (!HB)) {
hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 0, 3, 1);
hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 0x0);
return;
}
/*DV function must set bit 0~1 to 0 in P_VPU_HDMI_FMT_CTRL */
if ((HB[2] == 0x18) || (HB[2] == 0x1b))
hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 0, 2);
hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID0, DB[0]);
hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID1, DB[1]);
hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID2, DB[2]);
@@ -2039,6 +2044,13 @@ static void hdmitx_set_packet(int type, unsigned char *DB, unsigned char *HB)
else
hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 6);
}
if (HB[2] == 0x1b) {/*set dolby vsif data information*/
hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, DB[4]);
hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD2, DB[5]);
hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD3, DB[6]);
hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD4, DB[7]);
hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD5, DB[8]);
}
/* Enable VSI packet */
hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 3, 1);
hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0);

48
include/linux/amlogic/media/amdolbyvision/dolby_vision.h Normal file
View File

@@ -0,0 +1,48 @@
#ifndef _DV_H_
#define _DV_H_
#define V1_5
#define V2_4
#include <linux/types.h>
extern void enable_dolby_vision(int enable);
extern bool is_dolby_vision_enable(void);
extern bool is_dolby_vision_on(void);
extern bool for_dolby_vision_certification(void);
extern void set_dolby_vision_mode(int mode);
extern int get_dolby_vision_mode(void);
extern void dolby_vision_set_toggle_flag(int flag);
extern int dolby_vision_wait_metadata(struct vframe_s *vf);
extern int dolby_vision_pop_metadata(void);
extern int dolby_vision_update_metadata(struct vframe_s *vf);
extern int dolby_vision_process(struct vframe_s *vf, u32 display_size);
extern void dolby_vision_init_receiver(void *pdev);
extern void dolby_vision_vf_put(struct vframe_s *vf);
extern struct vframe_s *dolby_vision_vf_peek_el(struct vframe_s *vf);
extern void dolby_vision_dump_setting(int debug_flag);
extern void dolby_vision_dump_struct(void);
extern void enable_osd_path(int on, int shadow_mode);
extern void tv_dolby_vision_config(int config);
extern void dolby_vision_update_pq_config(
char *pq_config_buf);
extern int dolby_vision_update_setting(void);
extern bool is_dolby_vision_stb_mode(void);
extern void tv_dolby_vision_crc_clear(int flag);
extern char *tv_dolby_vision_get_crc(u32 *len);
extern void tv_dolby_vision_insert_crc(bool print);
extern int dolby_vision_check_hdr10(struct vframe_s *vf);
extern void tv_dolby_vision_dma_table_modify(
u32 tbl_id, uint64_t value);
extern void tv_dolby_vision_efuse_info(void);
extern int dolby_vision_parse_metadata(
struct vframe_s *vf, u8 toggle_mode, bool bypass_release);
extern void dolby_vision_update_vsvdb_config(
char *vsvdb_buf, u32 tbl_size);
extern void tv_dolby_vision_el_info(void);
extern int enable_rgb_to_yuv_matrix_for_dvll(
int32_t on, uint32_t *coeff_orig, uint32_t bits);
#endif

18
include/linux/amlogic/media/amvecm/amvecm.h
View File

@@ -249,24 +249,6 @@ extern void amvecm_sharpness_enable(int sel);
extern int metadata_read_u32(uint32_t *value);
extern int metadata_wait(struct vframe_s *vf);
extern int metadata_sync(uint32_t frame_id, uint64_t pts);
extern void enable_dolby_vision(int enable);
extern bool is_dolby_vision_enable(void);
extern bool is_dolby_vision_on(void);
extern bool for_dolby_vision_certification(void);
extern void set_dolby_vision_mode(int mode);
extern int get_dolby_vision_mode(void);
extern void dolby_vision_set_toggle_flag(int flag);
extern int dolby_vision_wait_metadata(struct vframe_s *vf);
extern int dolby_vision_pop_metadata(void);
extern int dolby_vision_update_metadata(struct vframe_s *vf);
extern int dolby_vision_process(struct vframe_s *vf);
extern void dolby_vision_init_receiver(void);
extern void dolby_vision_vf_put(struct vframe_s *vf);
extern struct vframe_s *dolby_vision_vf_peek_el(struct vframe_s *vf);
extern void dolby_vision_dump_setting(int debug_flag);
extern void dolby_vision_dump_struct(void);
extern void enable_osd_path(int on, int shadow_mode);
extern void amvecm_wakeup_queue(void);
#endif /* AMVECM_H */

1
include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
View File

@@ -355,6 +355,7 @@ struct hdmitx_dev {
unsigned char hdmi_audio_off_flag;
enum hdmi_hdr_transfer hdr_transfer_feature;
enum hdmi_hdr_color hdr_color_feature;
unsigned int dv_src_feature;
unsigned int sdr_hdr_feature;
unsigned int flag_3dfp:1;
unsigned int flag_3dtb:1;

103
include/linux/amlogic/media/vout/vinfo.h
View File

@@ -66,50 +66,87 @@ enum eotf_type {
EOTF_T_DOLBYVISION,
EOTF_T_HDR10,
EOTF_T_SDR,
EOTF_T_LL_MODE,
EOTF_T_MAX,
};
/* Dolby Version support information */
struct dv_info {
uint32_t ieeeoui;
uint8_t ver; /* 0 or 1 */
uint8_t sup_yuv422_12bit:1; /* if as 0, then support RGB tunnel mode */
uint8_t sup_2160p60hz:1; /* if as 0, then support 2160p30hz */
uint8_t sup_global_dimming:1;
uint8_t colorimetry:1;
enum mode_type {
YUV422_BIT12 = 0,
RGB_8BIT,
RGB_10_12BIT,
YUV444_10_12BIT,
};
#define DV_IEEE_OUI 0x00D046
/* Dolby Version VSIF parameter*/
struct dv_vsif_para {
uint8_t ver; /* 0 or 1 or 2*/
uint8_t length;/*ver1: 15 or 12*/
union {
struct {
uint16_t chrom_red_primary_x;
uint16_t chrom_red_primary_y;
uint16_t chrom_green_primary_x;
uint16_t chrom_green_primary_y;
uint16_t chrom_blue_primary_x;
uint16_t chrom_blue_primary_y;
uint16_t chrom_white_primary_x;
uint16_t chrom_white_primary_y;
uint16_t target_min_pq;
uint16_t target_max_pq;
uint8_t dm_major_ver;
uint8_t dm_minor_ver;
} ver0;
struct {
uint8_t dm_version;
uint8_t target_max_lum;
uint8_t target_min_lum;
uint8_t chrom_red_primary_x;
uint8_t chrom_red_primary_y;
uint8_t chrom_green_primary_x;
uint8_t chrom_green_primary_y;
uint8_t chrom_blue_primary_x;
uint8_t chrom_blue_primary_y;
} ver1;
uint8_t low_latency:1;
uint8_t dobly_vision_signal:1;
uint8_t backlt_ctrl_MD_present:1;
uint8_t auxiliary_MD_present:1;
uint8_t eff_tmax_PQ_hi;
uint8_t eff_tmax_PQ_low;
uint8_t auxiliary_runmode;
uint8_t auxiliary_runversion;
uint8_t auxiliary_debug0;
} ver2;
} vers;
};
/* Dolby Version support information from EDID*/
/* Refer to DV Spec version2.9 page26 to page39*/
enum block_type {
ERROR_NULL = 0,
ERROR_LENGTH,
ERROR_OUI,
CORRECT,
};
struct dv_info {
unsigned char rawdata[27];
enum block_type block_flag;
uint32_t ieeeoui;
uint8_t ver; /* 0 or 1 or 2*/
uint8_t length;/*ver1: 15 or 12*/
uint8_t sup_yuv422_12bit:1;
/* if as 0, then support RGB tunnel mode */
uint8_t sup_2160p60hz:1;
/* if as 0, then support 2160p30hz */
uint8_t sup_global_dimming:1;
uint16_t Rx;
uint16_t Ry;
uint16_t Gx;
uint16_t Gy;
uint16_t Bx;
uint16_t By;
uint16_t Wx;
uint16_t Wy;
uint16_t tminPQ;
uint16_t tmaxPQ;
uint8_t dm_major_ver;
uint8_t dm_minor_ver;
uint8_t dm_version;
uint8_t tmaxLUM;
uint8_t colorimetry:1;/* ver1*/
uint8_t tminLUM;
uint8_t low_latency:1;/* ver1_12 and 2*/
uint8_t sup_backlight_control:1;/*only ver2*/
uint8_t backlt_min_luma;/*only ver2*/
uint8_t Interface;/*only ver2*/
uint8_t sup_10b_12b_444;/*only ver2*/
};
struct vout_device_s {
const struct dv_info *dv_info;
void (*fresh_tx_hdr_pkt)(struct master_display_info_s *data);
void (*fresh_tx_vsif_pkt)(enum eotf_type type, uint8_t tunnel_mode);
void (*fresh_tx_vsif_pkt)(enum eotf_type type,
enum mode_type tunnel_mode, struct dv_vsif_para *data);
};
struct vinfo_base_s {