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https://github.com/hardkernel/linux.git
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misc: rk628: enable rk628 hdmirx audio
Signed-off-by: Shunhua Lan <lsh@rock-chips.com> Change-Id: Ifd5fc3d15399b8eeca616c4f64b34956727bcd06
This commit is contained in:
Shunhua Lan
@@ -54,6 +54,28 @@ struct rk628_hdmi_mode {
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unsigned int flags;
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};
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#define INIT_FIFO_STATE 64
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#define is_validfs(x) (x == 32000 || \
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x == 44100 || \
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x == 48000 || \
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x == 88200 || \
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x == 96000 || \
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x == 176400 || \
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x == 192000 || \
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x == 768000)
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struct rk628_audiostate {
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u32 hdmirx_aud_clkrate;
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u32 fs_audio;
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u32 ctsn_flag;
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u32 fifo_flag;
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int init_state;
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int pre_state;
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bool fifo_int;
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bool audio_enable;
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};
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struct rk628_hdmirx {
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bool plugin;
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bool res_change;
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@@ -66,6 +88,9 @@ struct rk628_hdmirx {
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bool src_depth_10bit;
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bool phy_lock;
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bool is_hdmi2;
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struct rk628 *rk628;
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struct delayed_work delayed_work_audio;
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struct rk628_audiostate audio_state;
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};
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void rk628_hdmirx_reset_control_assert(struct rk628 *rk628)
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@@ -186,6 +211,212 @@ void rk628_hdmirx_phy_set_clrdpt(struct rk628 *rk628, bool is_8bit)
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hdmirx_phy_write(rk628, 0x03, 0x0060);
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}
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static uint32_t rk628_hdmirx_audio_fs(struct rk628 *rk628)
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{
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u64 tmdsclk = 0;
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u32 clkrate = 0, cts_decoded = 0, n_decoded = 0, fs_audio = 0;
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/* fout=128*fs=ftmds*N/CTS */
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rk628_i2c_read(rk628, HDMI_RX_HDMI_CKM_RESULT, &clkrate);
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clkrate = clkrate & 0xffff;
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/* tmdsclk = (clkrate/1000) * 49500000 */
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tmdsclk = clkrate * (49500000 / 1000);
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rk628_i2c_read(rk628, HDMI_RX_PDEC_ACR_CTS, &cts_decoded);
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rk628_i2c_read(rk628, HDMI_RX_PDEC_ACR_N, &n_decoded);
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if (cts_decoded != 0) {
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fs_audio = div_u64((tmdsclk * n_decoded), cts_decoded);
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fs_audio /= 128;
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fs_audio = div_u64(fs_audio + 50, 100);
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fs_audio *= 100;
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}
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dev_dbg(rk628->dev,
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"%s: clkrate:%u tmdsclk:%llu, n_decoded:%u, cts_decoded:%u, fs_audio:%u\n",
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__func__, clkrate, tmdsclk, n_decoded, cts_decoded, fs_audio);
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if (!is_validfs(fs_audio))
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fs_audio = 0;
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return fs_audio;
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}
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static void rk628_hdmirx_audio_clk_set_rate(struct rk628_hdmirx *hdmirx, u32 rate)
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{
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dev_dbg(hdmirx->rk628->dev, "%s: %u to %u\n",
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__func__, hdmirx->audio_state.hdmirx_aud_clkrate, rate);
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rk628_cru_clk_set_rate(hdmirx->rk628, CGU_CLK_HDMIRX_AUD, rate);
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hdmirx->audio_state.hdmirx_aud_clkrate = rate;
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}
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static void rk628_hdmirx_audio_clk_ppm_inc(struct rk628_hdmirx *hdmirx, int ppm)
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{
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int delta, rate, inc;
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rate = hdmirx->audio_state.hdmirx_aud_clkrate;
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if (ppm < 0) {
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ppm = -ppm;
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inc = -1;
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} else
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inc = 1;
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delta = (uint64_t)((uint64_t)rate * ppm + 500000) / 1000000;
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delta *= inc;
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rate += delta;
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dev_dbg(hdmirx->rk628->dev, "%s: %u to %u(delta:%d)\n",
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__func__, hdmirx->audio_state.hdmirx_aud_clkrate, rate, delta);
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rk628_cru_clk_set_rate(hdmirx->rk628, CGU_CLK_HDMIRX_AUD, rate);
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hdmirx->audio_state.hdmirx_aud_clkrate = rate;
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}
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static void rk628_hdmirx_audio_fifo_init(struct rk628_hdmirx *hdmirx)
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{
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rk628_i2c_write(hdmirx->rk628, HDMI_RX_AUD_FIFO_ICLR, 0x1f);
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rk628_i2c_write(hdmirx->rk628, HDMI_RX_AUD_FIFO_CTRL, 0x10001);
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//delay_us(100);
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rk628_i2c_write(hdmirx->rk628, HDMI_RX_AUD_FIFO_CTRL, 0x10000);
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}
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static void rk628_hdmirx_audio_set_fs(struct rk628_hdmirx *hdmirx, u32 fs_audio)
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{
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u32 hdmirx_aud_clkrate_t = fs_audio*128;
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dev_dbg(hdmirx->rk628->dev, "%s: %u to %u with fs %u\n", __func__,
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hdmirx->audio_state.hdmirx_aud_clkrate, hdmirx_aud_clkrate_t,
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fs_audio);
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rk628_hdmirx_audio_clk_set_rate(hdmirx, hdmirx_aud_clkrate_t);
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hdmirx->audio_state.fs_audio = fs_audio;
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}
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static const char *audio_fifo_err(u32 fifo_status)
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{
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switch (fifo_status & (AFIF_UNDERFL_ISTS | AFIF_OVERFL_ISTS)) {
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case AFIF_UNDERFL_ISTS:
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return "underflow";
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case AFIF_OVERFL_ISTS:
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return "overflow";
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case AFIF_UNDERFL_ISTS | AFIF_OVERFL_ISTS:
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return "underflow and overflow";
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}
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return "underflow or overflow";
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}
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static void rk628_hdmirx_delayed_work_audio(struct work_struct *work)
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{
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struct delayed_work *dwork = to_delayed_work(work);
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struct rk628_hdmirx *hdmirx = container_of(dwork, struct rk628_hdmirx,
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delayed_work_audio);
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struct rk628 *rk628 = hdmirx->rk628;
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struct rk628_audiostate *audio_state = &hdmirx->audio_state;
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u32 fs_audio;
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int init_state, pre_state, fifo_status, fifo_ints;
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unsigned long delay = 500;
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fs_audio = rk628_hdmirx_audio_fs(rk628);
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/* read fifo init status */
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rk628_i2c_read(rk628, HDMI_RX_AUD_FIFO_ISTS, &fifo_ints);
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dev_dbg(rk628->dev, "%s: HDMI_RX_AUD_FIFO_ISTS:%#x\r\n", __func__, fifo_ints);
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if (fifo_ints & (AFIF_UNDERFL_ISTS | AFIF_OVERFL_ISTS)) {
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dev_warn(rk628->dev, "%s: audio %s %#x, with fs %svalid %d\n",
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__func__, audio_fifo_err(fifo_ints), fifo_ints,
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is_validfs(fs_audio) ? "" : "in", fs_audio);
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if (is_validfs(fs_audio))
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rk628_hdmirx_audio_set_fs(hdmirx, fs_audio);
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rk628_hdmirx_audio_fifo_init(hdmirx);
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audio_state->pre_state = 0;
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goto exit;
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}
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/* read fifo fill status */
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init_state = audio_state->init_state;
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pre_state = audio_state->pre_state;
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rk628_i2c_read(rk628, HDMI_RX_AUD_FIFO_FILLSTS1, &fifo_status);
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dev_dbg(rk628->dev,
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"%s: HDMI_RX_AUD_FIFO_FILLSTS1:%#x, single offset:%d, total offset:%d\n",
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__func__, fifo_status, fifo_status - pre_state, fifo_status - init_state);
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if (!is_validfs(fs_audio)) {
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dev_dbg(rk628->dev,
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"%s: no supported fs(%u), fifo_status %d\n",
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__func__, fs_audio, fifo_status);
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delay = 1000;
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} else if (abs(fs_audio - audio_state->fs_audio) > 1000) {
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dev_info(rk628->dev, "%s: restart audio fs(%d -> %d)\n",
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__func__, audio_state->fs_audio, fs_audio);
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rk628_hdmirx_audio_set_fs(hdmirx, fs_audio);
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rk628_hdmirx_audio_fifo_init(hdmirx);
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audio_state->pre_state = 0;
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goto exit;
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}
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if (fifo_status != 0) {
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if (!hdmirx->audio_present) {
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dev_info(rk628->dev, "audio on");
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hdmirx->audio_present = true;
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}
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if (fifo_status - init_state > 16 && fifo_status - pre_state > 0)
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rk628_hdmirx_audio_clk_ppm_inc(hdmirx, 10);
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else if (fifo_status - init_state < -16 && fifo_status - pre_state < 0)
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rk628_hdmirx_audio_clk_ppm_inc(hdmirx, -10);
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} else {
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if (hdmirx->audio_present) {
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dev_info(rk628->dev, "audio off");
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hdmirx->audio_present = false;
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}
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}
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audio_state->pre_state = fifo_status;
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exit:
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schedule_delayed_work(&hdmirx->delayed_work_audio, msecs_to_jiffies(delay));
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}
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static void rk628_hdmirx_audio_setup(struct rk628 *rk628)
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{
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u32 audio_pll_n, audio_pll_cts;
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struct rk628_hdmirx *hdmirx = rk628->hdmirx;
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audio_pll_n = 5644;
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audio_pll_cts = 148500;
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hdmirx->audio_state.fs_audio = 0;
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hdmirx->audio_state.pre_state = 0;
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hdmirx->audio_state.init_state = INIT_FIFO_STATE*4;
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rk628_hdmirx_audio_set_fs(hdmirx, 44100);
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/* manual aud CTS */
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rk628_i2c_write(rk628, HDMI_RX_AUDPLL_GEN_CTS, audio_pll_cts);
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/* manual aud N */
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rk628_i2c_write(rk628, HDMI_RX_AUDPLL_GEN_N, audio_pll_n);
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/* aud CTS N en manual */
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rk628_i2c_update_bits(rk628, HDMI_RX_AUD_CLK_CTRL,
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CTS_N_REF_MASK, CTS_N_REF(1));
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/* aud pll ctrl */
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rk628_i2c_update_bits(rk628, HDMI_RX_AUD_PLL_CTRL,
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PLL_LOCK_TOGGLE_DIV_MASK, PLL_LOCK_TOGGLE_DIV(0));
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rk628_i2c_update_bits(rk628, HDMI_RX_AUD_FIFO_TH,
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AFIF_TH_START_MASK |
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AFIF_TH_MAX_MASK |
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AFIF_TH_MIN_MASK,
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AFIF_TH_START(INIT_FIFO_STATE) |
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AFIF_TH_MAX(8) |
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AFIF_TH_MIN(8));
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/* AUTO_VMUTE */
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rk628_i2c_update_bits(rk628, HDMI_RX_AUD_FIFO_CTRL,
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AFIF_SUBPACKET_DESEL_MASK |
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AFIF_SUBPACKETS_MASK,
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AFIF_SUBPACKET_DESEL(0) |
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AFIF_SUBPACKETS(1));
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rk628_i2c_write(rk628, HDMI_RX_AUD_SAO_CTRL,
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I2S_LPCM_BPCUV(0) |
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I2S_32_16(1));
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rk628_i2c_write(rk628, HDMI_RX_AUD_MUTE_CTRL,
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APPLY_INT_MUTE(0) |
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APORT_SHDW_CTRL(3) |
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AUTO_ACLK_MUTE(2) |
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AUD_MUTE_SPEED(1) |
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AUD_AVMUTE_EN(1) |
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AUD_MUTE_SEL(0) |
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AUD_MUTE_MODE(1));
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rk628_i2c_write(rk628, HDMI_RX_AUD_PAO_CTRL, PAO_RATE(0));
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rk628_i2c_write(rk628, HDMI_RX_AUD_CHEXTR_CTRL, AUD_LAYOUT_CTRL(1));
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/* audio detect */
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rk628_i2c_write(rk628, HDMI_RX_PDEC_AUDIODET_CTRL, AUDIODET_THRESHOLD(0));
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schedule_delayed_work(&hdmirx->delayed_work_audio, msecs_to_jiffies(1000));
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}
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static void rk628_hdmirx_ctrl_enable(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
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@@ -851,6 +1082,7 @@ static int rk628_hdmirx_init(struct rk628 *rk628)
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if (!hdmirx)
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return -ENOMEM;
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rk628->hdmirx = hdmirx;
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hdmirx->rk628 = rk628;
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/*
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* rk628f hdmirx phy can only access via hdmirx controller inner i2c.
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@@ -872,6 +1104,10 @@ static int rk628_hdmirx_init(struct rk628 *rk628)
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//i2s pinctrl
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rk628_i2c_write(rk628, GRF_GPIO0AB_SEL_CON, 0x155c155c);
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/* enable */
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rk628_i2c_write(rk628, GRF_GPIO1AB_SEL_CON, HIWORD_UPDATE(0, 0, 0));
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rk628_i2c_write(rk628, GRF_GPIO3AB_SEL_CON, HIWORD_UPDATE(1, 14, 14));
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/* if GVI and HDMITX OUT, HDMIRX missing signal */
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
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SW_OUTPUT_RGB_MODE_MASK,
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@@ -883,8 +1119,9 @@ static int rk628_hdmirx_init(struct rk628 *rk628)
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/* clear avi rcv interrupt */
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rk628_i2c_write(rk628, HDMI_RX_PDEC_ICLR, AVI_RCV_ISTS);
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_I2S_DATA_OEN_MASK, SW_I2S_DATA_OEN(0));
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dev_info(rk628->dev, "hdmirx driver version: %s\n", DRIVER_VERSION);
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INIT_DELAYED_WORK(&hdmirx->delayed_work_audio, rk628_hdmirx_delayed_work_audio);
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return 0;
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}
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@@ -950,6 +1187,7 @@ int rk628_hdmirx_enable(struct rk628 *rk628)
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ret = rk628_hdmirx_phy_setup(rk628);
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if (ret < 0)
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return HDMIRX_PLUGIN | HDMIRX_NOSIGNAL;
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rk628_hdmirx_audio_setup(rk628);
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rk628_hdmirx_get_input_format(rk628);
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rk628_set_input_bus_format(rk628, hdmirx->input_format);
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@@ -989,6 +1227,7 @@ void rk628_hdmirx_disable(struct rk628 *rk628)
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rk628_hdmirx_disable_edid(rk628);
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_I2S_DATA_OEN_MASK,
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SW_I2S_DATA_OEN(1));
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cancel_delayed_work_sync(&hdmirx->delayed_work_audio);
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dev_info(rk628->dev, "hdmirx plug out\n");
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}
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}
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@@ -483,6 +483,11 @@
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#define HDMI_RX_AUD_CEC_ISET HDMIRX_REG(0x0fa4)
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#define HDMI_RX_AUD_FIFO_IEN_CLR HDMIRX_REG(0x0fa8)
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#define HDMI_RX_AUD_FIFO_IEN_SET HDMIRX_REG(0x0fac)
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#define AFIF_OVERFL_ISTS BIT(4)
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#define AFIF_UNDERFL_ISTS BIT(3)
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#define AFIF_THS_PASS_ISTS BIT(2)
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#define AFIF_TH_MAX_ISTS BIT(1)
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#define AFIF_TH_MIN_ISTS BIT(0)
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#define HDMI_RX_AUD_FIFO_ISTS HDMIRX_REG(0x0fb0)
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#define HDMI_RX_AUD_FIFO_IEN HDMIRX_REG(0x0fb4)
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#define HDMI_RX_AUD_FIFO_ICLR HDMIRX_REG(0x0fb8)
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