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vpp: sr: correct the sr core0 enable switch operation [1/1]

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PD#SWPL-5113

Problem:
SR core0 enable switch register is latched as default. It
will cause the screen flicker when operating this bit in vsync.
Because the frame size will be out of sync with back-end module.

Solution:
1. For g12a, no latch ctrl. So did not disable sr core2 enable bit.
2. For g12b/tl1, disable the latch function.

Verify:
Verified on U212/w400/x301

Change-Id: I54027b71ef8a6066004b3bd32ed1633b4bfa351c
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2019-03-01 03:16:45 +08:00
committed by Luan Yuan
parent a89df5ec9e
commit 5b49adddeb
2 changed files with 9 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/amlogic/media/video_sink/video.c
View File

@@ -12069,13 +12069,13 @@ static int __init video_early_init(void)
DOLBY_PATH_CTRL, 0xf, 0, 6);
/* disable latch for sr core0/1 scaler */
WRITE_VCBUS_REG_BITS(
SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1);
WRITE_VCBUS_REG_BITS(
SRSHARP1_SHARP_SYNC_CTRL, 1, 8, 1);
}
if (is_meson_g12b_cpu())
WRITE_VCBUS_REG_BITS(
SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1);
return 0;
}

9
drivers/amlogic/media/video_sink/vpp.c
View File

@@ -1614,11 +1614,16 @@ int vpp_set_super_scaler_regs(
int tmp_data = 0;
int tmp_data2 = 0;
unsigned int data_path_chose;
int sr_core0_max_width = SUPER_CORE0_WIDTH_MAX;
/* just work around for g12a not to disable sr core2 bit2 */
if (is_meson_g12a_cpu() && (reg_srscl0_vert_ratio == 0))
sr_core0_max_width = SUPER_CORE0_WIDTH_MAX << 1;
/* top config */
tmp_data = VSYNC_RD_MPEG_REG(VPP_SRSHARP0_CTRL);
if (sr0_sr1_refresh) {
if (reg_srscl0_hsize > SUPER_CORE0_WIDTH_MAX) {
if (reg_srscl0_hsize > sr_core0_max_width) {
if (((tmp_data >> 1) & 0x1) != 0)
VSYNC_WR_MPEG_REG_BITS(VPP_SRSHARP0_CTRL,
0, 1, 1);
@@ -1650,7 +1655,7 @@ int vpp_set_super_scaler_regs(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt,
reg_srscl0_hori_ratio&0x1, 4, 1);
if (reg_srscl0_hsize > SUPER_CORE0_WIDTH_MAX) {
if (reg_srscl0_hsize > sr_core0_max_width) {
if (((tmp_data >> 2) & 0x1) != 0)
VSYNC_WR_MPEG_REG_BITS(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt,