shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-05 02:21:52 +09:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt

Browse Source 
AT91 DT for v5.20

It contains:
- compilation warning fixes for SAMA5D2
- updates for all AT91 device tree to use generic name for reset
  controller
- reset controller node for SAMA7G5
- MCAN1 and UDPHS nodes for LAN966 SoCs
- Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope
  with reality

* tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: lan966x: Add UDPHS support
  dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string
  ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.
  ARM: dts: lan966x: Add mcan1 node.
  ARM: dts: at91: sama7g5: add reset-controller node
  ARM: dts: at91: use generic name for reset controller
  ARM: dts: at91: sama5d2: fix compilation warning
  ARM: dts: at91: sama5d2: fix compilation warning

Link: https://lore.kernel.org/r/20220705084637.818216-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-07-06 13:42:46 +02:00
parent 11303e4e4c 4dd1a613e4
commit 5b98b4021e
19 changed files with 69 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/usb/atmel-usb.txt
View File

@@ -87,6 +87,9 @@ Required properties:
"atmel,at91sam9g45-udc"
"atmel,sama5d3-udc"
"microchip,sam9x60-udc"
"microchip,lan9662-udc"
For "microchip,lan9662-udc" the fallback "atmel,sama5d3-udc"
is required.
- reg: Address and length of the register set for the device
- interrupts: Should contain usba interrupt
- clocks: Should reference the peripheral and host clocks

2
arch/arm/boot/dts/at91-sama5d27_som1.dtsi
View File

@@ -83,6 +83,8 @@
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default>;
#address-cells = <1>;
#size-cells = <0>;
phy-mode = "rmii";
ethernet-phy@7 {

2
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
View File

@@ -194,6 +194,8 @@
&macb0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default>;
#address-cells = <1>;
#size-cells = <0>;
phy-mode = "rmii";
ethernet-phy@0 {

2
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
View File

@@ -139,6 +139,8 @@
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
#address-cells = <1>;
#size-cells = <0>;
phy-mode = "rmii";
status = "okay";

2
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@@ -147,6 +147,8 @@
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
#address-cells = <1>;
#size-cells = <0>;
phy-mode = "rmii";
status = "okay";

2
arch/arm/boot/dts/at91sam9260.dtsi
View File

@@ -123,7 +123,7 @@
clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;

2
arch/arm/boot/dts/at91sam9261.dtsi
View File

@@ -603,7 +603,7 @@
clock-names = "slow_xtal", "main_xtal";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;

2
arch/arm/boot/dts/at91sam9263.dtsi
View File

@@ -151,7 +151,7 @@
clock-names = "t0_clk", "slow_clk";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;

2
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@@ -137,7 +137,7 @@
clock-names = "slow_clk", "main_xtal";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@@ -126,7 +126,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
};
rstc@fffffe00 {
reset-controller@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@@ -766,7 +766,7 @@
clock-names = "slow_clk", "main_xtal";
};
rstc@fffffd00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@@ -134,7 +134,7 @@
clock-names = "slow_clk", "main_xtal";
};
reset_controller: rstc@fffffe00 {
reset_controller: reset-controller@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;

18
arch/arm/boot/dts/lan966x-pcb8291.dts
View File

@@ -19,19 +19,9 @@
};
&gpio {
fc_shrd7_pins: fc_shrd7-pins {
pins = "GPIO_49";
function = "fc_shrd7";
};
fc_shrd8_pins: fc_shrd8-pins {
pins = "GPIO_54";
function = "fc_shrd8";
};
fc3_b_pins: fcb3-spi-pins {
/* SCK, RXD, TXD */
pins = "GPIO_51", "GPIO_52", "GPIO_53";
fc3_b_pins: fc3-b-pins {
/* RX, TX */
pins = "GPIO_52", "GPIO_53";
function = "fc3_b";
};
@@ -53,7 +43,7 @@
status = "okay";
usart3: serial@200 {
pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>;
pinctrl-0 = <&fc3_b_pins>;
pinctrl-names = "default";
status = "okay";
};

26
arch/arm/boot/dts/lan966x.dtsi
View File

@@ -84,6 +84,17 @@
#size-cells = <1>;
ranges;
udc: usb@200000 {
compatible = "microchip,lan9662-udc",
"atmel,sama5d3-udc";
reg = <0x00200000 0x80000>,
<0xe0808000 0x400>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>;
clock-names = "pclk", "hclk";
status = "disabled";
};
switch: switch@e0000000 {
compatible = "microchip,lan966x-switch";
reg = <0xe0000000 0x0100000>,
@@ -473,6 +484,21 @@
status = "disabled";
};
can1: can@e0820000 {
compatible = "bosch,m_can";
reg = <0xe0820000 0xfc>, <0x00100000 0x8000>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>;
clock-names = "hclk", "cclk";
assigned-clocks = <&clks GCK_ID_MCAN1>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>;
status = "disabled";
};
reset: reset-controller@e200400c {
compatible = "microchip,lan966x-switch-reset";
reg = <0xe200400c 0x4>;

2
arch/arm/boot/dts/sam9x60.dtsi
View File

@@ -667,7 +667,7 @@
clock-names = "td_slck", "md_slck", "main_xtal";
};
reset_controller: rstc@fffffe00 {
reset_controller: reset-controller@fffffe00 {
compatible = "microchip,sam9x60-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k 0>;

24
arch/arm/boot/dts/sama5d2.dtsi
View File

@@ -99,6 +99,16 @@
ranges = <0 0x00200000 0x20000>;
};
resistive_touch: resistive-touch {
compatible = "resistive-adc-touch";
io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
<&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
<&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
io-channel-names = "x", "y", "pressure";
touchscreen-min-pressure = <50000>;
status = "disabled";
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -374,8 +384,6 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
clock-names = "hclk", "pclk";
status = "disabled";
@@ -660,7 +668,7 @@
ranges = <0 0xf8044000 0x1420>;
};
reset_controller: rstc@f8048000 {
reset_controller: reset-controller@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
clocks = <&clk32k>;
@@ -1050,16 +1058,6 @@
status = "disabled";
};
resistive_touch: resistive-touch {
compatible = "resistive-adc-touch";
io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
<&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
<&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
io-channel-names = "x", "y", "pressure";
touchscreen-min-pressure = <50000>;
status = "disabled";
};
pioA: pinctrl@fc038000 {
compatible = "atmel,sama5d2-pinctrl";
reg = <0xfc038000 0x600>;

2
arch/arm/boot/dts/sama5d3.dtsi
View File

@@ -1003,7 +1003,7 @@
clock-names = "slow_clk", "main_xtal";
};
reset_controller: rstc@fffffe00 {
reset_controller: reset-controller@fffffe00 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;

2
arch/arm/boot/dts/sama5d4.dtsi
View File

@@ -726,7 +726,7 @@
};
};
reset_controller: rstc@fc068600 {
reset_controller: reset-controller@fc068600 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfc068600 0x10>;
clocks = <&clk32k>;

7
arch/arm/boot/dts/sama7g5.dtsi
View File

@@ -198,6 +198,13 @@
clock-names = "td_slck", "md_slck", "main_xtal";
};
reset_controller: reset-controller@e001d000 {
compatible = "microchip,sama7g5-rstc";
reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
#reset-cells = <1>;
clocks = <&clk32k 0>;
};
shdwc: shdwc@e001d010 {
compatible = "microchip,sama7g5-shdwc", "syscon";
reg = <0xe001d010 0x10>;