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UPSTREAM: ARM: dts: rockchip: move rk3288 usbphy under the GRF node
The rk3288 usbphy is completely enclosed in the general register files
and the updated binding allows it to be a subnode of the GRF now.
So move the node appropriately.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I85ca27786da0cd388ef6b4fddb11747761a579a3
(cherry picked from commit 546a3521f2)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This commit is contained in:
@@ -859,6 +859,38 @@
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compatible = "rockchip,rk3288-io-voltage-domain";
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status = "disabled";
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};
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usbphy: phy {
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compatible = "rockchip,rk3288-usb-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy0 {
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#phy-cells = <0>;
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reg = <0x320>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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resets = <&cru SRST_USBOTG_PHY>;
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reset-names = "phy-reset";
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};
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usbphy1: usb-phy1 {
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#phy-cells = <0>;
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reg = <0x334>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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};
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usbphy2: usb-phy2 {
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#phy-cells = <0>;
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reg = <0x348>;
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clocks = <&cru SCLK_OTGPHY2>;
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clock-names = "phyclk";
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resets = <&cru SRST_USBHOST1_PHY>;
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reset-names = "phy-reset";
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};
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};
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};
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wdt: watchdog@ff800000 {
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@@ -1252,39 +1284,6 @@
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};
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};
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usbphy: phy {
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compatible = "rockchip,rk3288-usb-phy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy0 {
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#phy-cells = <0>;
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reg = <0x320>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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resets = <&cru SRST_USBOTG_PHY>;
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reset-names = "phy-reset";
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};
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usbphy1: usb-phy1 {
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#phy-cells = <0>;
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reg = <0x334>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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};
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usbphy2: usb-phy2 {
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#phy-cells = <0>;
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reg = <0x348>;
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clocks = <&cru SCLK_OTGPHY2>;
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clock-names = "phyclk";
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resets = <&cru SRST_USBHOST1_PHY>;
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reset-names = "phy-reset";
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};
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};
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cif_isp0: cif_isp@ff910000 {
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compatible = "rockchip,rk3288-cif-isp";
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rockchip,grf = <&grf>;
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