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pinctrl: rockchip: add rv1126b support

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Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: Ibb75f7b8f6b9ec72dd73b533e4d1cb0b49bccace
This commit is contained in:
Ye Zhang
2024-10-31 09:31:06 +08:00
committed by Tao Huang
parent c8d6e2b552
commit 5c4bc56605
2 changed files with 184 additions and 3 deletions
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186
drivers/pinctrl/pinctrl-rockchip.c
View File

@@ -316,6 +316,19 @@
#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
#define PIN_BANK_IOMUX_4_OFFSET_DRV_8(id, pins, label, offset0, \
offset1, offset2, offset3) \
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
offset0, offset1, \
offset2, offset3, \
DRV_TYPE_IO_LEVEL_8_BIT, \
DRV_TYPE_IO_LEVEL_8_BIT, \
DRV_TYPE_IO_LEVEL_8_BIT, \
DRV_TYPE_IO_LEVEL_8_BIT)
static struct pinctrl_dev *g_pctldev;
static DEFINE_MUTEX(iomux_lock);
@@ -1986,6 +1999,136 @@ static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RV1126B_DRV_BITS_PER_PIN 8
#define RV1126B_DRV_PINS_PER_REG 2
#define RV1126B_DRV_GPIO0_A_OFFSET 0x100
#define RV1126B_DRV_GPIO0_C_OFFSET 0x8120
#define RV1126B_DRV_GPIO_OFFSET(GPION) (0x8100 + GPION * 0x8040)
static int rv1126b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
if (pin_num < 16)
*reg = RV1126B_DRV_GPIO0_A_OFFSET;
else
*reg = RV1126B_DRV_GPIO0_C_OFFSET - 0x20;
break;
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
*reg = RV1126B_DRV_GPIO_OFFSET(bank->bank_num);
break;
default:
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
break;
}
*reg += ((pin_num / RV1126B_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RV1126B_DRV_PINS_PER_REG;
*bit *= RV1126B_DRV_BITS_PER_PIN;
return 0;
}
#define RV1126B_PULL_BITS_PER_PIN 2
#define RV1126B_PULL_PINS_PER_REG 8
#define RV1126B_PULL_GPIO0_A_OFFSET 0x300
#define RV1126B_PULL_GPIO0_C_OFFSET 0x8308
#define RV1126B_PULL_GPIO_OFFSET(GPION) (0x8300 + GPION * 0x8010)
static int rv1126b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
if (pin_num < 16)
*reg = RV1126B_PULL_GPIO0_A_OFFSET;
else
*reg = RV1126B_PULL_GPIO0_C_OFFSET - 0x8;
break;
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
*reg = RV1126B_PULL_GPIO_OFFSET(bank->bank_num);
break;
default:
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
break;
}
*reg += ((pin_num / RV1126B_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RV1126B_PULL_PINS_PER_REG;
*bit *= RV1126B_PULL_BITS_PER_PIN;
return 0;
}
#define RV1126B_SMT_BITS_PER_PIN 1
#define RV1126B_SMT_PINS_PER_REG 8
#define RV1126B_SMT_GPIO0_A_OFFSET 0x500
#define RV1126B_SMT_GPIO0_C_OFFSET 0x8508
#define RV1126B_SMT_GPIO_OFFSET(GPION) (0x8500 + GPION * 0x8010)
static int rv1126b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
if (pin_num < 16)
*reg = RV1126B_SMT_GPIO0_A_OFFSET;
else
*reg = RV1126B_SMT_GPIO0_C_OFFSET - 0x8;
break;
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
*reg = RV1126B_SMT_GPIO_OFFSET(bank->bank_num);
break;
default:
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
break;
}
*reg += ((pin_num / RV1126B_SMT_PINS_PER_REG) * 4);
*bit = pin_num % RV1126B_SMT_PINS_PER_REG;
*bit *= RV1126B_SMT_BITS_PER_PIN;
return 0;
}
#define RK3308_SCHMITT_PINS_PER_REG 8
#define RK3308_SCHMITT_BANK_STRIDE 16
#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
@@ -3601,9 +3744,10 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask_bits = RV1126_DRV_BITS_PER_PIN;
ret = strength;
goto config;
} else if (ctrl->type == RV1106 ||
ctrl->type == RK3506 ||
ctrl->type == RK3528 ||
} else if (ctrl->type == RV1106 ||
ctrl->type == RV1126B ||
ctrl->type == RK3506 ||
ctrl->type == RK3528 ||
ctrl->type == RK3562 ||
ctrl->type == RK3568) {
rmask_bits = RK3568_DRV_BITS_PER_PIN;
@@ -3781,6 +3925,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
case RV1106:
case RV1108:
case RV1126:
case RV1126B:
case RK1808:
case RK3188:
case RK3288:
@@ -3846,6 +3991,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RV1106:
case RV1108:
case RV1126:
case RV1126B:
case RK1808:
case RK3188:
case RK3288:
@@ -4225,6 +4371,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RV1106:
case RV1108:
case RV1126:
case RV1126B:
case RK1808:
case RK3188:
case RK3288:
@@ -5164,6 +5311,35 @@ static struct rockchip_pin_ctrl rv1126_pin_ctrl __maybe_unused = {
.schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rv1126b_pin_banks[] = {
PIN_BANK_IOMUX_4_OFFSET_DRV_8(0, 32, "gpio0",
0x0, 0x8, 0x8010, 0x8018),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(1, 32, "gpio1",
0x10020, 0x10028, 0x10030, 0x10038),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(2, 32, "gpio2",
0x18040, 0x18048, 0x18050, 0x18058),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(3, 32, "gpio3",
0x20060, 0x20068, 0x20070, 0x20078),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(4, 32, "gpio4",
0x28080, 0x28088, 0x28090, 0x28098),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(5, 32, "gpio5",
0x300a0, 0x300a8, 0x300b0, 0x300b8),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(6, 32, "gpio6",
0x380c0, 0x380c8, 0x380d0, 0x380d8),
PIN_BANK_IOMUX_4_OFFSET_DRV_8(7, 32, "gpio7",
0x400e0, 0x400e8, 0x400f0, 0x400f8),
};
static struct rockchip_pin_ctrl rv1126b_pin_ctrl __maybe_unused = {
.pin_banks = rv1126b_pin_banks,
.nr_banks = ARRAY_SIZE(rv1126b_pin_banks),
.label = "RV1126B-GPIO",
.type = RV1126B,
.pull_calc_reg = rv1126b_calc_pull_reg_and_bit,
.drv_calc_reg = rv1126b_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1126b_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk1808_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
@@ -5794,6 +5970,10 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rv1126-pinctrl",
.data = &rv1126_pin_ctrl },
#endif
#ifdef CONFIG_CPU_RV1126B
{ .compatible = "rockchip,rv1126b-pinctrl",
.data = &rv1126b_pin_ctrl },
#endif
#ifdef CONFIG_CPU_RK1808
{ .compatible = "rockchip,rk1808-pinctrl",
.data = &rk1808_pin_ctrl },

1
drivers/pinctrl/pinctrl-rockchip.h
View File

@@ -191,6 +191,7 @@ enum rockchip_pinctrl_type {
RV1106,
RV1108,
RV1126,
RV1126B,
RK1808,
RK2928,
RK3066B,