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Merge branch 'develop-3.10' of ssh://10.10.10.29/rk/kernel into develop-3.10

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This commit is contained in:
xbw
2014-02-25 12:35:25 +08:00
parent 9913355ce3 0ad0a29a89
commit 5cbd50029c
17 changed files with 3869 additions and 140 deletions
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57
arch/arm/boot/dts/lcd-LP097Qx1.dtsi Normal file
View File

@@ -0,0 +1,57 @@
/*
* RockChip. LCD_B101ew05
*
*/
/ {
disp_power_ctr: power_ctr {
rockchip,debug = <0>;
/*lcd_en:lcd_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio0 GPIO_B0 1>;
rockchip,delay = <10>;
};
bl_en:bl_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio0 GPIO_A2 1>;
rockchip,delay = <10>;
};
bl_ctr:bl_ctr {
rockchip,power_type = <GPIO>;
gpios = <&gpio3 GPIO_D6 1>;
rockchip,delay = <10>;
};
lcd_rst:lcd_rst {
rockchip,power_type = <REGULATOR>;
rockchip,delay = <5>;
};*/
};
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen-type = <SCREEN_EDP>;
out-face = <OUT_P666>;
clock-frequency = <205000000>;
hactive = <2048>;
vactive = <1536>;
hback-porch = <5>;
hfront-porch = <150>;
vback-porch = <9>;
vfront-porch = <3>;
hsync-len = <5>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};
};

34
arch/arm/boot/dts/lcd-b101ew05.dtsi
View File

@@ -8,19 +8,19 @@
rockchip,debug = <0>;
lcd_en:lcd_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio0 GPIO_B0 1>;
gpios = <&gpio0 GPIO_B0 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
/* bl_en:bl_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio0 GPIO_A2 1>;
gpios = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
bl_ctr:bl_ctr {
rockchip,power_type = <GPIO>;
gpios = <&gpio3 GPIO_D6 1>;
gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
@@ -34,19 +34,25 @@
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
screen_type = <SCREEN_LVDS>;
lvds_format = <LVDS_8BIT_2>;
out_face = <OUT_D888_P666>;
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <100>;
hfront-porch = <18>;
vback-porch = <8>;
vfront-porch = <6>;
hsync-len = <10>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
vactive = <800>;
hback-porch = <100>;
hfront-porch = <18>;
vback-porch = <8>;
vfront-porch = <6>;
hsync-len = <10>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
swap-rb = <0>;
swap-rg = <0>;
swap-gb = <0>;
};
};
};

369
arch/arm/boot/dts/rk3188-lr097.dts Normal file
View File

@@ -0,0 +1,369 @@
/dts-v1/;
#include "rk3188.dtsi"
#include "rk3188-clocks.dtsi"
#include "lcd-LP097Qx1.dtsi"
/ {
memory {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
chosen {
bootargs = "clk_ignore_unused";
};
fiq-debugger {
status = "okay";
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
gpios = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>;
};
codec-hdmi-i2s {
compatible = "hdmi-i2s";
};
codec-hdmi-spdif {
compatible = "hdmi-spdif";
};
rockchip-rt5631 {
compatible = "rockchip-rt5631";
dais {
dai0 {
codec-name = "rt5631.0-001a";
cpu-dai-name = "rockchip-i2s.1";
format = "i2s";
//continuous-clock;
//bitclock-inversion;
//frame-inversion;
//bitclock-master;
//frame-master;
};
};
};
rockchip-hdmi-i2s {
compatible = "rockchip-hdmi-i2s";
dais {
dai0 {
codec-name = "hdmi-i2s";
cpu-dai-name = "rockchip-i2s.1";
format = "i2s";
//continuous-clock;
//bitclock-inversion;
//frame-inversion;
//bitclock-master;
//frame-master;
};
};
};
rockchip-hdmi-spdif {
compatible = "rockchip-hdmi-spdif";
};
};
&uart0 {
status = "okay";
};
&uart3 {
status = "okay";
};
&i2c0 {
status = "okay";
codec@1a {
compatible = "rt5631";
reg = <0x1a>;
};
};
&i2c1 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
act8846: act8846@5a {
reg = <0x5a>;
status = "okay";
};
rk808: rk808@1b {
reg = <0x1b>;
status = "okay";
};
};
&i2c2 {
status = "okay";
edp@39 {
compatible = "analogix,anx6345";
reg = <0x39>;
dvdd33-gpio = <&gpio0 GPIO_B0 GPIO_ACTIVE_LOW>;
dvdd18-gpio = <&gpio3 GPIO_D4 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;
};
};
&i2c3 {
status = "okay";
};
&fb {
rockchip,disp-mode = <DUAL>;
};
&lcdc0 {
status = "okay";
power_ctr = <&disp_power_ctr>;
display-timings = <&disp_timings>;
};
&lcdc1 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&clk_core_dvfs_table {
operating-points = <
/* KHz uV */
312000 1100000
504000 1100000
816000 1100000
1008000 1100000
1200000 1200000
1416000 1300000
1608000 1350000
>;
};
&clk_gpu_dvfs_table {
operating-points = <
/* KHz uV */
200000 1200000
300000 1200000
400000 1300000
>;
};
&clk_ddr_dvfs_table {
operating-points = <
/* KHz uV */
200000 1200000
300000 1200000
400000 1300000
>;
};
/include/ "act8846.dtsi"
&act8846 {
gpios =<&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
regulators {
dcdc1_reg: regulator@0{
regulator-name= "act_dcdc1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
dcdc2_reg: regulator@1 {
regulator-name= "vdd_logic";
regulator-always-on;
regulator-boot-on;
};
dcdc3_reg: regulator@2 {
regulator-name= "vdd_arm";
regulator-always-on;
regulator-boot-on;
};
dcdc4_reg: regulator@3 {
regulator-name= "act_dcdc4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo1_reg: regulator@4 {
regulator-name= "act_ldo1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
ldo2_reg: regulator@5 {
regulator-name= "act_ldo2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
ldo3_reg: regulator@6 {
regulator-name= "act_ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg:regulator@7 {
regulator-name= "act_ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo5_reg: regulator@8 {
regulator-name= "act_ldo5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo6_reg: regulator@9 {
regulator-name= "act_ldo6";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo7_reg: regulator@10 {
regulator-name= "act_ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo8_reg: regulator@11 {
regulator-name= "act_ldo8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
/include/ "rk808.dtsi"
&rk808{
gpios =<&gpio0 GPIO_B3 GPIO_ACTIVE_HIGH>,<&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>;
regulators {
rk808_dcdc1_reg: regulator@0{
regulator-name= "vdd_arm";
regulator-always-on;
regulator-boot-on;
};
rk808_dcdc2_reg: regulator@1 {
regulator-name= "vdd_logic";
regulator-always-on;
regulator-boot-on;
};
rk808_dcdc3_reg: regulator@2 {
regulator-name= "rk_dcdc3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
rk808_dcdc4_reg: regulator@3 {
regulator-name= "rk_dcdc4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo1_reg: regulator@4 {
regulator-name= "rk_ldo1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo2_reg: regulator@5 {
regulator-name= "rk_ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo3_reg: regulator@6 {
regulator-name= "rk_ldo3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo4_reg:regulator@7 {
regulator-name= "rk_ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo5_reg: regulator@8 {
regulator-name= "rk_ldo5";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo6_reg: regulator@9 {
regulator-name= "rk_ldo6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo7_reg: regulator@10 {
regulator-name= "rk_ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo8_reg: regulator@11 {
regulator-name= "rk_ldo8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
};

15
drivers/video/of_display_timing.c
View File

@@ -98,6 +98,21 @@ static struct display_timing *of_get_display_timing(struct device_node *np)
if (of_property_read_bool(np, "doublescan"))
dt->flags |= DISPLAY_FLAGS_DOUBLESCAN;
#if defined(CONFIG_FB_ROCKCHIP)
if (!of_property_read_u32(np, "swap-rg", &val))
dt->flags |= val ? DISPLAY_FLAGS_SWAP_RG : 0;
if (!of_property_read_u32(np, "swap-gb", &val))
dt->flags |= val ? DISPLAY_FLAGS_SWAP_GB : 0;
if (!of_property_read_u32(np, "swap-rb", &val))
dt->flags |= val ? DISPLAY_FLAGS_SWAP_RB : 0;
if (!of_property_read_u32(np, "screen-type", &val))
dt->screen_type = val;
if (!of_property_read_u32(np, "lvds-format", &val))
dt->lvds_format = val;
if (!of_property_read_u32(np, "out-face", &val))
dt->face = val;
#endif
if (ret) {
pr_err("%s: error reading timing properties\n",
of_node_full_name(np));

55
drivers/video/rockchip/rk_fb.c
View File

@@ -92,7 +92,7 @@ int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv)
dev_err(dev_drv->dev, "%s ivalid gpio\n", child->name);
return -EINVAL;
}
pwr_ctr->pwr_ctr.atv_val = flags & OF_GPIO_ACTIVE_LOW;
pwr_ctr->pwr_ctr.atv_val = !(flags & OF_GPIO_ACTIVE_LOW);
ret = gpio_request(pwr_ctr->pwr_ctr.gpio,child->name);
if (ret) {
dev_err(dev_drv->dev, "request %s gpio fail:%d\n",
@@ -168,7 +168,41 @@ int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv)
return 0;
}
int rk_fb_video_mode_from_timing(const struct display_timing *dt,
struct rk_screen *screen)
{
screen->mode.pixclock = dt->pixelclock.typ;
screen->mode.left_margin = dt->hback_porch.typ;
screen->mode.right_margin = dt->hfront_porch.typ;
screen->mode.xres = dt->hactive.typ;
screen->mode.hsync_len = dt->hsync_len.typ;
screen->mode.upper_margin = dt->vback_porch.typ;
screen->mode.lower_margin = dt->vfront_porch.typ;
screen->mode.yres = dt->vactive.typ;
screen->mode.vsync_len = dt->vsync_len.typ;
screen->type = dt->screen_type;
screen->lvds_format = dt->lvds_format;
screen->face = dt->face;
if (dt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
screen->pin_dclk = 1;
else
screen->pin_dclk = 0;
if(dt->flags & DISPLAY_FLAGS_HSYNC_HIGH)
screen->pin_hsync = 1;
else
screen->pin_hsync = 0;
if(dt->flags & DISPLAY_FLAGS_VSYNC_HIGH)
screen->pin_vsync = 1;
else
screen->pin_vsync = 0;
if(dt->flags & DISPLAY_FLAGS_DE_HIGH)
screen->pin_den = 1;
else
screen->pin_den = 0;
return 0;
}
int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv)
{
struct display_timings *disp_timing;
@@ -180,16 +214,7 @@ int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv)
return -EINVAL;
}
dt = display_timings_get(disp_timing, 0);
screen->mode.pixclock = dt->pixelclock.typ;
screen->mode.left_margin = dt->hback_porch.typ;
screen->mode.right_margin = dt->hfront_porch.typ;
screen->mode.xres = dt->hactive.typ;
screen->mode.hsync_len = dt->hsync_len.typ;
screen->mode.upper_margin = dt->vback_porch.typ;
screen->mode.lower_margin = dt->vfront_porch.typ;
screen->mode.yres = dt->vactive.typ;
screen->mode.vsync_len = dt->vsync_len.typ;
rk_fb_video_mode_from_timing(dt, screen);
printk(KERN_DEBUG "dclk:%d\n"
"hactive:%d\n"
"hback_porch:%d\n"
@@ -358,10 +383,12 @@ static struct rk_lcdc_driver *rk_get_extend_lcdc_drv(void)
return dev_drv;
}
struct rk_screen *rk_fb_get_prmry_screen(void)
int rk_fb_get_prmry_screen(struct rk_screen *screen)
{
struct rk_lcdc_driver *dev_drv = rk_get_prmry_lcdc_drv();
return dev_drv->screen0;
memcpy(screen, dev_drv->screen0, sizeof(struct rk_screen));
return 0;
}

8
drivers/video/rockchip/transmitter/Kconfig
View File

@@ -26,11 +26,15 @@ config RK616_LVDS
config DP_ANX6345
bool "RGB to Display Port transmitter anx6345,anx9804,anx9805 support"
bool "RGB to DisplayPort transmitter anx6345,anx9804,anx9805 support"
depends on RK_TRSM
config DP501
bool"RGB to Display Port transmitter dp501 support"
bool"RGB to DisplayPort transmitter dp501 support"
depends on RK_TRSM
config RK32_DP
bool "RK32 RGB to DisplayPort transmitter support "
depends on RK_TRSM
config MIPI_DSI

21
drivers/video/rockchip/transmitter/Makefile
View File

@@ -1,14 +1,15 @@
#
# Makefile for display transmitter like lvds edp mipi
#
obj-$(CONFIG_RK2928_LVDS) += rk2928_lvds.o
obj-$(CONFIG_RK3026_LVDS) += rk3026_lvds.o
obj-$(CONFIG_RK610_LVDS) += rk610_lcd.o
obj-$(CONFIG_RK616_LVDS) += rk616_lvds.o
obj-$(CONFIG_DP_ANX6345) += dp_anx6345.o
obj-$(CONFIG_DP501) += dp501.o
obj-$(CONFIG_MIPI_DSI) += mipi_dsi.o
obj-$(CONFIG_RK616_MIPI_DSI) += rk616_mipi_dsi.o
obj-$(CONFIG_TC358768_RGB2MIPI) += tc358768.o
obj-$(CONFIG_SSD2828_RGB2MIPI) += ssd2828.o
obj-$(CONFIG_RK2928_LVDS) += rk2928_lvds.o
obj-$(CONFIG_RK3026_LVDS) += rk3026_lvds.o
obj-$(CONFIG_RK610_LVDS) += rk610_lcd.o
obj-$(CONFIG_RK616_LVDS) += rk616_lvds.o
obj-$(CONFIG_DP_ANX6345) += dp_anx6345.o
obj-$(CONFIG_DP501) += dp501.o
obj-$(CONFIG_RK32_DP) += rk32_dp.o rk32_dp_reg.o
obj-$(CONFIG_MIPI_DSI) += mipi_dsi.o
obj-$(CONFIG_RK616_MIPI_DSI) += rk616_mipi_dsi.o
obj-$(CONFIG_TC358768_RGB2MIPI) += tc358768.o
obj-$(CONFIG_SSD2828_RGB2MIPI) += ssd2828.o

27
include/linux/anx6345.h → drivers/video/rockchip/transmitter/anx6345.h Executable file → Normal file
View File

@@ -1,9 +1,8 @@
#ifndef __ANX6345_H_
#define __ANX6345_H_
#include<linux/rk_screen.h>
#include<linux/earlysuspend.h>
#include<linux/anx9805.h>
#include<linux/rk_fb.h>
#include "anx9805.h"
#define ANX6345_SCL_RATE (100*1000)
@@ -323,26 +322,26 @@
#define SP_TX_VID_CTRL3_REG 0x0A
#define SP_TX_VID_CTRL4_REG 0x0B
#define SP_TX_VID_CTRL4_REG 0x0B
#define SP_TX_VID_CTRL4_E_SYNC_EN 0x80 //bit position
#define SP_TX_VID_CTRL4_EX_E_SYNC 0x40 // bit position
#define SP_TX_VID_CTRL4_EX_E_SYNC 0x40 // bit position
#define SP_TX_VID_CTRL4_BIST 0x08 // bit position
#define SP_TX_VID_CTRL4_BIST_WIDTH 0x04 // bit position
#define SP_TX_VID_CTRL4_BIST_WIDTH 0x04 // bit position
#define SP_TX_VID_CTRL5_REG 0x0C
#define SP_TX_VID_CTRL6_REG 0x0D
#define SP_TX_VID_UPSAMPLE 0x02//bit position
#define SP_TX_VID_UPSAMPLE 0x02//bit position
#define SP_TX_VID_CTRL7_REG 0x0E
#define SP_TX_VID_CTRL8_REG 0x0F
#define SP_TX_VID_CTRL9_REG 0x10
#define SP_TX_VID_CTRL10_REG 0x11
#define SP_TX_VID_CTRL10_INV_F 0x08 // bit position
#define SP_TX_VID_CTRL10_I_SCAN 0x04 // bit position
#define SP_TX_VID_CTRL10_VSYNC_POL 0x02 // bit position
#define SP_TX_VID_CTRL10_HSYNC_POL 0x01 // bit position
#define SP_TX_VID_CTRL10_REG 0x11
#define SP_TX_VID_CTRL10_INV_F 0x08 // bit position
#define SP_TX_VID_CTRL10_I_SCAN 0x04 // bit position
#define SP_TX_VID_CTRL10_VSYNC_POL 0x02 // bit position
#define SP_TX_VID_CTRL10_HSYNC_POL 0x01 // bit position
#define SP_TX_TOTAL_LINEL_REG 0x12
#define SP_TX_TOTAL_LINEH_REG 0x13
@@ -687,13 +686,13 @@ struct anx6345_platform_data {
unsigned int dvdd18_en_pin;
int dvdd18_en_val;
unsigned int edp_rst_pin;
int (*power_ctl)(void);
int (*power_ctl)(struct anx6345_platform_data *pdata);
};
struct edp_anx6345 {
struct i2c_client *client;
struct anx6345_platform_data *pdata;
rk_screen screen;
struct rk_screen screen;
struct dentry *debugfs_dir;
#ifdef CONFIG_HAS_EARLYSUSPEND
struct early_suspend early_suspend;

2
include/linux/anx9805.h → drivers/video/rockchip/transmitter/anx9805.h Executable file → Normal file
View File

@@ -100,7 +100,7 @@ struct rk_edp_platform_data {
struct rk_edp {
struct i2c_client *client;
struct rk_edp_platform_data *pdata;
rk_screen screen;
struct rk_screen screen;
#ifdef CONFIG_HAS_EARLYSUSPEND
struct early_suspend early_suspend;
#endif

261
drivers/video/rockchip/transmitter/dp_anx6345.c
View File

@@ -5,8 +5,14 @@
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/anx6345.h>
#if defined(CONFIG_HAS_EARLYSUSPEND)
#include<linux/earlysuspend.h>
#endif
#if defined(CONFIG_OF)
#include <linux/of_gpio.h>
#endif
#include "anx6345.h"
#if defined(CONFIG_DEBUG_FS)
#include <linux/fs.h>
@@ -16,6 +22,54 @@
//#define BIST_MODE 0
static int i2c_master_reg8_send(const struct i2c_client *client,
const char reg, const char *buf, int count, int scl_rate)
{
struct i2c_adapter *adap=client->adapter;
struct i2c_msg msg;
int ret;
char *tx_buf = (char *)kmalloc(count + 1, GFP_KERNEL);
if(!tx_buf)
return -ENOMEM;
tx_buf[0] = reg;
memcpy(tx_buf+1, buf, count);
msg.addr = client->addr;
msg.flags = client->flags;
msg.len = count + 1;
msg.buf = (char *)tx_buf;
msg.scl_rate = scl_rate;
ret = i2c_transfer(adap, &msg, 1);
kfree(tx_buf);
return (ret == 1) ? count : ret;
}
static int i2c_master_reg8_recv(const struct i2c_client *client,
const char reg, char *buf, int count, int scl_rate)
{
struct i2c_adapter *adap=client->adapter;
struct i2c_msg msgs[2];
int ret;
char reg_buf = reg;
msgs[0].addr = client->addr;
msgs[0].flags = client->flags;
msgs[0].len = 1;
msgs[0].buf = &reg_buf;
msgs[0].scl_rate = scl_rate;
msgs[1].addr = client->addr;
msgs[1].flags = client->flags | I2C_M_RD;
msgs[1].len = count;
msgs[1].buf = (char *)buf;
msgs[1].scl_rate = scl_rate;
ret = i2c_transfer(adap, msgs, 2);
return (ret == 2)? count : ret;
}
static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
{
@@ -78,14 +132,13 @@ static int edp_reg_show(struct seq_file *s, void *v)
printk(KERN_ERR "no edp device!\n");
return 0;
}
seq_printf(s,"0x70:\n");
for(i=0;i< MAX_REG;i++)
{
anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
seq_printf(s,"0x%02x>>0x%02x\n",i,val);
}
seq_printf(s,"\n0x72:\n");
for(i=0;i< MAX_REG;i++)
@@ -571,53 +624,120 @@ static int anx980x_init(struct i2c_client *client)
return 0;
}
#if 1
static int anx6345_bist_mode(struct i2c_client *client)
{
struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
struct rk_screen *screen = &anx6345->screen;
u16 x_total ,y_total;
u32 total, act_total;
char val = 0x00;
//these register are for bist mode
val = 0x2c;
x_total = screen->mode.left_margin + screen->mode.right_margin +
screen->mode.xres + screen->mode.hsync_len;
y_total = screen->mode.upper_margin + screen->mode.lower_margin +
screen->mode.yres + screen->mode.vsync_len;
total = x_total * y_total;
printk("%s>>>>total:0x%08x\n",__func__, total);
act_total = screen->mode.xres * screen->mode.yres;
val = y_total & 0xff;
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
val = 0x06;
val = (y_total >> 8);
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
val = 0x00;
val = (screen->mode.yres & 0xff);
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
val = 0x06;
val = (screen->mode.yres >> 8);
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
val = 0x02;
val = screen->mode.lower_margin;
anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
val = 0x04;
val = screen->mode.vsync_len;
anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
val = 0x26;
val = screen->mode.upper_margin;
anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
val = total & 0xff;
val = 0x50;
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
val = total >> 8;
val = 0x04;
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
val = (act_total & 0xff);
val = 0x00;
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
val = (act_total >> 8);
val = 0x04;
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
val = 0x18;
val = screen->mode.right_margin & 0xff;
anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
val = 0x00;
val = screen->mode.right_margin >> 8;
anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
val = 0x10;
val = screen->mode.hsync_len & 0xff;
anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
val = 0x00;
val = screen->mode.hsync_len >> 8;
anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
val = 0x28;
val = screen->mode.left_margin & 0xff;
anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
val = screen->mode.left_margin >> 8;
anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHH_REG,&val);
val = 0x13;
anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
//enable BIST. In normal mode, don't need to config this reg
val = 0x08;
anx6345_i2c_write_p1_reg(client, 0x0b, &val);
anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL4_REG, &val);
printk("anx6345 enter bist mode\n");
return 0;
}
#else
static int anx6345_bist_mode(struct i2c_client *client)
{
char val = 0x00;
//these register are for bist mode
val = 0x2c;
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
val = 0x06;
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
val = 0x00;
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
val = 0x06;
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
val = 0x02;
anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
val = 0x04;
anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
val = 0x26;
anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
val = 0x50;
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
val = 0x04;
anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
val = 0x00;
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
val = 0x04;
anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
val = 0x18;
anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
val = 0x00;
anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
val = 0x10;
anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
val = 0x00;
anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
val = 0x28;
anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
val = 0x13;
anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
//enable BIST. In normal mode, don't need to config this reg
val = 0x08;
anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL4_REG, &val);
printk("anx6345 enter bist mode\n");
return 0;
}
#endif
static int anx6345_init(struct i2c_client *client)
{
char val = 0x00;
@@ -758,31 +878,98 @@ static void anx6345_late_resume(struct early_suspend *h)
}
#endif
#if defined(CONFIG_OF)
static int anx6345_power_ctl(struct anx6345_platform_data *pdata)
{
int ret;
ret = gpio_request(pdata->dvdd33_en_pin, "dvdd33_en_pin");
if (ret != 0) {
gpio_free(pdata->dvdd33_en_pin);
printk(KERN_ERR "request dvdd33 en pin fail!\n");
return -1;
} else {
gpio_direction_output(pdata->dvdd33_en_pin, pdata->dvdd33_en_val);
}
mdelay(5);
ret = gpio_request(pdata->dvdd18_en_pin, "dvdd18_en_pin");
if (ret != 0) {
gpio_free(pdata->dvdd18_en_pin);
printk(KERN_ERR "request dvdd18 en pin fail!\n");
return -1;
} else {
gpio_direction_output(pdata->dvdd18_en_pin, pdata->dvdd18_en_pin);
}
ret = gpio_request(pdata->edp_rst_pin, "edp_rst_pin");
if (ret != 0) {
gpio_free(pdata->edp_rst_pin);
printk(KERN_ERR "request rst pin fail!\n");
return -1;
} else {
gpio_direction_output(pdata->edp_rst_pin, 0);
msleep(50);
gpio_direction_output(pdata->edp_rst_pin, 1);
}
return 0;
}
static void anx6345_parse_dt(struct edp_anx6345 *anx6345)
{
struct device_node *np = anx6345->client->dev.of_node;
struct anx6345_platform_data *pdata;
enum of_gpio_flags dvdd33_flags,dvdd18_flags,rst_flags;
pdata = devm_kzalloc(&anx6345->client->dev,
sizeof(struct anx6345_platform_data ), GFP_KERNEL);
if (!pdata) {
dev_err(&anx6345->client->dev,
"failed to allocate platform data\n");
return ;
}
pdata->dvdd33_en_pin = of_get_named_gpio_flags(np, "dvdd33-gpio", 0, &dvdd33_flags);
pdata->dvdd18_en_pin = of_get_named_gpio_flags(np, "dvdd18-gpio", 0, &dvdd18_flags);
pdata->edp_rst_pin = of_get_named_gpio_flags(np, "reset-gpio", 0, &rst_flags);
pdata->dvdd33_en_val = (dvdd33_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
pdata->dvdd18_en_val = (dvdd18_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
pdata->power_ctl = anx6345_power_ctl;
anx6345->pdata = pdata;
}
#else
static void anx6345_parse_dt(struct edp_anx6345 * anx6345)
{
}
#endif
static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
{
int ret;
struct edp_anx6345 *anx6345 = NULL;
struct edp_anx6345 *anx6345;
int chip_id;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
{
dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
ret = -ENODEV;
return -ENODEV;
}
anx6345 = kzalloc(sizeof(struct edp_anx6345), GFP_KERNEL);
if (anx6345 == NULL)
{
printk(KERN_ALERT "alloc for struct anx6345 fail\n");
ret = -ENOMEM;
anx6345 = devm_kzalloc(&client->dev, sizeof(struct edp_anx6345),
GFP_KERNEL);
if (unlikely(!anx6345)) {
dev_err(&client->dev, "alloc for struct anx6345 fail\n");
return -ENOMEM;
}
anx6345->client = client;
anx6345->pdata = client->dev.platform_data;
anx6345->pdata = dev_get_platdata(&client->dev);
if (!anx6345->pdata) {
anx6345_parse_dt(anx6345);
}
i2c_set_clientdata(client,anx6345);
rk_fb_get_prmry_screen(&anx6345->screen);
if(anx6345->pdata->power_ctl)
anx6345->pdata->power_ctl();
anx6345->pdata->power_ctl(anx6345->pdata);
#if defined(CONFIG_DEBUG_FS)
anx6345->debugfs_dir = debugfs_create_dir("edp", NULL);
@@ -808,12 +995,12 @@ static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_i
anx6345->edp_anx_init(client);
printk("edp anx%x probe ok\n",get_dp_chip_id(client));
return ret;
dev_info(&client->dev, "edp anx%x probe ok \n", get_dp_chip_id(client));
return 0;
}
static int __devexit anx6345_i2c_remove(struct i2c_client *client)
static int anx6345_i2c_remove(struct i2c_client *client)
{
return 0;
}
@@ -823,10 +1010,20 @@ static const struct i2c_device_id id_table[] = {
{ }
};
#if defined(CONFIG_OF)
static struct of_device_id anx6345_dt_ids[] = {
{ .compatible = "analogix, anx6345" },
{ }
};
#endif
static struct i2c_driver anx6345_i2c_driver = {
.driver = {
.name = "anx6345",
.owner = THIS_MODULE,
#if defined(CONFIG_OF)
.of_match_table = of_match_ptr(anx6345_dt_ids),
#endif
},
.probe = &anx6345_i2c_probe,
.remove = &anx6345_i2c_remove,

1227
drivers/video/rockchip/transmitter/rk32_dp.c Normal file
View File

File diff suppressed because it is too large Load Diff

649
drivers/video/rockchip/transmitter/rk32_dp.h Normal file
View File

@@ -0,0 +1,649 @@
#ifndef __RK32_DP_H
#define __RK32_DP_H
#define DP_VERSION 0x10
#define TX_SW_RST 0x14
#define FUNC_EN_1 0x18
#define VID_CAP_FUNC_EN_N (0x1 << 6)
#define VID_FIFO_FUNC_EN_N (0x1 << 5)
#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
#define AUD_FUNC_EN_N (0x1 << 3)
#define HDCP_FUNC_EN_N (0x1 << 2)
#define SW_FUNC_EN_N (0x1 << 0)
#define FUNC_EN_2 0x1C
#define SSC_FUNC_EN_N (0x1 << 7)
#define AUX_FUNC_EN_N (0x1 << 2)
#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
#define VIDEO_CTL_1 0x20
#define VIDEO_EN (0x1 << 7)
#define VIDEO_MUTE (0x1 << 6)
#define VIDEO_CTL_2 0x24
#define IN_D_RANGE_MASK (0x1 << 7)
#define IN_D_RANGE_SHIFT (7)
#define IN_D_RANGE_CEA (0x1 << 7)
#define IN_D_RANGE_VESA (0x0 << 7)
#define IN_BPC_MASK (0x7 << 4)
#define IN_BPC_SHIFT (4)
#define IN_BPC_12_BITS (0x3 << 4)
#define IN_BPC_10_BITS (0x2 << 4)
#define IN_BPC_8_BITS (0x1 << 4)
#define IN_BPC_6_BITS (0x0 << 4)
#define IN_COLOR_F_MASK (0x3 << 0)
#define IN_COLOR_F_SHIFT (0)
#define IN_COLOR_F_YCBCR444 (0x2 << 0)
#define IN_COLOR_F_YCBCR422 (0x1 << 0)
#define IN_COLOR_F_RGB (0x0 << 0)
#define VIDEO_CTL_3 0x28
#define IN_YC_COEFFI_MASK (0x1 << 7)
#define IN_YC_COEFFI_SHIFT (7)
#define IN_YC_COEFFI_ITU709 (0x1 << 7)
#define IN_YC_COEFFI_ITU601 (0x0 << 7)
#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
#define VID_CHK_UPDATE_TYPE_SHIFT (4)
#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
#define VIDEO_CTL_4 0x2c
#define BIST_EN (0x1 << 3)
#define BIST_WH_64 (0x1 << 2)
#define BIST_WH_32 (0x0 << 2)
#define BIST_TYPE_COLR_BAR (0x0 << 0)
#define BIST_TYPE_GRAY_BAR (0x1 << 0)
#define BIST_TYPE_MOBILE_BAR (0x2 << 0)
#define VIDEO_CTL_8 0x3C
#define VID_HRES_TH(x) (((x) & 0xf) << 4)
#define VID_VRES_TH(x) (((x) & 0xf) << 0)
#define VIDEO_CTL_10 0x44
#define F_SEL (0x1 << 4)
#define INTERACE_SCAN_CFG (0x1 << 2)
#define VSYNC_POLARITY_CFG (0x1 << 1)
#define HSYNC_POLARITY_CFG (0x1 << 0)
#define PLL_REG_1 0xfc
#define REF_CLK_24M (0x01 << 1)
#define REF_CLK_27M (0x0 << 1)
#define DP_PWRDN 0x12c
#define PD_INC_BG (0x1 << 7)
#define PD_EXP_BG (0x1 << 6)
#define PD_AUX (0x1 << 5)
#define PD_PLL (0x1 << 4)
#define PD_CH3 (0x1 << 3)
#define PD_CH2 (0x1 << 2)
#define PD_CH1 (0x1 << 1)
#define PD_CH0 (0x1 << 0)
#define LANE_MAP 0x35C
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
#define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6)
#define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4)
#define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
#define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
#define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4)
#define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2)
#define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
#define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
#define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2)
#define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0)
#define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
#define ANALOG_CTL_2 0x374
#define SEL_24M (0x1 << 3)
/*#define ANALOG_CTL_3 0x378
#define PLL_FILTER_CTL_1 0x37C
#define TX_AMP_TUNING_CTL 0x380*/
#define AUX_HW_RETRY_CTL 0x390
#define INT_STA 0x3c0
#define COMMON_INT_STA_1 0x3C4
#define VSYNC_DET (0x1 << 7)
#define PLL_LOCK_CHG (0x1 << 6)
#define SPDIF_ERR (0x1 << 5)
#define SPDIF_UNSTBL (0x1 << 4)
#define VID_FORMAT_CHG (0x1 << 3)
#define AUD_CLK_CHG (0x1 << 2)
#define VID_CLK_CHG (0x1 << 1)
#define SW_INT (0x1 << 0)
#define COMMON_INT_STA_2 0x3C8
#define ENC_EN_CHG (0x1 << 6)
#define HW_BKSV_RDY (0x1 << 3)
#define HW_SHA_DONE (0x1 << 2)
#define HW_AUTH_STATE_CHG (0x1 << 1)
#define HW_AUTH_DONE (0x1 << 0)
#define COMMON_INT_STA_3 0x3CC
#define AFIFO_UNDER (0x1 << 7)
#define AFIFO_OVER (0x1 << 6)
#define R0_CHK_FLAG (0x1 << 5)
#define COMMON_INT_STA_4 0x3D0
#define PSR_ACTIVE (0x1 << 7)
#define PSR_INACTIVE (0x1 << 6)
#define SPDIF_BI_PHASE_ERR (0x1 << 5)
#define HOTPLUG_CHG (0x1 << 2)
#define HPD_LOST (0x1 << 1)
#define PLUG (0x1 << 0)
#define DP_INT_STA 0x3DC
#define INT_HPD (0x1 << 6)
#define HW_LT_DONE (0x1 << 5)
#define SINK_LOST (0x1 << 3)
#define LINK_LOST (0x1 << 2)
#define RPLY_RECEIV (0x1 << 1)
#define AUX_ERR (0x1 << 0)
#define COMMON_INT_MASK_1 0x3E0
#define COMMON_INT_MASK_2 0x3E4
#define COMMON_INT_MASK_3 0x3E8
#define COMMON_INT_MASK_4 0x3EC
#define DP_INT_STA_MASK 0x3F8
#define INT_CTL 0x3FC
#define SOFT_INT_CTRL (0x1 << 2)
#define INT_POL (0x1 << 0)
#define SYS_CTL_1 0x600
#define DET_STA (0x1 << 2)
#define FORCE_DET (0x1 << 1)
#define DET_CTRL (0x1 << 0)
#define SYS_CTL_2 0x604
#define CHA_CRI(x) (((x) & 0xf) << 4)
#define CHA_STA (0x1 << 2)
#define FORCE_CHA (0x1 << 1)
#define CHA_CTRL (0x1 << 0)
#define SYS_CTL_3 0x608
#define HPD_STATUS (0x1 << 6)
#define F_HPD (0x1 << 5)
#define HPD_CTRL (0x1 << 4)
#define HDCP_RDY (0x1 << 3)
#define STRM_VALID (0x1 << 2)
#define F_VALID (0x1 << 1)
#define VALID_CTRL (0x1 << 0)
#define SYS_CTL_4 0x60C
#define FIX_M_AUD (0x1 << 4)
#define ENHANCED (0x1 << 3)
#define FIX_M_VID (0x1 << 2)
#define M_VID_UPDATE_CTRL (0x3 << 0)
#define PKT_SEND_CTL 0x640
#define HDCP_CTL 0x648
#define LINK_BW_SET 0x680
#define LANE_CNT_SET 0x684
#define TRAINING_PTN_SET 0x688
#define SCRAMBLING_DISABLE (0x1 << 5)
#define SCRAMBLING_ENABLE (0x0 << 5)
#define LINK_QUAL_PATTERN_SET_MASK (0x7 << 2)
#define LINK_QUAL_PATTERN_SET_HBR2 (0x5 << 2)
#define LINK_QUAL_PATTERN_SET_80BIT (0x4 << 2)
#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
#define SW_TRAINING_PATTERN_SET_DISABLE (0x0 << 0)
#define LN0_LINK_TRAINING_CTL 0x68C
#define LN1_LINK_TRAINING_CTL 0x690
#define LN2_LINK_TRAINING_CTL 0x694
#define LN3_LINK_TRAINING_CTL 0x698
#define HW_LT_CTL 0x6a0
#define HW_LT_EN (0x1 << 0)
#define DEBUG_CTL 0x6C0
#define PLL_LOCK (0x1 << 4)
#define F_PLL_LOCK (0x1 << 3)
#define PLL_LOCK_CTRL (0x1 << 2)
#define POLL_EN (0x1 << 1)
#define PN_INV (0x1 << 0)
#define HPD_DEGLITCH_L 0x6C4
#define HPD_DEGLITCH_H 0x6C8
#define LINK_DEBUG_CTL 0x6E0
#define M_VID_0 0x700
#define M_VID_1 0x704
#define M_VID_2 0x708
#define N_VID_0 0x70C
#define N_VID_1 0x710
#define N_VID_2 0x714
#define VIDEO_FIFO_THRD 0x730
#define AUDIO_MARGIN 0x73C
#define M_VID_GEN_FILTER_TH 0x764
#define M_AUD_GEN_FILTER_TH 0x778
#define AUX_CH_STA 0x780
#define AUX_BUSY (0x1 << 4)
#define AUX_STATUS_MASK (0xf << 0)
#define AUX_CH_DEFER_CTL 0x788
#define DEFER_CTRL_EN (0x1 << 7)
#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
#define AUX_RX_COMM 0x78C
#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
#define BUFFER_DATA_CTL 0x790
#define BUF_CLR (0x1 << 7)
#define BUF_HAVE_DATA (0x1 << 4)
#define BUF_DATA_COUNT(x) (((x) & 0xf) << 0)
#define AUX_CH_CTL_1 0x794
#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
#define AUX_TX_COMM_MASK (0xf << 0)
#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
#define AUX_TX_COMM_MOT (0x1 << 2)
#define AUX_TX_COMM_WRITE (0x0 << 0)
#define AUX_TX_COMM_READ (0x1 << 0)
#define DP_AUX_ADDR_7_0 0x798
#define DP_AUX_ADDR_15_8 0x79C
#define DP_AUX_ADDR_19_16 0x7A0
#define AUX_CH_CTL_2 0x7A4
#define PD_AUX_IDLE (0x1 << 3)
#define ADDR_ONLY (0x1 << 1)
#define AUX_EN (0x1 << 0)
#define BUF_DATA_0 0x7C0
#define SOC_GENERAL_CTL 0x800
/* TX_SW_RESET */
#define RST_DP_TX (0x1 << 0)
/* ANALOG_CTL_1 */
#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4)
/* ANALOG_CTL_3 */
#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
#define VCO_BIT_600_MICRO (0x5 << 0)
/* PLL_FILTER_CTL_1 */
#define PD_RING_OSC (0x1 << 6)
#define AUX_TERMINAL_CTRL_37_5_OHM (0x0 << 4)
#define AUX_TERMINAL_CTRL_45_OHM (0x1 << 4)
#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
#define AUX_TERMINAL_CTRL_65_OHM (0x3 << 4)
#define TX_CUR1_2X (0x1 << 2)
#define TX_CUR_16_MA (0x3 << 0)
/* TX_AMP_TUNING_CTL */
#define CH3_AMP_SHIFT (24)
#define CH3_AMP_400_MV (0x0 << 24)
#define CH2_AMP_SHIFT (16)
#define CH2_AMP_400_MV (0x0 << 16)
#define CH1_AMP_SHIFT (8)
#define CH1_AMP_400_MV (0x0 << 8)
#define CH0_AMP_SHIFT (0)
#define CH0_AMP_400_MV (0x0 << 0)
/* AUX_HW_RETRY_CTL */
#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
/* LN0_LINK_TRAINING_CTL */
#define PRE_EMPHASIS_SET_MASK (0x3 << 3)
#define PRE_EMPHASIS_SET_SHIFT (3)
/* PLL_CTL */
#define DP_PLL_PD (0x1 << 7)
#define DP_PLL_RESET (0x1 << 6)
#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
/* PHY_TEST */
#define MACRO_RST (0x1 << 5)
#define CH1_TEST (0x1 << 1)
#define CH0_TEST (0x1 << 0)
/* AUX_ADDR_7_0 */
#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
/* AUX_ADDR_15_8 */
#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
/* AUX_ADDR_19_16 */
#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
/* I2C EDID Chip ID, Slave Address */
#define I2C_EDID_DEVICE_ADDR 0x50
#define I2C_E_EDID_DEVICE_ADDR 0x30
#define EDID_BLOCK_LENGTH 0x80
#define EDID_HEADER_PATTERN 0x00
#define EDID_EXTENSION_FLAG 0x7e
#define EDID_CHECKSUM 0x7f
/* Definition for DPCD Register */
#define DPCD_ADDR_DPCD_REV 0x0000
#define DPCD_ADDR_MAX_LINK_RATE 0x0001
#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
#define DPCD_ADDR_LINK_BW_SET 0x0100
#define DPCD_ADDR_LANE_COUNT_SET 0x0101
#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
#define DPCD_ADDR_LANE0_1_STATUS 0x0202
#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
#define DPCD_ADDR_TEST_REQUEST 0x0218
#define DPCD_ADDR_TEST_RESPONSE 0x0260
#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
#define DPCD_ADDR_SINK_POWER_STATE 0x0600
/* DPCD_ADDR_MAX_LANE_COUNT */
#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
/* DPCD_ADDR_LANE_COUNT_SET */
#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
/* DPCD_ADDR_TRAINING_PATTERN_SET */
#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
/* DPCD_ADDR_TRAINING_LANE0_SET */
#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
#define DPCD_MAX_SWING_REACHED (0x1 << 2)
#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
/* DPCD_ADDR_LANE0_1_STATUS */
#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
#define DPCD_LANE_CR_DONE (0x1 << 0)
#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
DPCD_LANE_CHANNEL_EQ_DONE|\
DPCD_LANE_SYMBOL_LOCKED)
/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
/* DPCD_ADDR_TEST_REQUEST */
#define DPCD_TEST_EDID_READ (0x1 << 2)
/* DPCD_ADDR_TEST_RESPONSE */
#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
/* DPCD_ADDR_SINK_POWER_STATE */
#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
#define DP_TIMEOUT_LOOP_CNT 100
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
#define REF_CLK_FROM_INTER (1 << 4)
enum color_coefficient {
COLOR_YCBCR601,
COLOR_YCBCR709
};
enum dynamic_range {
VESA,
CEA
};
enum pll_status {
DP_PLL_UNLOCKED,
DP_PLL_LOCKED
};
enum clock_recovery_m_value_type {
CALCULATED_M,
REGISTER_M
};
enum video_timing_recognition_type {
VIDEO_TIMING_FROM_CAPTURE,
VIDEO_TIMING_FROM_REGISTER
};
enum pattern_set {
PRBS7,
D10_2,
TRAINING_PTN1,
TRAINING_PTN2,
DP_NONE
};
enum color_space {
CS_RGB,
CS_YCBCR422,
CS_YCBCR444
};
enum color_depth {
COLOR_6,
COLOR_8,
COLOR_10,
COLOR_12
};
enum link_rate_type {
LINK_RATE_1_62GBPS = 0x06,
LINK_RATE_2_70GBPS = 0x0a
};
enum link_lane_count_type {
LANE_CNT1 = 1,
LANE_CNT2 = 2,
LANE_CNT4 = 4
};
enum link_training_state {
LT_START,
LT_CLK_RECOVERY,
LT_EQ_TRAINING,
FINISHED,
FAILED
};
enum voltage_swing_level {
VOLTAGE_LEVEL_0,
VOLTAGE_LEVEL_1,
VOLTAGE_LEVEL_2,
VOLTAGE_LEVEL_3,
};
enum pre_emphasis_level {
PRE_EMPHASIS_LEVEL_0,
PRE_EMPHASIS_LEVEL_1,
PRE_EMPHASIS_LEVEL_2,
PRE_EMPHASIS_LEVEL_3,
};
enum analog_power_block {
AUX_BLOCK,
CH0_BLOCK,
CH1_BLOCK,
CH2_BLOCK,
CH3_BLOCK,
ANALOG_TOTAL,
POWER_ALL
};
struct video_info {
char *name;
bool h_sync_polarity;
bool v_sync_polarity;
bool interlaced;
enum color_space color_space;
enum dynamic_range dynamic_range;
enum color_coefficient ycbcr_coeff;
enum color_depth color_depth;
enum link_rate_type link_rate;
enum link_lane_count_type lane_count;
};
struct link_train {
int eq_loop;
int cr_loop[4];
u8 link_rate;
u8 lane_count;
u8 training_lane[4];
enum link_training_state lt_state;
};
struct rk32_edp {
struct device *dev;
void __iomem *regs;
struct clk *clk_edp;
struct clk *clk_24m;
struct link_train link_train;
struct video_info video_info;
int enabled;
};
void rk32_edp_enable_video_mute(struct rk32_edp *edp, bool enable);
void rk32_edp_stop_video(struct rk32_edp *edp);
void rk32_edp_lane_swap(struct rk32_edp *edp, bool enable);
void rk32_edp_init_analog_param(struct rk32_edp *edp);
void rk32_edp_init_interrupt(struct rk32_edp *edp);
void rk32_edp_reset(struct rk32_edp *edp);
void rk32_edp_config_interrupt(struct rk32_edp *edp);
u32 rk32_edp_get_pll_lock_status(struct rk32_edp *edp);
void rk32_edp_analog_power_ctr(struct rk32_edp *edp, bool enable);
void rk32_edp_init_analog_func(struct rk32_edp *edp);
void rk32_edp_init_hpd(struct rk32_edp *edp);
void rk32_edp_reset_aux(struct rk32_edp *edp);
void rk32_edp_init_aux(struct rk32_edp *edp);
int rk32_edp_get_plug_in_status(struct rk32_edp *edp);
void rk32_edp_enable_sw_function(struct rk32_edp *edp);
int rk32_edp_start_aux_transaction(struct rk32_edp *edp);
int rk32_edp_write_byte_to_dpcd(struct rk32_edp *edp,
unsigned int reg_addr,
unsigned char data);
int rk32_edp_read_byte_from_dpcd(struct rk32_edp *edp,
unsigned int reg_addr,
unsigned char *data);
int rk32_edp_write_bytes_to_dpcd(struct rk32_edp *edp,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int rk32_edp_read_bytes_from_dpcd(struct rk32_edp *edp,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int rk32_edp_select_i2c_device(struct rk32_edp *edp,
unsigned int device_addr,
unsigned int reg_addr);
int rk32_edp_read_byte_from_i2c(struct rk32_edp *edp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int *data);
int rk32_edp_read_bytes_from_i2c(struct rk32_edp *edp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int count,
unsigned char edid[]);
void rk32_edp_set_link_bandwidth(struct rk32_edp *edp, u32 bwtype);
void rk32_edp_get_link_bandwidth(struct rk32_edp *edp, u32 *bwtype);
void rk32_edp_set_lane_count(struct rk32_edp *edp, u32 count);
void rk32_edp_get_lane_count(struct rk32_edp *edp, u32 *count);
void rk32_edp_enable_enhanced_mode(struct rk32_edp *edp, bool enable);
void rk32_edp_set_training_pattern(struct rk32_edp *edp,
enum pattern_set pattern);
void rk32_edp_set_lane0_pre_emphasis(struct rk32_edp *edp, u32 level);
void rk32_edp_set_lane1_pre_emphasis(struct rk32_edp *edp, u32 level);
void rk32_edp_set_lane2_pre_emphasis(struct rk32_edp *edp, u32 level);
void rk32_edp_set_lane3_pre_emphasis(struct rk32_edp *edp, u32 level);
void rk32_edp_set_lane0_link_training(struct rk32_edp *edp,
u32 training_lane);
void rk32_edp_set_lane1_link_training(struct rk32_edp *edp,
u32 training_lane);
void rk32_edp_set_lane2_link_training(struct rk32_edp *edp,
u32 training_lane);
void rk32_edp_set_lane3_link_training(struct rk32_edp *edp,
u32 training_lane);
u32 rk32_edp_get_lane0_link_training(struct rk32_edp *edp);
u32 rk32_edp_get_lane1_link_training(struct rk32_edp *edp);
u32 rk32_edp_get_lane2_link_training(struct rk32_edp *edp);
u32 rk32_edp_get_lane3_link_training(struct rk32_edp *edp);
void rk32_edp_reset_macro(struct rk32_edp *edp);
int rk32_edp_init_video(struct rk32_edp *edp);
void rk32_edp_set_video_color_format(struct rk32_edp *edp,
u32 color_depth,
u32 color_space,
u32 dynamic_range,
u32 coeff);
int rk32_edp_is_slave_video_stream_clock_on(struct rk32_edp *edp);
void rk32_edp_set_video_cr_mn(struct rk32_edp *edp,
enum clock_recovery_m_value_type type,
u32 m_value,
u32 n_value);
void rk32_edp_set_video_timing_mode(struct rk32_edp *edp, u32 type);
void rk32_edp_enable_video_master(struct rk32_edp *edp, bool enable);
void rk32_edp_start_video(struct rk32_edp *edp);
int rk32_edp_is_video_stream_on(struct rk32_edp *edp);
void rk32_edp_config_video_slave_mode(struct rk32_edp *edp,
struct video_info *video_info);
void rk32_edp_enable_scrambling(struct rk32_edp *edp);
void rk32_edp_disable_scrambling(struct rk32_edp *edp);
void rk32_edp_rx_control(struct rk32_edp *edp, bool enable);
#endif

1156
drivers/video/rockchip/transmitter/rk32_dp_reg.c Normal file
View File

File diff suppressed because it is too large Load Diff

64
include/dt-bindings/rkfb/rk_fb.h
View File

@@ -10,4 +10,68 @@
#define ONE_DUAL 1
#define DUAL 2
#define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
#define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
#define OUT_P565 2
#define OUT_S888x 4
#define OUT_CCIR656 6
#define OUT_S888 8
#define OUT_S888DUMY 12
#define OUT_P16BPP4 24
#define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
#define OUT_D888_P565 0x22
#define SCREEN_NULL 0
#define SCREEN_RGB 1
#define SCREEN_LVDS 2
#define SCREEN_DUAL_LVDS 3
#define SCREEN_MCU 4
#define SCREEN_TVOUT 5
#define SCREEN_HDMI 6
#define SCREEN_MIPI 7
#define SCREEN_DUAL_MIPI 8
#define SCREEN_EDP 9
#define LVDS_8BIT_1 0
#define LVDS_8BIT_2 1
#define LVDS_8BIT_3 2
#define LVDS_6BIT 3
/* lvds connect config
*
* LVDS_8BIT_1 LVDS_8BIT_2 LVDS_8BIT_3 LVDS_6BIT
----------------------------------------------------------------------
TX0 R0 R2 R2 R0
TX1 R1 R3 R3 R1
TX2 R2 R4 R4 R2
Y TX3 R3 R5 R5 R3
0 TX4 R4 R6 R6 R4
TX6 R5 R7 R7 R5
TX7 G0 G2 G2 G0
----------------------------------------------------------------------
TX8 G1 G3 G3 G1
TX9 G2 G4 G4 G2
Y TX12 G3 G5 G5 G3
1 TX13 G4 G6 G6 G4
TX14 G5 G7 G7 G5
TX15 B0 B2 B2 B0
TX18 B1 B3 B3 B1
----------------------------------------------------------------------
TX19 B2 B4 B4 B2
TX20 B3 B5 B5 B3
TX21 B4 B6 B6 B4
Y TX22 B5 B7 B7 B5
2 TX24 HSYNC HSYNC HSYNC HSYNC
TX25 VSYNC VSYNC VSYNC VSYNC
TX26 ENABLE ENABLE ENABLE ENABLE
----------------------------------------------------------------------
TX27 R6 R0 GND GND
TX5 R7 R1 GND GND
TX10 G6 G0 GND GND
Y TX11 G7 G1 GND GND
3 TX16 B6 B0 GND GND
TX17 B7 B1 GND GND
TX23 RSVD RSVD RSVD RSVD
----------------------------------------------------------------------
*/
#endif

2
include/linux/rk_fb.h
View File

@@ -354,7 +354,7 @@ extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
struct rk_lcdc_win *win, int id);
extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
extern struct rk_screen *rk_fb_get_prmry_screen(void);
extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
extern u32 rk_fb_get_prmry_screen_pixclock(void);
extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);

52
include/linux/rk_screen.h
View File

@@ -1,58 +1,6 @@
#ifndef _SCREEN_H
#define _SCREEN_H
#define LVDS_8BIT_1 0
#define LVDS_8BIT_2 1
#define LVDS_8BIT_3 2
#define LVDS_6BIT 3
/* lvds connect config
*
* LVDS_8BIT_1 LVDS_8BIT_2 LVDS_8BIT_3 LVDS_6BIT
----------------------------------------------------------------------
TX0 R0 R2 R2 R0
TX1 R1 R3 R3 R1
TX2 R2 R4 R4 R2
Y TX3 R3 R5 R5 R3
0 TX4 R4 R6 R6 R4
TX6 R5 R7 R7 R5
TX7 G0 G2 G2 G0
----------------------------------------------------------------------
TX8 G1 G3 G3 G1
TX9 G2 G4 G4 G2
Y TX12 G3 G5 G5 G3
1 TX13 G4 G6 G6 G4
TX14 G5 G7 G7 G5
TX15 B0 B2 B2 B0
TX18 B1 B3 B3 B1
----------------------------------------------------------------------
TX19 B2 B4 B4 B2
TX20 B3 B5 B5 B3
TX21 B4 B6 B6 B4
Y TX22 B5 B7 B7 B5
2 TX24 HSYNC HSYNC HSYNC HSYNC
TX25 VSYNC VSYNC VSYNC VSYNC
TX26 ENABLE ENABLE ENABLE ENABLE
----------------------------------------------------------------------
TX27 R6 R0 GND GND
TX5 R7 R1 GND GND
TX10 G6 G0 GND GND
Y TX11 G7 G1 GND GND
3 TX16 B6 B0 GND GND
TX17 B7 B1 GND GND
TX23 RSVD RSVD RSVD RSVD
----------------------------------------------------------------------
*/
typedef enum _SCREEN_TYPE {
SCREEN_NULL = 0,
SCREEN_RGB,
SCREEN_LVDS,
SCREEN_MCU,
SCREEN_TVOUT,
SCREEN_HDMI,
SCREEN_MIPI,
} SCREEN_TYPE;
typedef enum _REFRESH_STAGE {
REFRESH_PRE = 0,
REFRESH_END,

10
include/video/display_timing.h
View File

@@ -27,6 +27,11 @@ enum display_flags {
DISPLAY_FLAGS_PIXDATA_NEGEDGE = BIT(7),
DISPLAY_FLAGS_INTERLACED = BIT(8),
DISPLAY_FLAGS_DOUBLESCAN = BIT(9),
#if defined(CONFIG_FB_ROCKCHIP)
DISPLAY_FLAGS_SWAP_GB = BIT(10),
DISPLAY_FLAGS_SWAP_RG = BIT(11),
DISPLAY_FLAGS_SWAP_RB = BIT(12),
#endif
};
/*
@@ -70,6 +75,11 @@ struct display_timing {
struct timing_entry vsync_len; /* ver. sync len */
enum display_flags flags; /* display flags */
#if defined(CONFIG_FB_ROCKCHIP)
u16 screen_type; /*screen type*/
u16 lvds_format; /*lvds data format for lvds screen*/
u16 face; /*display output interface format:24bit 18bit 16bit*/
#endif
};
/*