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clk: rockchip: rv1126: Change parent clock for hclk and pclk pdbus

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As dmac aclk comes from hclk pdbus, dmac pclk comes frome pclk pdbus,
dmac aclk should be an integer multiple of dmac pclk and the same
parent with dmac pclk. so let hclk pdbus and pclk pdbus only come from gpll.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia75c3613573f4a6818cbc18668a66736f011c695
This commit is contained in:
Finley Xiao
2020-06-02 09:54:36 +08:00
committed by Tao Huang
parent 9713c36a41
commit 5dedb0163a
1 changed files with 3 additions and 2 deletions
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5
drivers/clk/rockchip/clk-rv1126.c
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@@ -154,6 +154,7 @@ PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
@@ -479,12 +480,12 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
RV1126_CLKGATE_CON(2), 0, GFLAGS),
GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE(0, "hclk_pdbus_pre", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1126_CLKGATE_CON(2), 1, GFLAGS),
GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE(0, "pclk_pdbus_pre", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(2), 2, GFLAGS),
GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,