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di: di post wr&vpp link disaply ok

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PD#156734: di:
1) fix 0x1a0a error config in video.c
2) update gate control for if0

Change-Id: I6f1a7080b1f6f2d343ed3773ef55b2834d55d0d6
Signed-off-by: kele bai <kele.bai@amlogic.com>
This commit is contained in:
kele bai
2018-02-04 16:27:20 +08:00
committed by Yixun Lan
parent 829ddebafe
commit 5df5e48668
3 changed files with 43 additions and 17 deletions
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12
drivers/amlogic/media/deinterlace/deinterlace.c
View File

@@ -5616,13 +5616,14 @@ static void di_unreg_process_irq(void)
di_uninit_buf(mirror_disable);
init_flag = 0;
#ifdef CONFIG_AMLOGIC_MEDIA_RDMA
/* stop rdma */
rdma_clear(de_devp->rdma_handle);
if (di_pre_rdma_enable)
rdma_clear(de_devp->rdma_handle);
#endif
adpative_combing_exit();
enable_di_pre_mif(false, mcpre_en);
di_hw_uninit();
if (is_meson_txlx_cpu() || is_meson_txhd_cpu())
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()
|| is_meson_g12a_cpu())
di_pre_gate_control(false, mcpre_en);
else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) {
DI_Wr(DI_CLKG_CTRL, 0x80f60000);
@@ -5632,7 +5633,8 @@ static void di_unreg_process_irq(void)
/* nr/blend0/ei0/mtn0 clock gate */
if (mirror_disable) {
di_hw_disable(mcpre_en);
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) {
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()
|| is_meson_g12a_cpu()) {
enable_di_post_mif(GATE_OFF);
di_post_gate_control(false);
di_top_gate_control(false, false);
@@ -5770,7 +5772,7 @@ static void di_pre_size_change(unsigned short width,
nr_ds_init(width, height);
if (de_devp->pps_enable && pps_position) {
pps_w = di_pre_stru.cur_width;
pps_h = di_pre_stru.cur_height>>(vf_type?1:0);
pps_h = di_pre_stru.cur_height>>1;
di_pps_config(1, pps_w, pps_h, pps_dstw, (pps_dsth>>1));
}
}

35
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

@@ -2098,7 +2098,6 @@ void initial_di_post_2(int hsize_post, int vsize_post,
DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
0, 8, 9);
} else {
DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0x00200005);
DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
1, 20, 1);
DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL,
@@ -2178,6 +2177,10 @@ void di_post_switch_buffer(
(di_buf0_mif->canvas0_addr2 << 16) |
(di_buf0_mif->canvas0_addr1 << 8) |
(di_buf0_mif->canvas0_addr0 << 0));
if (!di_ddr_en) {
DI_VSYNC_WR_MPEG_REG_BITS(VD1_IF0_GEN_REG,
0, 0, 1);
}
if (mc_enable) {
DI_VSYNC_WR_MPEG_REG_BITS(MCVECRD_CTRL1,
di_mcvecrd_mif->canvas_num, 16, 8);
@@ -2268,7 +2271,7 @@ void di_post_switch_buffer(
((blend_mode == 1?1:0) << 1) |
(ei_en << 2) | /* ei enable */
(blend_mtn_en << 3) | /* mtn line buffer enable */
(blend_mtn_en << 4) |/* mtnp read mif enable */
(blend_mtn_en << 4) |/* mtnp read mif enable */
(blend_en << 5) |
(1 << 6) | /* di mux output enable */
(di_ddr_en << 7) |/* di write to SDRAM enable.*/
@@ -2340,10 +2343,15 @@ void enable_di_post_2(
buf1_en = (!ei_only && (di_ddr_en || di_vpp_en));
if (ei_en || di_vpp_en || di_ddr_en) {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
set_di_if0_mif_g12(di_buf0_mif, di_vpp_en,
hold_line, vskip_cnt, di_ddr_en);
else
/* if di post vpp link disable vd1 for new if0 */
if (!di_ddr_en) {
DI_VSYNC_WR_MPEG_REG_BITS(VD1_IF0_GEN_REG,
0, 0, 1);
}
} else
set_di_if0_mif(di_buf0_mif, di_vpp_en,
hold_line, vskip_cnt, di_ddr_en);
}
@@ -2433,8 +2441,8 @@ void disable_post_deinterlace_2(void)
* Rd(DI_IF1_GEN_REG) & 0xfffffffe);
*/
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, 0, 8, 9);
DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, 0, 20, 1);
DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, 0, 8, 2);
DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, 0, 20, 2);
}
}
@@ -2455,7 +2463,20 @@ void enable_di_post_mif(enum gate_mode_e mode)
default:
gate = 0;
}
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
/* enable if0 external gate freerun hw issue */
DI_Wr_reg_bits(VIUB_GCLK_CTRL1, ((gate == 0)?2:gate), 2, 2);
/* enable if1 external gate freerun hw issue */
DI_Wr_reg_bits(VIUB_GCLK_CTRL1, ((gate == 0)?2:gate), 4, 2);
/* enable if1 external gate freerun hw issue */
DI_Wr_reg_bits(VIUB_GCLK_CTRL1, ((gate == 0)?2:gate), 6, 2);
/* enable di wr external gate */
DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 8, 2);
/* enable mtn rd external gate */
DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 10, 2);
/* enable mv rd external gate */
DI_Wr_reg_bits(VIUB_GCLK_CTRL1, gate, 12, 2);
} else if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXLX)) {
/* enable if1 external gate freerun hw issue */
DI_Wr_reg_bits(VIUB_GCLK_CTRL1, ((gate == 0)?2:gate), 2, 2);
/* enable if2 external gate freerun hw issue */

13
drivers/amlogic/media/video_sink/video.c
View File

@@ -2476,7 +2476,6 @@ static void vsync_toggle_frame(struct vframe_s *vf)
if (cur_dispbuf != &vf_local)
video_keeper_new_frame_notify();
}
static inline void vd1_path_select(bool afbc)
{
u32 misc_off = cur_dev->vpp_off;
@@ -2503,14 +2502,18 @@ static inline void vd1_path_select(bool afbc)
/* afbc0 gclk ctrl */
(0 << 0),
0, 22);
if ((DI_POST_REG_RD(DI_POST_CTRL) & 0x100) != 0)
if ((DI_POST_REG_RD(DI_POST_CTRL) & 0x100) != 0) {
VSYNC_WR_MPEG_REG_BITS(
VD1_AFBCD0_MISC_CTRL,
/* afbc0 to di */
(1 << 9) |
/* vd1 mif to di */
(1 << 8),
1,
8, 2);
VSYNC_WR_MPEG_REG_BITS(
VD1_AFBCD0_MISC_CTRL,
/* go field select di post */
1,
20, 2);
}
} else {
if ((DI_POST_REG_RD(DI_POST_CTRL) & 0x100) == 0)
VSYNC_WR_MPEG_REG_BITS(