net: rockchip_wlan: support rtl8723cs to "v5.12.2-6-g7dd36f8de.20201207_COEX20180330-1e00"

Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I236127e7d5aa5aed356a49b46d0cd47eb7e7de39
This commit is contained in:
Alex Zhao
2021-04-08 09:54:07 +08:00
committed by Tao Huang
parent b78f04564a
commit 5e5a7e0cfb
10 changed files with 6153 additions and 6125 deletions

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@@ -1032,6 +1032,9 @@ endif
endif
########### END OF PATH #################################
+EXTRA_CFLAGS += -DDBG_IO
#WIFIDBG
EXTRA_CFLAGS += -DDBG_C2H_MAC_HIDDEN_RPT_HANDLE
ifeq ($(CONFIG_AP_MODE), y)
EXTRA_CFLAGS += -DCONFIG_AP_MODE

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@@ -461,8 +461,7 @@ enum btc_wl2bt_scoreboard {
BTC_SCBD_TDMA = BIT(9),
BTC_SCBD_FIX2M = BIT(10),
BTC_SCBD_MAILBOX_DBG = BIT(14),
BTC_SCBD_ALL = 0xffff,
BTC_SCBD_ALL_32BIT = 0xffffffff
BTC_SCBD_ALL = 0xffffffff
};
enum btc_bt2wl_scoreboard {
@@ -545,9 +544,7 @@ static const char *const coex_mode_string[] = {
"5G",
"2G-P2P-GO",
"2G-P2P-GC",
"BT-MR",
"2G1RFREE",
"unknow"
"BT-MR"
};
enum btc_bt_state_cnt {
@@ -874,8 +871,6 @@ struct btc_coex_sta {
u16 bt_reg_rf_9;
u16 wl_txlimit;
u32 score_board_BW_32bit;
u32 score_board_WB_32bit;
u32 hi_pri_tx;
u32 hi_pri_rx;
u32 lo_pri_tx;
@@ -1485,24 +1480,13 @@ typedef u4Byte
IN PVOID pBtcContext,
IN u2Byte reg_addr
);
typedef u2Byte
(*BFP_BTC_R_SCBD)(
IN PVOID pBtcContext,
IN pu2Byte score_board_val
);
typedef u4Byte
(*BFP_BTC_R_SCBD_32BIT)(
(*BFP_BTC_R_SCBD)(
IN PVOID pBtcContext,
IN pu4Byte score_board_val
);
typedef VOID
(*BFP_BTC_W_SCBD)(
IN PVOID pBtcContext,
IN u2Byte bitpos,
IN BOOLEAN state
);
typedef VOID
(*BFP_BTC_W_SCBD_32BIT)(
IN PVOID pBtcContext,
IN u4Byte bitpos,
IN BOOLEAN state
@@ -1820,10 +1804,7 @@ struct btc_coexist {
BFP_BTC_R_LINDIRECT btc_read_linderct;
BFP_BTC_W_LINDIRECT btc_write_linderct;
BFP_BTC_R_SCBD btc_read_scbd;
BFP_BTC_R_SCBD_32BIT btc_read_scbd_32bit;
BFP_BTC_W_SCBD btc_write_scbd;
BFP_BTC_W_SCBD_32BIT btc_write_scbd_32bit;
/* read/write bb related */
BFP_BTC_SET_BB_REG btc_set_bb_reg;
BFP_BTC_GET_BB_REG btc_get_bb_reg;

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@@ -2329,23 +2329,7 @@ void halbtcoutsrc_WriteLIndirectReg(void *pBtcContext, u16 reg_addr, u32 bit_mas
}
}
u16 halbtcoutsrc_Read_scbd(void *pBtcContext, u16* score_board_val)
{
PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
struct btc_coex_sta *coex_sta = &btc->coex_sta;
const struct btc_chip_para *chip_para = btc->chip_para;
if (!chip_para->scbd_support)
return 0;
*score_board_val = (btc->btc_read_2byte(btc, chip_para->scbd_reg))
& 0x7fff;
coex_sta->score_board_BW = *score_board_val;
return coex_sta->score_board_BW;
}
u32 halbtcoutsrc_Read_scbd_32bit(void *pBtcContext, u32* score_board_val)
u32 halbtcoutsrc_Read_scbd(void *pBtcContext, u32* score_board_val)
{
PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
struct btc_coex_sta *coex_sta = &btc->coex_sta;
@@ -2356,17 +2340,18 @@ u32 halbtcoutsrc_Read_scbd_32bit(void *pBtcContext, u32* score_board_val)
*score_board_val = (btc->btc_read_4byte(btc, chip_para->scbd_reg))
& 0x7fffffff;
coex_sta->score_board_BW_32bit = *score_board_val;
coex_sta->score_board_BW = *score_board_val;
return coex_sta->score_board_BW_32bit;
return coex_sta->score_board_BW;
}
void halbtcoutsrc_Write_scbd(void *pBtcContext, u16 bitpos, u8 state)
void halbtcoutsrc_Write_scbd(void *pBtcContext, u32 bitpos, u8 state)
{
PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
struct btc_coex_sta *coex_sta = &btc->coex_sta;
const struct btc_chip_para *chip_para = btc->chip_para;
u16 val = 0x2;
u32 val = 0x2;
u8* btc_dbg_buf = &gl_btc_trace_buf[0];
if (!chip_para->scbd_support)
return;
@@ -2390,52 +2375,19 @@ void halbtcoutsrc_Write_scbd(void *pBtcContext, u16 bitpos, u8 state)
if (val != coex_sta->score_board_WB) {
coex_sta->score_board_WB = val;
val = val | 0x8000;
btc->btc_write_2byte(btc, chip_para->scbd_reg, val);
RTW_DBG("[BTC], write scoreboard 0x%x\n", val);
} else {
RTW_DBG("[BTC], return for nochange\n");
}
}
void halbtcoutsrc_Write_scbd_32bit(void *pBtcContext, u32 bitpos, u8 state)
{
PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
struct btc_coex_sta *coex_sta = &btc->coex_sta;
const struct btc_chip_para *chip_para = btc->chip_para;
u32 val = 0x2;
if (!chip_para->scbd_support)
return;
val = val | coex_sta->score_board_WB;
/* for 8822b, Scoreboard[10]: 0: CQDDR off, 1: CQDDR on
* for 8822c, Scoreboard[10]: 0: CQDDR on, 1:CQDDR fix 2M
*/
if (!btc->chip_para->new_scbd10_def && (bitpos & BTC_SCBD_FIX2M)) {
if (state)
val = val & (~BTC_SCBD_FIX2M);
if(chip_para->scbd_bit_num == BTC_SCBD_32_BIT)
val = val | 0x80000000;
else
val = val | BTC_SCBD_FIX2M;
} else {
if (state)
val = val | bitpos;
else
val = val & (~bitpos);
}
if (val != coex_sta->score_board_WB_32bit) {
coex_sta->score_board_WB_32bit = val;
val = val | 0x80000000;
val = val | 0x8000;
btc->btc_write_4byte(btc, chip_para->scbd_reg, val);
RTW_DBG("[BTC], write scoreboard 0x%x\n", val);
BTC_SPRINTF(btc_dbg_buf, BT_TMP_BUF_SIZE,
"[BTCoex], write scoreboard 0x%x\n", val);
} else {
RTW_DBG("[BTC], return for nochange\n");
BTC_SPRINTF(btc_dbg_buf, BT_TMP_BUF_SIZE,
"[BTCoex], %s: return for nochange\n", __func__);
}
}
@@ -3259,13 +3211,11 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)
pBtCoexist->chip_para = &btc_chip_para_8192f;
}
#endif
#ifdef PLATFORM_LINUX
#ifdef CONFIG_RTL8723F
else if (IS_HARDWARE_TYPE_8723F(padapter)) {
pBtCoexist->chip_type = BTC_CHIP_RTL8723F;
pBtCoexist->chip_para = &btc_chip_para_8723f;
}
#endif
#endif
else {
pBtCoexist->chip_type = BTC_CHIP_UNDEF;
@@ -3341,9 +3291,7 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)
pBtCoexist->btc_write_linderct = halbtcoutsrc_WriteLIndirectReg;
pBtCoexist->btc_read_scbd = halbtcoutsrc_Read_scbd;
pBtCoexist->btc_read_scbd_32bit = halbtcoutsrc_Read_scbd_32bit;
pBtCoexist->btc_write_scbd = halbtcoutsrc_Write_scbd;
pBtCoexist->btc_write_scbd_32bit = halbtcoutsrc_Write_scbd_32bit;
pBtCoexist->btc_set_bb_reg = halbtcoutsrc_SetBbReg;
pBtCoexist->btc_get_bb_reg = halbtcoutsrc_GetBbReg;

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@@ -1567,6 +1567,8 @@ int hal_read_mac_hidden_rpt(_adapter *adapter)
rtw_msleep_os(10);
} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
RTW_INFO("%s() delay patch\n", __func__);
rtw_msleep_os(1000);
if (id == C2H_MAC_HIDDEN_RPT) {
/* read data */
for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++)
@@ -1575,6 +1577,7 @@ int hal_read_mac_hidden_rpt(_adapter *adapter)
/* inform FW mac hidden rpt has read */
rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG);
RTW_INFO_DUMP("hal_read_mac_hidden_rpt\n", mac_hidden_rpt, MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN);
mac_hidden_rpt_hdl:
c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN);

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@@ -20,15 +20,15 @@
#ifdef LOAD_FW_HEADER_FROM_DRIVER
#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
extern u8 array_mp_8703b_fw_ap[19994];
extern u8 array_mp_8703b_fw_ap[20328];
extern u32 array_length_mp_8703b_fw_ap;
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
extern u8 array_mp_8703b_fw_nic[20290];
extern u8 array_mp_8703b_fw_nic[20614];
extern u32 array_length_mp_8703b_fw_nic;
#ifdef CONFIG_WOWLAN
extern u8 array_mp_8703b_fw_wowlan[23074];
extern u8 array_mp_8703b_fw_wowlan[23076];
extern u32 array_length_mp_8703b_fw_wowlan;
#endif /*CONFIG_WOWLAN*/
#endif

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@@ -1,3 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define DRIVERVERSION "v5.12.2-7-g2de5ec386.20201013_beta"
#define DRIVERVERSION "v5.12.2-6-g7dd36f8de.20201207_COEX20180330-1e00"
#define BTCOEXVERSION "COEX20180330-1e00"

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@@ -9823,6 +9823,11 @@ static int rtw_cfg80211_init_wiphy_band(_adapter *padapter, struct wiphy *wiphy)
rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_2_4G, rf_type);
#endif
}
else
{
RTW_INFO("%s: %d not supported24G mode: %d\n", __FUNCTION__, __LINE__, padapter->registrypriv.wireless_mode);
goto exit;
}
#if CONFIG_IEEE80211_BAND_5GHZ
if (is_supported_5g(padapter->registrypriv.wireless_mode)) {
band = wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(BAND_ON_5G);

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@@ -1158,6 +1158,7 @@ uint loadparam(_adapter *padapter)
uint status = _SUCCESS;
struct registry_priv *registry_par = &padapter->registrypriv;
_rtw_memset(&padapter->registrypriv, 0, sizeof(padapter->registrypriv));
#ifdef CONFIG_RTW_DEBUG
if (rtw_drv_log_level >= _DRV_MAX_)
@@ -1179,6 +1180,7 @@ uint loadparam(_adapter *padapter)
rtw_wireless_mode &= ~WIRELESS_11B;
#endif
registry_par->wireless_mode = (u8)rtw_wireless_mode;
RTW_INFO("%s:%d registry_par->wireless_mode:%d \n", __FUNCTION__, __LINE__, registry_par->wireless_mode);
if (IsSupported24G(registry_par->wireless_mode) && (!is_supported_5g(registry_par->wireless_mode))
&& (registry_par->channel > 14))

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@@ -1190,8 +1190,8 @@ extern int pm_netdev_close(struct net_device *pnetdev, u8 bnormal);
static int rtw_sdio_suspend(struct device *dev)
{
struct sdio_func *func = dev_to_sdio_func(dev);
struct dvobj_priv *psdpriv;
struct sdio_func *func = NULL;
struct dvobj_priv *psdpriv = NULL;
struct pwrctrl_priv *pwrpriv = NULL;
_adapter *padapter = NULL;
struct debug_priv *pdbgpriv = NULL;
@@ -1203,7 +1203,11 @@ static int rtw_sdio_suspend(struct device *dev)
#endif
if (dev == NULL)
goto exit;
goto exit_1;
func = dev_to_sdio_func(dev);
if(func == NULL)
goto exit_1;
psdpriv = sdio_get_drvdata(func);
if (psdpriv == NULL)
@@ -1225,6 +1229,7 @@ static int rtw_sdio_suspend(struct device *dev)
ret = rtw_suspend_common(padapter);
exit:
#ifdef CONFIG_RTW_SDIO_PM_KEEP_POWER
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
/* Android 4.0 don't support WIFI close power */
@@ -1240,12 +1245,12 @@ static int rtw_sdio_suspend(struct device *dev)
pdbgpriv->dbg_suspend_error_cnt++;
return -ENOSYS;
} else {
RTW_INFO("cmd: suspend with MMC_PM_KEEP_POWER\n");
RTW_ERR("cmd: suspend with MMC_PM_KEEP_POWER\n");
sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
}
#endif
#endif
exit:
exit_1:
return ret;
}
int rtw_resume_process(_adapter *padapter)