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rk29: L2 Data RAM latency set to 4 cycles, Tag RAM latency set to 3 cycles, suggested by zcs

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黄涛
2011-07-11 20:26:15 +08:00
parent ae71eb278d
commit 5ed7eccb31
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mm/proc-v7.S
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@@ -271,8 +271,8 @@ __v7_setup:
bic r5, r5, #1 << 29 @ L2 data RAM read multiplexer select: 0 = two cycles
bic r5, r5, #7 << 6
bic r5, r5, #15
orr r5, r5, #3 << 6 @ Tag RAM latency: b011 = 4 cycles
orr r5, r5, #4 @ Data RAM latency: b0100 = 5 cycles
orr r5, r5, #2 << 6 @ Tag RAM latency: b010 = 3 cycles
orr r5, r5, #3 @ Data RAM latency: b0011 = 4 cycles
mcr p15, 1, r5, c9, c0, 2
#endif